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Searched refs:hw (Results 1 – 25 of 236) sorted by relevance

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/linux-2.4.37.9/drivers/net/e1000/
De1000_hw.c37 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
38 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
39 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
40 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
41 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
42 static void e1000_release_software_semaphore(struct e1000_hw *hw);
44 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
45 static int32_t e1000_check_downshift(struct e1000_hw *hw);
46 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
[all …]
/linux-2.4.37.9/drivers/net/wan/
Dsdladrv.c176 static int sdla_detect (sdlahw_t* hw);
177 static int sdla_autodpm (sdlahw_t* hw);
178 static int sdla_setdpm (sdlahw_t* hw);
179 static int sdla_load (sdlahw_t* hw, sfm_t* sfm, unsigned len);
180 static int sdla_init (sdlahw_t* hw);
181 static unsigned long sdla_memtest (sdlahw_t* hw);
182 static int sdla_bootcfg (sdlahw_t* hw, sfm_info_t* sfminfo);
183 static unsigned char make_config_byte (sdlahw_t* hw);
184 static int sdla_start (sdlahw_t* hw, unsigned addr);
186 static int init_s502a (sdlahw_t* hw);
[all …]
/linux-2.4.37.9/drivers/net/wireless/
Dhermes.c72 #define IO_TYPE(hw) ((hw)->io_space ? "IO " : "MEM ") argument
73 #define DMSG(stuff...) do {printk(KERN_DEBUG "hermes @ %s0x%x: " , IO_TYPE(hw), hw->iobase); \
100 static int hermes_issue_cmd(hermes_t *hw, u16 cmd, u16 param0) in hermes_issue_cmd() argument
106 reg = hermes_read_regn(hw, CMD); in hermes_issue_cmd()
110 reg = hermes_read_regn(hw, CMD); in hermes_issue_cmd()
116 hermes_write_regn(hw, PARAM2, 0); in hermes_issue_cmd()
117 hermes_write_regn(hw, PARAM1, 0); in hermes_issue_cmd()
118 hermes_write_regn(hw, PARAM0, param0); in hermes_issue_cmd()
119 hermes_write_regn(hw, CMD, cmd); in hermes_issue_cmd()
128 void hermes_struct_init(hermes_t *hw, ulong address, in hermes_struct_init() argument
[all …]
Dhermes.h302 #define hermes_read_reg(hw, off) ((hw)->io_space ? \ argument
303 inw((hw)->iobase + ( (off) << (hw)->reg_spacing )) : \
304 readw((hw)->iobase + ( (off) << (hw)->reg_spacing )))
305 #define hermes_write_reg(hw, off, val) ((hw)->io_space ? \ argument
306 outw_p((val), (hw)->iobase + ( (off) << (hw)->reg_spacing )) : \
307 writew((val), (hw)->iobase + ( (off) << (hw)->reg_spacing )))
309 #define hermes_read_regn(hw, name) (hermes_read_reg((hw), HERMES_##name)) argument
310 #define hermes_write_regn(hw, name, val) (hermes_write_reg((hw), HERMES_##name, (val))) argument
313 void hermes_struct_init(hermes_t *hw, ulong address, int io_space, int reg_spacing);
314 int hermes_init(hermes_t *hw);
[all …]
/linux-2.4.37.9/drivers/net/
Dskge.c99 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
100 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103 static void yukon_init(struct skge_hw *hw, int port);
104 static void genesis_mac_init(struct skge_hw *hw, int port);
127 const void __iomem *io = skge->hw->regs; in skge_get_regs()
141 static u32 skge_supported_modes(const struct skge_hw *hw) in skge_supported_modes() argument
145 if (hw->copper) { in skge_supported_modes()
154 if (hw->chip_id == CHIP_ID_GENESIS) in skge_supported_modes()
160 else if (hw->chip_id == CHIP_ID_YUKON) in skge_supported_modes()
173 struct skge_hw *hw = skge->hw; in skge_get_settings() local
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Dsky2.c139 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) in gm_phy_write() argument
143 gma_write16(hw, port, GM_SMI_DATA, val); in gm_phy_write()
144 gma_write16(hw, port, GM_SMI_CTRL, in gm_phy_write()
148 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) in gm_phy_write()
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); in gm_phy_write()
157 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) in __gm_phy_read() argument
161 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) in __gm_phy_read()
165 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { in __gm_phy_read()
166 *val = gma_read16(hw, port, GM_SMI_DATA); in __gm_phy_read()
176 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) in gm_phy_read() argument
[all …]
/linux-2.4.37.9/drivers/isdn/hisax/
Dsedlbauer.c170 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset)); in ReadISAC()
176 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); in WriteISAC()
182 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); in ReadISACfifo()
188 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); in WriteISACfifo()
194 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset|0x80)); in ReadISAC_IPAC()
200 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset|0x80, value); in WriteISAC_IPAC()
206 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0x80, data, size); in ReadISACfifo_IPAC()
212 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0x80, data, size); in WriteISACfifo_IPAC()
218 return (readreg(cs->hw.sedl.adr, in ReadHSCX()
219 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
[all …]
Delsa.c194 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset)); in ReadISAC()
200 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); in WriteISAC()
206 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); in ReadISACfifo()
212 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); in WriteISACfifo()
218 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset+0x80)); in ReadISAC_IPAC()
224 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset|0x80, value); in WriteISAC_IPAC()
230 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0x80, data, size); in ReadISACfifo_IPAC()
236 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0x80, data, size); in WriteISACfifo_IPAC()
242 return (readreg(cs->hw.elsa.ale, in ReadHSCX()
243 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
[all …]
Dnetjet.c41 cs->hw.njet.auxd &= 0xfc; in NETjet_ReadIC()
42 cs->hw.njet.auxd |= (offset>>4) & 3; in NETjet_ReadIC()
43 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_ReadIC()
44 ret = bytein(cs->hw.njet.isac + ((offset & 0xf)<<2)); in NETjet_ReadIC()
56 cs->hw.njet.auxd &= 0xfc; in NETjet_WriteIC()
57 cs->hw.njet.auxd |= (offset>>4) & 3; in NETjet_WriteIC()
58 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_WriteIC()
59 byteout(cs->hw.njet.isac + ((offset & 0xf)<<2), value); in NETjet_WriteIC()
66 cs->hw.njet.auxd &= 0xfc; in NETjet_ReadICfifo()
67 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_ReadICfifo()
[all …]
Davm_a1.c60 return (readreg(cs->hw.avm.isac, offset)); in ReadISAC()
66 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
72 read_fifo(cs->hw.avm.isacfifo, data, size); in ReadISACfifo()
78 write_fifo(cs->hw.avm.isacfifo, data, size); in WriteISACfifo()
84 return (readreg(cs->hw.avm.hscx[hscx], offset)); in ReadHSCX()
90 writereg(cs->hw.avm.hscx[hscx], offset, value); in WriteHSCX()
97 #define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg)
98 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
99 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
100 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
[all …]
Dteles3.c60 return (readreg(cs->hw.teles3.isac, offset)); in ReadISAC()
66 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
72 read_fifo(cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
78 write_fifo(cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
84 return (readreg(cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
90 writereg(cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
97 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg)
98 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
99 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
100 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
[all …]
Denternow_pci.c90 return (InByte(cs->hw.njet.isac + 4*offset)); in ReadByteAmd7930()
94 OutByte(cs->hw.njet.isac + 4*AMD_CR, offset); in ReadByteAmd7930()
95 return(InByte(cs->hw.njet.isac + 4*AMD_DR)); in ReadByteAmd7930()
105 OutByte(cs->hw.njet.isac + 4*offset, value); in WriteByteAmd7930()
109 OutByte(cs->hw.njet.isac + 4*AMD_CR, offset); in WriteByteAmd7930()
110 OutByte(cs->hw.njet.isac + 4*AMD_DR, value); in WriteByteAmd7930()
118 OutByte(cs->hw.njet.base+NETJET_IRQMASK1, 0x00); in enpci_setIrqMask()
120 OutByte(cs->hw.njet.base+NETJET_IRQMASK1, TJ_AMD_IRQ); in enpci_setIrqMask()
149 cs->hw.njet.ctrl_reg = 0x07; in reset_enpci()
150 OutByte(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_enpci()
[all …]
Dasuscom.c95 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset)); in ReadISAC()
101 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); in WriteISAC()
107 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); in ReadISACfifo()
113 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); in WriteISACfifo()
119 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset|0x80)); in ReadISAC_IPAC()
125 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset|0x80, value); in WriteISAC_IPAC()
131 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0x80, data, size); in ReadISACfifo_IPAC()
137 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0x80, data, size); in WriteISACfifo_IPAC()
143 return (readreg(cs->hw.asus.adr, in ReadHSCX()
144 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
[all …]
Ddiva.c150 return(readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset)); in ReadISAC()
156 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); in WriteISAC()
162 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); in ReadISACfifo()
168 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); in WriteISACfifo()
174 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset+0x80)); in ReadISAC_IPAC()
180 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset|0x80, value); in WriteISAC_IPAC()
186 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size); in ReadISACfifo_IPAC()
192 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size); in WriteISACfifo_IPAC()
198 return(readreg(cs->hw.diva.hscx_adr, in ReadHSCX()
199 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
[all …]
Dsaphir.c84 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); in ReadISAC()
90 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); in WriteISAC()
96 readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in ReadISACfifo()
102 writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in WriteISACfifo()
108 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in ReadHSCX()
115 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in WriteHSCX()
119 #define READHSCX(cs, nr, reg) readreg(cs->hw.saphir.ale, \
120 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
121 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
122 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data)
[all …]
Dniccy.c99 return (readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset)); in ReadISAC()
105 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); in WriteISAC()
111 readfifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); in ReadISACfifo()
117 writefifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); in WriteISACfifo()
123 return (readreg(cs->hw.niccy.hscx_ale, in ReadHSCX()
124 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
130 writereg(cs->hw.niccy.hscx_ale, in WriteHSCX()
131 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
134 #define READHSCX(cs, nr, reg) readreg(cs->hw.niccy.hscx_ale, \
135 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0))
[all …]
Dteleint.c119 cs->hw.hfc.cip = offset; in ReadISAC()
120 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); in ReadISAC()
126 cs->hw.hfc.cip = offset; in WriteISAC()
127 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); in WriteISAC()
133 cs->hw.hfc.cip = 0; in ReadISACfifo()
134 readfifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); in ReadISACfifo()
140 cs->hw.hfc.cip = 0; in WriteISACfifo()
141 writefifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); in WriteISACfifo()
150 cs->hw.hfc.cip = reg; in ReadHFC()
151 byteout(cs->hw.hfc.addr | 1, reg); in ReadHFC()
[all …]
Ds0box.c109 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); in ReadISAC()
115 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); in WriteISAC()
121 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
127 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
133 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
139 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
146 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
147 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, d…
148 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr],…
149 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr…
[all …]
Dmic.c84 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset)); in ReadISAC()
90 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); in WriteISAC()
96 readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); in ReadISACfifo()
102 writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); in WriteISACfifo()
108 return (readreg(cs->hw.mic.adr, in ReadHSCX()
109 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0))); in ReadHSCX()
115 writereg(cs->hw.mic.adr, in WriteHSCX()
116 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
123 #define READHSCX(cs, nr, reg) readreg(cs->hw.mic.adr, \
124 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
[all …]
Dnj_u.c41 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) & in netjet_u_interrupt()
56 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < in netjet_u_interrupt()
57 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) in netjet_u_interrupt()
62 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < in netjet_u_interrupt()
63 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) in netjet_u_interrupt()
68 if (sval != cs->hw.njet.last_is0) /* we have a DMA interrupt */ in netjet_u_interrupt()
74 cs->hw.njet.irqstat0 = sval; in netjet_u_interrupt()
76 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != in netjet_u_interrupt()
77 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) in netjet_u_interrupt()
80 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != in netjet_u_interrupt()
[all …]
/linux-2.4.37.9/drivers/isdn/eicon/
Dbri.c76 DivasIOBase = UxCardMemAttach(card->hw, DIVAS_IOBASE); in diva_server_bri_reset()
78 UxCardPortIoOut(card->hw, DivasIOBase, REG_IOCTRL, 0); in diva_server_bri_reset()
83 UxCardPortIoOut(card->hw, DivasIOBase, REG_ADDRHI, 0); in diva_server_bri_reset()
84 UxCardPortIoOutW(card->hw, DivasIOBase, REG_ADDRLO, 0); in diva_server_bri_reset()
85 UxCardPortIoOutW(card->hw, DivasIOBase, REG_DATA , 0); in diva_server_bri_reset()
87 UxCardPortIoOut(card->hw, DivasIOBase, REG_ADDRHI, 0xFF); in diva_server_bri_reset()
88 UxCardPortIoOutW(card->hw, DivasIOBase, REG_ADDRLO, 0x0000); in diva_server_bri_reset()
92 UxCardPortIoOutW(card->hw, DivasIOBase, REG_DATA , 0); in diva_server_bri_reset()
98 UxCardMemDetach(card->hw, DivasIOBase); in diva_server_bri_reset()
108 DivasIOBase = UxCardMemAttach(card->hw, DIVAS_IOBASE); in diva_server_bri_reset_int()
[all …]
Dpri.c81 reg = UxCardMemAttach(card->hw, DIVAS_REG_MEMORY); in diva_server_reset()
83 UxCardMemOut(card->hw, &reg[DIVAS_RESET_REG], DIVAS_RESET | in diva_server_reset()
89 UxCardMemOut(card->hw, &reg[DIVAS_RESET_REG], 0x00); in diva_server_reset()
94 UxCardMemDetach(card->hw, reg); in diva_server_reset()
96 boot = UxCardMemAttach(card->hw, DIVAS_RAM_MEMORY); in diva_server_reset()
98 UxCardMemOutD(card->hw, boot->reserved, 0); in diva_server_reset()
100 live = UxCardMemInD(card->hw, &boot->live); in diva_server_reset()
104 if (live != UxCardMemInD(card->hw, &boot->live)) in diva_server_reset()
113 UxCardMemDetach(card->hw, boot); in diva_server_reset()
119 UxCardMemDetach(card->hw, boot); in diva_server_reset()
[all …]
/linux-2.4.37.9/drivers/video/intel/
Dintelfbhw.c375 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, in intelfbhw_read_hw_state() argument
382 if (!hw || !dinfo) in intelfbhw_read_hw_state()
386 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()
387 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()
388 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()
389 hw->dpll_a = INREG(DPLL_A); in intelfbhw_read_hw_state()
390 hw->dpll_b = INREG(DPLL_B); in intelfbhw_read_hw_state()
391 hw->fpa0 = INREG(FPA0); in intelfbhw_read_hw_state()
392 hw->fpa1 = INREG(FPA1); in intelfbhw_read_hw_state()
393 hw->fpb0 = INREG(FPB0); in intelfbhw_read_hw_state()
[all …]
/linux-2.4.37.9/drivers/video/matrox/
Dmatroxfb_DAC1064.c212 ACCESS_FBINFO(hw).DACclk[0] = m; in DAC1064_setpclk()
213 ACCESS_FBINFO(hw).DACclk[1] = n; in DAC1064_setpclk()
214 ACCESS_FBINFO(hw).DACclk[2] = p; in DAC1064_setpclk()
219 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); in DAC1064_setmclk() local
225 hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM); in DAC1064_setmclk()
226 hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN); in DAC1064_setmclk()
227 hw->DACclk[5] = inDAC1064(PMINFO DAC1064_XSYSPLLP); in DAC1064_setmclk()
230 mx = hw->MXoptionReg | 0x00000004; in DAC1064_setmclk()
258 outDAC1064(PMINFO DAC1064_XSYSPLLM, hw->DACclk[3] = m); in DAC1064_setmclk()
259 outDAC1064(PMINFO DAC1064_XSYSPLLN, hw->DACclk[4] = n); in DAC1064_setmclk()
[all …]
/linux-2.4.37.9/include/asm-arm/arch-sa1100/
Dide.h26 ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq) in ide_init_hwif_ports() argument
44 memset(hw, 0, sizeof(*hw)); in ide_init_hwif_ports()
49 hw->io_ports[i] = reg; in ide_init_hwif_ports()
53 hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port; in ide_init_hwif_ports()
71 hw_regs_t hw; in ide_init_default_hwifs() local
92 ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x40, PCMCIA_IO_0_BASE + 0x78, NULL); in ide_init_default_hwifs()
93 hw.irq = EMPEG_IRQ_IDE2; in ide_init_default_hwifs()
94 ide_register_hw(&hw, NULL); in ide_init_default_hwifs()
95 ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x00, PCMCIA_IO_0_BASE + 0x38, NULL); in ide_init_default_hwifs()
96 hw.irq = ,EMPEG_IRQ_IDE1; in ide_init_default_hwifs()
[all …]

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