Lines Matching refs:hw
99 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
100 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103 static void yukon_init(struct skge_hw *hw, int port);
104 static void genesis_mac_init(struct skge_hw *hw, int port);
127 const void __iomem *io = skge->hw->regs; in skge_get_regs()
141 static u32 skge_supported_modes(const struct skge_hw *hw) in skge_supported_modes() argument
145 if (hw->copper) { in skge_supported_modes()
154 if (hw->chip_id == CHIP_ID_GENESIS) in skge_supported_modes()
160 else if (hw->chip_id == CHIP_ID_YUKON) in skge_supported_modes()
173 struct skge_hw *hw = skge->hw; in skge_get_settings() local
176 ecmd->supported = skge_supported_modes(hw); in skge_get_settings()
178 if (hw->copper) { in skge_get_settings()
180 ecmd->phy_address = hw->phy_addr; in skge_get_settings()
194 const struct skge_hw *hw = skge->hw; in skge_set_settings() local
195 u32 supported = skge_supported_modes(hw); in skge_set_settings()
258 strcpy(info->bus_info, pci_name(skge->hw->pdev)); in skge_get_drvinfo()
302 if (skge->hw->chip_id == CHIP_ID_GENESIS) in skge_get_ethtool_stats()
317 if (skge->hw->chip_id == CHIP_ID_GENESIS) in skge_get_stats()
411 struct skge_hw *hw = skge->hw; in skge_set_sg() local
413 if (hw->chip_id == CHIP_ID_GENESIS && data) in skge_set_sg()
426 struct skge_hw *hw = skge->hw; in skge_set_tx_csum() local
428 if (hw->chip_id == CHIP_ID_GENESIS && data) in skge_set_tx_csum()
451 if (skge->hw->chip_id == CHIP_ID_GENESIS && data) in skge_set_rx_csum()
492 static inline u32 hwkhz(const struct skge_hw *hw) in hwkhz() argument
494 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; in hwkhz()
498 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) in skge_clk2usec() argument
500 return (ticks * 1000) / hwkhz(hw); in skge_clk2usec()
504 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) in skge_usecs2clk() argument
506 return hwkhz(hw) * usec / 1000; in skge_usecs2clk()
513 struct skge_hw *hw = skge->hw; in skge_get_coalesce() local
519 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { in skge_get_coalesce()
520 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); in skge_get_coalesce()
521 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_get_coalesce()
537 struct skge_hw *hw = skge->hw; in skge_set_coalesce() local
539 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_set_coalesce()
562 skge_write32(hw, B2_IRQM_MSK, msk); in skge_set_coalesce()
564 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); in skge_set_coalesce()
566 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); in skge_set_coalesce()
567 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_set_coalesce()
575 struct skge_hw *hw = skge->hw; in skge_led() local
578 spin_lock_bh(&hw->phy_lock); in skge_led()
579 if (hw->chip_id == CHIP_ID_GENESIS) { in skge_led()
582 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); in skge_led()
583 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); in skge_led()
584 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); in skge_led()
585 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); in skge_led()
589 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); in skge_led()
590 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); in skge_led()
592 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
593 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
598 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); in skge_led()
599 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); in skge_led()
600 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
602 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); in skge_led()
608 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
609 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
617 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, in skge_led()
623 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
629 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
638 spin_unlock_bh(&hw->phy_lock); in skge_led()
733 map = pci_map_single(skge->hw->pdev, skb->data, bufsize, in skge_rx_setup()
771 struct skge_hw *hw = skge->hw; in skge_rx_clean() local
780 pci_unmap_single(hw->pdev, in skge_rx_clean()
817 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), in skge_link_up()
837 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); in skge_link_down()
845 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __xm_phy_read() argument
849 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in __xm_phy_read()
850 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
853 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) in __xm_phy_read()
860 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
865 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) in xm_phy_read() argument
868 if (__xm_phy_read(hw, port, reg, &v)) in xm_phy_read()
870 hw->dev[port]->name); in xm_phy_read()
874 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in xm_phy_write() argument
878 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in xm_phy_write()
880 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
887 xm_write16(hw, port, XM_PHY_DATA, val); in xm_phy_write()
889 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
896 static void genesis_init(struct skge_hw *hw) in genesis_init() argument
899 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); in genesis_init()
900 skge_write8(hw, B2_BSC_CTRL, BSC_START); in genesis_init()
903 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_init()
906 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); in genesis_init()
907 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); in genesis_init()
908 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); in genesis_init()
909 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); in genesis_init()
911 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_init()
912 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_init()
913 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_init()
914 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_init()
917 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); in genesis_init()
918 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); in genesis_init()
919 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); in genesis_init()
920 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); in genesis_init()
921 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); in genesis_init()
924 static void genesis_reset(struct skge_hw *hw, int port) in genesis_reset() argument
928 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in genesis_reset()
931 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); in genesis_reset()
932 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ in genesis_reset()
933 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ in genesis_reset()
934 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ in genesis_reset()
935 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ in genesis_reset()
938 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); in genesis_reset()
940 xm_outhash(hw, port, XM_HSM, zero); in genesis_reset()
954 static void bcom_check_link(struct skge_hw *hw, int port) in bcom_check_link() argument
956 struct net_device *dev = hw->dev[port]; in bcom_check_link()
961 (void) xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
962 status = xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
965 u16 cmd = xm_read16(hw, port, XM_MMU_CMD); in bcom_check_link()
967 xm_write16(hw, port, XM_MMU_CMD, cmd); in bcom_check_link()
969 (void) xm_read16(hw, port, XM_MMU_CMD); in bcom_check_link()
976 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP); in bcom_check_link()
977 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); in bcom_check_link()
1028 struct skge_hw *hw = skge->hw; in bcom_phy_init() local
1048 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); in bcom_phy_init()
1051 r = xm_read16(hw, port, XM_MMU_CMD); in bcom_phy_init()
1053 xm_write16(hw, port, XM_MMU_CMD,r); in bcom_phy_init()
1062 xm_phy_write(hw, port, in bcom_phy_init()
1072 xm_phy_write(hw, port, in bcom_phy_init()
1081 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); in bcom_phy_init()
1083 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); in bcom_phy_init()
1086 xm_read16(hw, port, XM_ISRC); in bcom_phy_init()
1102 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); in bcom_phy_init()
1109 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); in bcom_phy_init()
1113 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, in bcom_phy_init()
1118 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in bcom_phy_init()
1125 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); in bcom_phy_init()
1126 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); in bcom_phy_init()
1129 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in bcom_phy_init()
1131 bcom_check_link(hw, port); in bcom_phy_init()
1134 static void genesis_mac_init(struct skge_hw *hw, int port) in genesis_mac_init() argument
1136 struct net_device *dev = hw->dev[port]; in genesis_mac_init()
1138 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; in genesis_mac_init()
1144 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in genesis_mac_init()
1146 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) in genesis_mac_init()
1155 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_mac_init()
1163 r = skge_read32(hw, B2_GP_IO); in genesis_mac_init()
1169 skge_write32(hw, B2_GP_IO, r); in genesis_mac_init()
1173 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); in genesis_mac_init()
1178 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in genesis_mac_init()
1182 xm_outaddr(hw, port, XM_EXM(i), zero); in genesis_mac_init()
1185 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1188 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1192 xm_write16(hw, port, XM_RX_HI_WM, 1450); in genesis_mac_init()
1207 xm_write16(hw, port, XM_RX_CMD, r); in genesis_mac_init()
1211 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); in genesis_mac_init()
1217 xm_write16(hw, port, XM_TX_THR, 512); in genesis_mac_init()
1233 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); in genesis_mac_init()
1241 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); in genesis_mac_init()
1248 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); in genesis_mac_init()
1251 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_mac_init()
1254 skge_write8(hw, B3_MA_TOINI_RX1, 72); in genesis_mac_init()
1255 skge_write8(hw, B3_MA_TOINI_RX2, 72); in genesis_mac_init()
1256 skge_write8(hw, B3_MA_TOINI_TX1, 72); in genesis_mac_init()
1257 skge_write8(hw, B3_MA_TOINI_TX2, 72); in genesis_mac_init()
1259 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_mac_init()
1260 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_mac_init()
1261 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_mac_init()
1262 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_mac_init()
1265 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1266 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); in genesis_mac_init()
1267 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1270 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1271 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); in genesis_mac_init()
1272 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1276 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); in genesis_mac_init()
1279 skge_write16(hw, B3_PA_CTRL, in genesis_mac_init()
1286 struct skge_hw *hw = skge->hw; in genesis_stop() local
1290 genesis_reset(hw, port); in genesis_stop()
1293 skge_write16(hw, B3_PA_CTRL, in genesis_stop()
1300 xm_write32(hw, port, XM_MODE, in genesis_stop()
1301 xm_read32(hw, port, XM_MODE)|XM_MD_FTF); in genesis_stop()
1305 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); in genesis_stop()
1308 reg = skge_read32(hw, B2_GP_IO); in genesis_stop()
1316 skge_write32(hw, B2_GP_IO, reg); in genesis_stop()
1317 skge_read32(hw, B2_GP_IO); in genesis_stop()
1319 xm_write16(hw, port, XM_MMU_CMD, in genesis_stop()
1320 xm_read16(hw, port, XM_MMU_CMD) in genesis_stop()
1323 xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1329 struct skge_hw *hw = skge->hw; in genesis_get_stats() local
1334 xm_write16(hw, port, in genesis_get_stats()
1338 while (xm_read16(hw, port, XM_STAT_CMD) in genesis_get_stats()
1346 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 in genesis_get_stats()
1347 | xm_read32(hw, port, XM_TXO_OK_LO); in genesis_get_stats()
1348 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 in genesis_get_stats()
1349 | xm_read32(hw, port, XM_RXO_OK_LO); in genesis_get_stats()
1352 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); in genesis_get_stats()
1355 static void genesis_mac_intr(struct skge_hw *hw, int port) in genesis_mac_intr() argument
1357 struct skge_port *skge = netdev_priv(hw->dev[port]); in genesis_mac_intr()
1358 u16 status = xm_read16(hw, port, XM_ISRC); in genesis_mac_intr()
1365 xm_write32(hw, port, XM_MODE, XM_MD_FTF); in genesis_mac_intr()
1369 xm_write32(hw, port, XM_MODE, XM_MD_FRF); in genesis_mac_intr()
1376 struct skge_hw *hw = skge->hw; in genesis_link_up() local
1381 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1395 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_link_up()
1397 mode = xm_read32(hw, port, XM_MODE); in genesis_link_up()
1411 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); in genesis_link_up()
1414 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); in genesis_link_up()
1423 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); in genesis_link_up()
1426 xm_write32(hw, port, XM_MODE, mode); in genesis_link_up()
1432 xm_write16(hw, port, XM_IMSK, msk); in genesis_link_up()
1433 xm_read16(hw, port, XM_ISRC); in genesis_link_up()
1436 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1444 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in genesis_link_up()
1445 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) in genesis_link_up()
1447 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in genesis_link_up()
1450 xm_write16(hw, port, XM_MMU_CMD, in genesis_link_up()
1458 struct skge_hw *hw = skge->hw; in bcom_phy_intr() local
1462 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); in bcom_phy_intr()
1469 hw->dev[port]->name); in bcom_phy_intr()
1475 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); in bcom_phy_intr()
1476 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1478 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1483 bcom_check_link(hw, port); in bcom_phy_intr()
1487 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in gm_phy_write() argument
1491 gma_write16(hw, port, GM_SMI_DATA, val); in gm_phy_write()
1492 gma_write16(hw, port, GM_SMI_CTRL, in gm_phy_write()
1493 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); in gm_phy_write()
1497 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) in gm_phy_write()
1502 hw->dev[port]->name); in gm_phy_write()
1506 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __gm_phy_read() argument
1510 gma_write16(hw, port, GM_SMI_CTRL, in __gm_phy_read()
1511 GM_SMI_CT_PHY_AD(hw->phy_addr) in __gm_phy_read()
1516 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) in __gm_phy_read()
1522 *val = gma_read16(hw, port, GM_SMI_DATA); in __gm_phy_read()
1526 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) in gm_phy_read() argument
1529 if (__gm_phy_read(hw, port, reg, &v)) in gm_phy_read()
1531 hw->dev[port]->name); in gm_phy_read()
1536 static void yukon_init(struct skge_hw *hw, int port) in yukon_init() argument
1538 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_init()
1542 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); in yukon_init()
1550 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); in yukon_init()
1553 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_init()
1558 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
1565 if (hw->copper) { in yukon_init()
1605 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); in yukon_init()
1607 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); in yukon_init()
1608 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
1612 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); in yukon_init()
1614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_init()
1617 static void yukon_reset(struct skge_hw *hw, int port) in yukon_reset() argument
1619 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ in yukon_reset()
1620 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ in yukon_reset()
1621 gma_write16(hw, port, GM_MC_ADDR_H2, 0); in yukon_reset()
1622 gma_write16(hw, port, GM_MC_ADDR_H3, 0); in yukon_reset()
1623 gma_write16(hw, port, GM_MC_ADDR_H4, 0); in yukon_reset()
1625 gma_write16(hw, port, GM_RX_CTRL, in yukon_reset()
1626 gma_read16(hw, port, GM_RX_CTRL) in yukon_reset()
1631 static int is_yukon_lite_a0(struct skge_hw *hw) in is_yukon_lite_a0() argument
1636 if (hw->chip_id != CHIP_ID_YUKON) in is_yukon_lite_a0()
1639 reg = skge_read32(hw, B2_FAR); in is_yukon_lite_a0()
1640 skge_write8(hw, B2_FAR + 3, 0xff); in is_yukon_lite_a0()
1641 ret = (skge_read8(hw, B2_FAR + 3) != 0); in is_yukon_lite_a0()
1642 skge_write32(hw, B2_FAR, reg); in is_yukon_lite_a0()
1646 static void yukon_mac_init(struct skge_hw *hw, int port) in yukon_mac_init() argument
1648 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_mac_init()
1651 const u8 *addr = hw->dev[port]->dev_addr; in yukon_mac_init()
1654 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
1655 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
1656 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
1658 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
1662 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_mac_init()
1663 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_mac_init()
1666 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
1667 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
1668 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
1671 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
1677 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; in yukon_mac_init()
1680 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); in yukon_mac_init()
1681 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); in yukon_mac_init()
1682 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); in yukon_mac_init()
1686 gma_write16(hw, port, GM_GP_CTRL, in yukon_mac_init()
1687 gma_read16(hw, port, GM_GP_CTRL) | reg); in yukon_mac_init()
1710 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_mac_init()
1718 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_mac_init()
1719 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_init()
1721 yukon_init(hw, port); in yukon_mac_init()
1724 reg = gma_read16(hw, port, GM_PHY_ADDR); in yukon_mac_init()
1725 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); in yukon_mac_init()
1728 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); in yukon_mac_init()
1729 gma_write16(hw, port, GM_PHY_ADDR, reg); in yukon_mac_init()
1732 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in yukon_mac_init()
1735 gma_write16(hw, port, GM_RX_CTRL, in yukon_mac_init()
1739 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); in yukon_mac_init()
1742 gma_write16(hw, port, GM_TX_PARAM, in yukon_mac_init()
1749 if (hw->dev[port]->mtu > 1500) in yukon_mac_init()
1752 gma_write16(hw, port, GM_SERIAL_MODE, reg); in yukon_mac_init()
1755 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); in yukon_mac_init()
1757 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); in yukon_mac_init()
1760 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); in yukon_mac_init()
1761 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); in yukon_mac_init()
1762 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); in yukon_mac_init()
1767 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); in yukon_mac_init()
1771 if (is_yukon_lite_a0(hw)) in yukon_mac_init()
1774 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
1775 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); in yukon_mac_init()
1781 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); in yukon_mac_init()
1784 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
1785 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); in yukon_mac_init()
1789 static void yukon_suspend(struct skge_hw *hw, int port) in yukon_suspend() argument
1793 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in yukon_suspend()
1795 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in yukon_suspend()
1797 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
1799 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
1802 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
1804 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
1809 struct skge_hw *hw = skge->hw; in yukon_stop() local
1812 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in yukon_stop()
1813 yukon_reset(hw, port); in yukon_stop()
1815 gma_write16(hw, port, GM_GP_CTRL, in yukon_stop()
1816 gma_read16(hw, port, GM_GP_CTRL) in yukon_stop()
1818 gma_read16(hw, port, GM_GP_CTRL); in yukon_stop()
1820 yukon_suspend(hw, port); in yukon_stop()
1823 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_stop()
1824 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_stop()
1829 struct skge_hw *hw = skge->hw; in yukon_get_stats() local
1833 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 in yukon_get_stats()
1834 | gma_read32(hw, port, GM_TXO_OK_LO); in yukon_get_stats()
1835 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 in yukon_get_stats()
1836 | gma_read32(hw, port, GM_RXO_OK_LO); in yukon_get_stats()
1839 data[i] = gma_read32(hw, port, in yukon_get_stats()
1843 static void yukon_mac_intr(struct skge_hw *hw, int port) in yukon_mac_intr() argument
1845 struct net_device *dev = hw->dev[port]; in yukon_mac_intr()
1847 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_intr()
1855 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in yukon_mac_intr()
1860 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in yukon_mac_intr()
1865 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) in yukon_speed() argument
1879 struct skge_hw *hw = skge->hw; in yukon_link_up() local
1884 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); in yukon_link_up()
1886 reg = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_up()
1892 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_link_up()
1894 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_link_up()
1900 struct skge_hw *hw = skge->hw; in yukon_link_down() local
1904 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); in yukon_link_down()
1906 ctrl = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_down()
1908 gma_write16(hw, port, GM_GP_CTRL, ctrl); in yukon_link_down()
1912 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, in yukon_link_down()
1913 gm_phy_read(hw, port, in yukon_link_down()
1919 yukon_reset(hw, port); in yukon_link_down()
1922 yukon_init(hw, port); in yukon_link_down()
1927 struct skge_hw *hw = skge->hw; in yukon_phy_intr() local
1932 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); in yukon_phy_intr()
1933 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); in yukon_phy_intr()
1940 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) in yukon_phy_intr()
1946 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { in yukon_phy_intr()
1958 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
1977 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_phy_intr()
1979 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in yukon_phy_intr()
1985 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2005 struct skge_hw *hw = skge->hw; in skge_phy_reset() local
2011 spin_lock_bh(&hw->phy_lock); in skge_phy_reset()
2012 if (hw->chip_id == CHIP_ID_GENESIS) { in skge_phy_reset()
2013 genesis_reset(hw, port); in skge_phy_reset()
2014 genesis_mac_init(hw, port); in skge_phy_reset()
2016 yukon_reset(hw, port); in skge_phy_reset()
2017 yukon_init(hw, port); in skge_phy_reset()
2019 spin_unlock_bh(&hw->phy_lock); in skge_phy_reset()
2027 struct skge_hw *hw = skge->hw; in skge_ioctl() local
2036 data->phy_id = hw->phy_addr; in skge_ioctl()
2041 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2042 if (hw->chip_id == CHIP_ID_GENESIS) in skge_ioctl()
2043 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2045 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2046 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2055 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2056 if (hw->chip_id == CHIP_ID_GENESIS) in skge_ioctl()
2057 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2060 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2062 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2068 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) in skge_ramset() argument
2076 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2077 skge_write32(hw, RB_ADDR(q, RB_START), start); in skge_ramset()
2078 skge_write32(hw, RB_ADDR(q, RB_WP), start); in skge_ramset()
2079 skge_write32(hw, RB_ADDR(q, RB_RP), start); in skge_ramset()
2080 skge_write32(hw, RB_ADDR(q, RB_END), end); in skge_ramset()
2084 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), in skge_ramset()
2086 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), in skge_ramset()
2092 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2095 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2102 struct skge_hw *hw = skge->hw; in skge_qset() local
2107 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) in skge_qset()
2110 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset()
2111 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset()
2112 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset()
2113 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset()
2119 struct skge_hw *hw = skge->hw; in skge_up() local
2137 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); in skge_up()
2168 spin_lock_bh(&hw->phy_lock); in skge_up()
2169 if (hw->chip_id == CHIP_ID_GENESIS) in skge_up()
2170 genesis_mac_init(hw, port); in skge_up()
2172 yukon_mac_init(hw, port); in skge_up()
2173 spin_unlock_bh(&hw->phy_lock); in skge_up()
2176 chunk = hw->ram_size / ((hw->ports + 1)*2); in skge_up()
2177 ram_addr = hw->ram_offset + 2 * chunk * port; in skge_up()
2179 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); in skge_up()
2183 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); in skge_up()
2188 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2197 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); in skge_up()
2206 struct skge_hw *hw = skge->hw; in skge_down() local
2217 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); in skge_down()
2218 if (hw->chip_id == CHIP_ID_GENESIS) in skge_down()
2224 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2225 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2230 skge_write8(hw, SK_REG(port, TXA_CTRL), in skge_down()
2234 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); in skge_down()
2235 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); in skge_down()
2238 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2239 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2242 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
2244 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2245 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_down()
2247 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2249 if (hw->chip_id == CHIP_ID_GENESIS) { in skge_down()
2250 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2251 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2253 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2254 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2264 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); in skge_down()
2278 struct skge_hw *hw = skge->hw; in skge_xmit_frame() local
2303 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); in skge_xmit_frame()
2317 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) in skge_xmit_frame()
2337 map = pci_map_page(hw->pdev, frag->page, frag->page_offset, in skge_xmit_frame()
2359 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame()
2383 struct pci_dev *pdev = skge->hw->pdev; in skge_tx_free()
2432 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); in skge_tx_timeout()
2462 struct skge_hw *hw = skge->hw; in genesis_set_multicast() local
2469 mode = xm_read32(hw, port, XM_MODE); in genesis_set_multicast()
2488 xm_write32(hw, port, XM_MODE, mode); in genesis_set_multicast()
2489 xm_outhash(hw, port, XM_HSM, filter); in genesis_set_multicast()
2495 struct skge_hw *hw = skge->hw; in yukon_set_multicast() local
2503 reg = gma_read16(hw, port, GM_RX_CTRL); in yukon_set_multicast()
2523 gma_write16(hw, port, GM_MC_ADDR_H1, in yukon_set_multicast()
2525 gma_write16(hw, port, GM_MC_ADDR_H2, in yukon_set_multicast()
2527 gma_write16(hw, port, GM_MC_ADDR_H3, in yukon_set_multicast()
2529 gma_write16(hw, port, GM_MC_ADDR_H4, in yukon_set_multicast()
2532 gma_write16(hw, port, GM_RX_CTRL, reg); in yukon_set_multicast()
2535 static inline u16 phy_length(const struct skge_hw *hw, u32 status) in phy_length() argument
2537 if (hw->chip_id == CHIP_ID_GENESIS) in phy_length()
2543 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) in bad_phy_status() argument
2545 if (hw->chip_id == CHIP_ID_GENESIS) in bad_phy_status()
2574 if (bad_phy_status(skge->hw, status)) in skge_rx_get()
2577 if (phy_length(skge->hw, status) != len) in skge_rx_get()
2586 pci_dma_sync_single_for_cpu(skge->hw->pdev, in skge_rx_get()
2590 pci_dma_sync_single_for_device(skge->hw->pdev, in skge_rx_get()
2601 pci_unmap_single(skge->hw->pdev, in skge_rx_get()
2627 if (skge->hw->chip_id == CHIP_ID_GENESIS) { in skge_rx_get()
2678 struct skge_hw *hw = skge->hw; in skge_poll() local
2708 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); in skge_poll()
2718 spin_lock_irq(&hw->hw_lock); in skge_poll()
2719 hw->intr_mask |= rxirqmask[skge->port]; in skge_poll()
2720 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_poll()
2721 skge_read32(hw, B0_IMSK); in skge_poll()
2723 spin_unlock_irq(&hw->hw_lock); in skge_poll()
2731 static void skge_mac_parity(struct skge_hw *hw, int port) in skge_mac_parity() argument
2733 struct net_device *dev = hw->dev[port]; in skge_mac_parity()
2740 if (hw->chip_id == CHIP_ID_GENESIS) in skge_mac_parity()
2741 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in skge_mac_parity()
2745 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), in skge_mac_parity()
2746 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in skge_mac_parity()
2750 static void skge_mac_intr(struct skge_hw *hw, int port) in skge_mac_intr() argument
2752 if (hw->chip_id == CHIP_ID_GENESIS) in skge_mac_intr()
2753 genesis_mac_intr(hw, port); in skge_mac_intr()
2755 yukon_mac_intr(hw, port); in skge_mac_intr()
2759 static void skge_error_irq(struct skge_hw *hw) in skge_error_irq() argument
2761 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
2763 if (hw->chip_id == CHIP_ID_GENESIS) { in skge_error_irq()
2766 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); in skge_error_irq()
2768 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); in skge_error_irq()
2772 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in skge_error_irq()
2777 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); in skge_error_irq()
2782 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); in skge_error_irq()
2786 skge_mac_parity(hw, 0); in skge_error_irq()
2789 skge_mac_parity(hw, 1); in skge_error_irq()
2793 hw->dev[0]->name); in skge_error_irq()
2794 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); in skge_error_irq()
2799 hw->dev[1]->name); in skge_error_irq()
2800 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); in skge_error_irq()
2806 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd); in skge_error_irq()
2807 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); in skge_error_irq()
2810 pci_name(hw->pdev), pci_cmd, pci_status); in skge_error_irq()
2814 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_error_irq()
2815 pci_write_config_word(hw->pdev, PCI_COMMAND, in skge_error_irq()
2817 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status); in skge_error_irq()
2818 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_error_irq()
2821 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
2824 hw->intr_mask &= ~IS_HW_ERR; in skge_error_irq()
2836 struct skge_hw *hw = (void *) arg; in skge_phytask() local
2839 for (port = 0; port < hw->ports; port++) { in skge_phytask()
2840 struct net_device *dev = hw->dev[port]; in skge_phytask()
2844 if (hw->chip_id != CHIP_ID_GENESIS) in skge_phytask()
2850 spin_unlock(&hw->phy_lock); in skge_phytask()
2852 spin_lock_irq(&hw->hw_lock); in skge_phytask()
2853 hw->intr_mask |= IS_EXT_REG; in skge_phytask()
2854 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_phytask()
2855 spin_unlock_irq(&hw->hw_lock); in skge_phytask()
2860 struct skge_hw *hw = dev_id; in skge_intr() local
2864 status = skge_read32(hw, B0_SP_ISRC); in skge_intr()
2869 spin_lock(&hw->hw_lock); in skge_intr()
2870 status &= hw->intr_mask; in skge_intr()
2872 hw->intr_mask &= ~IS_EXT_REG; in skge_intr()
2873 tasklet_schedule(&hw->phy_task); in skge_intr()
2877 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F); in skge_intr()
2878 skge_txirq(hw->dev[0]); in skge_intr()
2882 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F); in skge_intr()
2883 hw->intr_mask &= ~IS_R1_F; in skge_intr()
2884 netif_rx_schedule(hw->dev[0]); in skge_intr()
2888 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); in skge_intr()
2891 struct skge_port *skge = netdev_priv(hw->dev[0]); in skge_intr()
2894 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); in skge_intr()
2899 skge_mac_intr(hw, 0); in skge_intr()
2901 if (hw->dev[1]) { in skge_intr()
2903 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F); in skge_intr()
2904 skge_txirq(hw->dev[1]); in skge_intr()
2908 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F); in skge_intr()
2909 hw->intr_mask &= ~IS_R2_F; in skge_intr()
2910 netif_rx_schedule(hw->dev[1]); in skge_intr()
2914 struct skge_port *skge = netdev_priv(hw->dev[1]); in skge_intr()
2916 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); in skge_intr()
2920 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); in skge_intr()
2923 skge_mac_intr(hw, 1); in skge_intr()
2927 skge_error_irq(hw); in skge_intr()
2929 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_intr()
2930 spin_unlock(&hw->hw_lock); in skge_intr()
2941 skge_intr(dev->irq, skge->hw, NULL); in skge_netpoll()
2949 struct skge_hw *hw = skge->hw; in skge_set_mac_address() local
2956 spin_lock_bh(&hw->phy_lock); in skge_set_mac_address()
2958 memcpy_toio(hw->regs + B2_MAC_1 + port*8, in skge_set_mac_address()
2960 memcpy_toio(hw->regs + B2_MAC_2 + port*8, in skge_set_mac_address()
2963 if (hw->chip_id == CHIP_ID_GENESIS) in skge_set_mac_address()
2964 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in skge_set_mac_address()
2966 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); in skge_set_mac_address()
2967 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); in skge_set_mac_address()
2969 spin_unlock_bh(&hw->phy_lock); in skge_set_mac_address()
2984 static const char *skge_board_name(const struct skge_hw *hw) in skge_board_name() argument
2990 if (skge_chips[i].id == hw->chip_id) in skge_board_name()
2993 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); in skge_board_name()
3002 static int skge_reset(struct skge_hw *hw) in skge_reset() argument
3009 ctst = skge_read16(hw, B0_CTST); in skge_reset()
3012 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_reset()
3013 skge_write8(hw, B0_CTST, CS_RST_CLR); in skge_reset()
3016 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3017 skge_write8(hw, B2_TST_CTRL2, 0); in skge_reset()
3019 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); in skge_reset()
3020 pci_write_config_word(hw->pdev, PCI_STATUS, in skge_reset()
3022 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3023 skge_write8(hw, B0_CTST, CS_MRST_CLR); in skge_reset()
3026 skge_write16(hw, B0_CTST, in skge_reset()
3029 hw->chip_id = skge_read8(hw, B2_CHIP_ID); in skge_reset()
3030 phy_type = skge_read8(hw, B2_E_1) & 0xf; in skge_reset()
3031 pmd_type = skge_read8(hw, B2_PMD_TYP); in skge_reset()
3032 hw->copper = (pmd_type == 'T' || pmd_type == '1'); in skge_reset()
3034 switch (hw->chip_id) { in skge_reset()
3038 hw->phy_addr = PHY_ADDR_BCOM; in skge_reset()
3042 pci_name(hw->pdev), phy_type); in skge_reset()
3051 hw->copper = 1; in skge_reset()
3053 hw->phy_addr = PHY_ADDR_MARV; in skge_reset()
3058 pci_name(hw->pdev), hw->chip_id); in skge_reset()
3062 mac_cfg = skge_read8(hw, B2_MAC_CFG); in skge_reset()
3063 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; in skge_reset()
3064 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; in skge_reset()
3067 t8 = skge_read8(hw, B2_E_0); in skge_reset()
3068 if (hw->chip_id == CHIP_ID_GENESIS) { in skge_reset()
3071 hw->ram_size = 0x100000; in skge_reset()
3072 hw->ram_offset = 0x80000; in skge_reset()
3074 hw->ram_size = t8 * 512; in skge_reset()
3077 hw->ram_size = 0x20000; in skge_reset()
3079 hw->ram_size = t8 * 4096; in skge_reset()
3081 spin_lock_init(&hw->hw_lock); in skge_reset()
3082 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1; in skge_reset()
3083 if (hw->ports > 1) in skge_reset()
3084 hw->intr_mask |= IS_PORT_2; in skge_reset()
3086 if (hw->chip_id == CHIP_ID_GENESIS) in skge_reset()
3087 genesis_init(hw); in skge_reset()
3090 skge_write8(hw, B0_POWER_CTRL, in skge_reset()
3094 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && in skge_reset()
3095 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { in skge_reset()
3097 hw->intr_mask &= ~IS_HW_ERR; in skge_reset()
3101 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3102 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); in skge_reset()
3104 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); in skge_reset()
3105 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3108 for (i = 0; i < hw->ports; i++) { in skge_reset()
3109 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); in skge_reset()
3110 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_reset()
3115 skge_write8(hw, B2_TI_CTRL, TIM_STOP); in skge_reset()
3116 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); in skge_reset()
3117 skge_write8(hw, B0_LED, LED_STAT_ON); in skge_reset()
3120 for (i = 0; i < hw->ports; i++) in skge_reset()
3121 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); in skge_reset()
3124 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); in skge_reset()
3126 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); in skge_reset()
3127 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); in skge_reset()
3128 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); in skge_reset()
3129 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); in skge_reset()
3130 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); in skge_reset()
3131 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); in skge_reset()
3132 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); in skge_reset()
3133 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); in skge_reset()
3134 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); in skge_reset()
3135 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); in skge_reset()
3136 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); in skge_reset()
3137 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); in skge_reset()
3139 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); in skge_reset()
3144 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); in skge_reset()
3145 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); in skge_reset()
3146 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_reset()
3148 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_reset()
3150 spin_lock_bh(&hw->phy_lock); in skge_reset()
3151 for (i = 0; i < hw->ports; i++) { in skge_reset()
3152 if (hw->chip_id == CHIP_ID_GENESIS) in skge_reset()
3153 genesis_reset(hw, i); in skge_reset()
3155 yukon_reset(hw, i); in skge_reset()
3157 spin_unlock_bh(&hw->phy_lock); in skge_reset()
3163 static struct net_device *skge_devinit(struct skge_hw *hw, int port, in skge_devinit() argument
3175 SET_NETDEV_DEV(dev, &hw->pdev->dev); in skge_devinit()
3181 if (hw->chip_id == CHIP_ID_GENESIS) in skge_devinit()
3196 dev->irq = hw->pdev->irq; in skge_devinit()
3202 skge->hw = hw; in skge_devinit()
3212 skge->advertising = skge_supported_modes(hw); in skge_devinit()
3214 hw->dev[port] = dev; in skge_devinit()
3220 if (hw->chip_id != CHIP_ID_GENESIS) in skge_devinit()
3224 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); in skge_devinit()
3248 struct skge_hw *hw; in skge_probe() local
3293 hw = kmalloc(sizeof(*hw), GFP_KERNEL); in skge_probe()
3294 if (!hw) { in skge_probe()
3299 memset(hw, 0, sizeof(*hw)); in skge_probe()
3301 hw->pdev = pdev; in skge_probe()
3302 spin_lock_init(&hw->phy_lock); in skge_probe()
3303 tasklet_init(&hw->phy_task, skge_phytask, (unsigned long) hw); in skge_probe()
3305 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); in skge_probe()
3306 if (!hw->regs) { in skge_probe()
3313 DRV_NAME, hw); in skge_probe()
3319 pci_set_drvdata(pdev, hw); in skge_probe()
3321 err = skge_reset(hw); in skge_probe()
3327 pdev->irq, skge_board_name(hw), hw->chip_rev); in skge_probe()
3329 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL) in skge_probe()
3349 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { in skge_probe()
3355 hw->dev[1] = NULL; in skge_probe()
3365 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_probe()
3367 free_irq(pdev->irq, hw); in skge_probe()
3369 iounmap(hw->regs); in skge_probe()
3371 kfree(hw); in skge_probe()
3383 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_remove() local
3386 if (!hw) in skge_remove()
3389 if ((dev1 = hw->dev[1])) in skge_remove()
3391 dev0 = hw->dev[0]; in skge_remove()
3394 spin_lock_irq(&hw->hw_lock); in skge_remove()
3395 hw->intr_mask = 0; in skge_remove()
3396 skge_write32(hw, B0_IMSK, 0); in skge_remove()
3397 spin_unlock_irq(&hw->hw_lock); in skge_remove()
3399 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_remove()
3400 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_remove()
3402 tasklet_disable(&hw->phy_task); in skge_remove()
3404 free_irq(pdev->irq, hw); in skge_remove()
3411 iounmap(hw->regs); in skge_remove()
3412 kfree(hw); in skge_remove()