Lines Matching refs:hw
375 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, in intelfbhw_read_hw_state() argument
382 if (!hw || !dinfo) in intelfbhw_read_hw_state()
386 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()
387 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()
388 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()
389 hw->dpll_a = INREG(DPLL_A); in intelfbhw_read_hw_state()
390 hw->dpll_b = INREG(DPLL_B); in intelfbhw_read_hw_state()
391 hw->fpa0 = INREG(FPA0); in intelfbhw_read_hw_state()
392 hw->fpa1 = INREG(FPA1); in intelfbhw_read_hw_state()
393 hw->fpb0 = INREG(FPB0); in intelfbhw_read_hw_state()
394 hw->fpb1 = INREG(FPB1); in intelfbhw_read_hw_state()
402 hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); in intelfbhw_read_hw_state()
403 hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); in intelfbhw_read_hw_state()
410 hw->htotal_a = INREG(HTOTAL_A); in intelfbhw_read_hw_state()
411 hw->hblank_a = INREG(HBLANK_A); in intelfbhw_read_hw_state()
412 hw->hsync_a = INREG(HSYNC_A); in intelfbhw_read_hw_state()
413 hw->vtotal_a = INREG(VTOTAL_A); in intelfbhw_read_hw_state()
414 hw->vblank_a = INREG(VBLANK_A); in intelfbhw_read_hw_state()
415 hw->vsync_a = INREG(VSYNC_A); in intelfbhw_read_hw_state()
416 hw->src_size_a = INREG(SRC_SIZE_A); in intelfbhw_read_hw_state()
417 hw->bclrpat_a = INREG(BCLRPAT_A); in intelfbhw_read_hw_state()
418 hw->htotal_b = INREG(HTOTAL_B); in intelfbhw_read_hw_state()
419 hw->hblank_b = INREG(HBLANK_B); in intelfbhw_read_hw_state()
420 hw->hsync_b = INREG(HSYNC_B); in intelfbhw_read_hw_state()
421 hw->vtotal_b = INREG(VTOTAL_B); in intelfbhw_read_hw_state()
422 hw->vblank_b = INREG(VBLANK_B); in intelfbhw_read_hw_state()
423 hw->vsync_b = INREG(VSYNC_B); in intelfbhw_read_hw_state()
424 hw->src_size_b = INREG(SRC_SIZE_B); in intelfbhw_read_hw_state()
425 hw->bclrpat_b = INREG(BCLRPAT_B); in intelfbhw_read_hw_state()
430 hw->adpa = INREG(ADPA); in intelfbhw_read_hw_state()
431 hw->dvoa = INREG(DVOA); in intelfbhw_read_hw_state()
432 hw->dvob = INREG(DVOB); in intelfbhw_read_hw_state()
433 hw->dvoc = INREG(DVOC); in intelfbhw_read_hw_state()
434 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); in intelfbhw_read_hw_state()
435 hw->dvob_srcdim = INREG(DVOB_SRCDIM); in intelfbhw_read_hw_state()
436 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); in intelfbhw_read_hw_state()
437 hw->lvds = INREG(LVDS); in intelfbhw_read_hw_state()
442 hw->pipe_a_conf = INREG(PIPEACONF); in intelfbhw_read_hw_state()
443 hw->pipe_b_conf = INREG(PIPEBCONF); in intelfbhw_read_hw_state()
444 hw->disp_arb = INREG(DISPARB); in intelfbhw_read_hw_state()
449 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); in intelfbhw_read_hw_state()
450 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); in intelfbhw_read_hw_state()
451 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); in intelfbhw_read_hw_state()
452 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); in intelfbhw_read_hw_state()
458 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); in intelfbhw_read_hw_state()
459 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); in intelfbhw_read_hw_state()
465 hw->cursor_size = INREG(CURSOR_SIZE); in intelfbhw_read_hw_state()
470 hw->disp_a_ctrl = INREG(DSPACNTR); in intelfbhw_read_hw_state()
471 hw->disp_b_ctrl = INREG(DSPBCNTR); in intelfbhw_read_hw_state()
472 hw->disp_a_base = INREG(DSPABASE); in intelfbhw_read_hw_state()
473 hw->disp_b_base = INREG(DSPBBASE); in intelfbhw_read_hw_state()
474 hw->disp_a_stride = INREG(DSPASTRIDE); in intelfbhw_read_hw_state()
475 hw->disp_b_stride = INREG(DSPBSTRIDE); in intelfbhw_read_hw_state()
480 hw->vgacntrl = INREG(VGACNTRL); in intelfbhw_read_hw_state()
485 hw->add_id = INREG(ADD_ID); in intelfbhw_read_hw_state()
491 hw->swf0x[i] = INREG(SWF00 + (i << 2)); in intelfbhw_read_hw_state()
492 hw->swf1x[i] = INREG(SWF10 + (i << 2)); in intelfbhw_read_hw_state()
494 hw->swf3x[i] = INREG(SWF30 + (i << 2)); in intelfbhw_read_hw_state()
498 hw->fence[i] = INREG(FENCE + (i << 2)); in intelfbhw_read_hw_state()
500 hw->instpm = INREG(INSTPM); in intelfbhw_read_hw_state()
501 hw->mem_mode = INREG(MEM_MODE); in intelfbhw_read_hw_state()
502 hw->fw_blc_0 = INREG(FW_BLC_0); in intelfbhw_read_hw_state()
503 hw->fw_blc_1 = INREG(FW_BLC_1); in intelfbhw_read_hw_state()
510 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) in intelfbhw_print_hw_state() argument
517 if (!hw || !dinfo) in intelfbhw_print_hw_state()
521 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); in intelfbhw_print_hw_state()
522 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); in intelfbhw_print_hw_state()
523 printk(" VGAPD: 0x%08x\n", hw->vga_pd); in intelfbhw_print_hw_state()
524 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
525 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
526 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
527 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2) in intelfbhw_print_hw_state()
530 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_print_hw_state()
531 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_print_hw_state()
536 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
537 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
538 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
539 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2) in intelfbhw_print_hw_state()
542 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_print_hw_state()
543 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_print_hw_state()
548 printk(" DPLL_A: 0x%08x\n", hw->dpll_a); in intelfbhw_print_hw_state()
549 printk(" DPLL_B: 0x%08x\n", hw->dpll_b); in intelfbhw_print_hw_state()
550 printk(" FPA0: 0x%08x\n", hw->fpa0); in intelfbhw_print_hw_state()
551 printk(" FPA1: 0x%08x\n", hw->fpa1); in intelfbhw_print_hw_state()
552 printk(" FPB0: 0x%08x\n", hw->fpb0); in intelfbhw_print_hw_state()
553 printk(" FPB1: 0x%08x\n", hw->fpb1); in intelfbhw_print_hw_state()
555 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
556 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
557 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
558 if (hw->dpll_a & DPLL_P1_FORCE_DIV2) in intelfbhw_print_hw_state()
561 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_print_hw_state()
562 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_print_hw_state()
567 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
568 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
569 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
570 if (hw->dpll_a & DPLL_P1_FORCE_DIV2) in intelfbhw_print_hw_state()
573 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_print_hw_state()
574 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_print_hw_state()
582 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]; in intelfbhw_print_hw_state()
585 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]; in intelfbhw_print_hw_state()
588 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); in intelfbhw_print_hw_state()
589 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); in intelfbhw_print_hw_state()
590 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); in intelfbhw_print_hw_state()
591 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); in intelfbhw_print_hw_state()
592 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); in intelfbhw_print_hw_state()
593 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); in intelfbhw_print_hw_state()
594 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); in intelfbhw_print_hw_state()
595 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); in intelfbhw_print_hw_state()
596 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); in intelfbhw_print_hw_state()
597 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); in intelfbhw_print_hw_state()
598 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); in intelfbhw_print_hw_state()
599 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); in intelfbhw_print_hw_state()
600 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); in intelfbhw_print_hw_state()
601 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); in intelfbhw_print_hw_state()
602 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); in intelfbhw_print_hw_state()
603 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); in intelfbhw_print_hw_state()
605 printk(" ADPA: 0x%08x\n", hw->adpa); in intelfbhw_print_hw_state()
606 printk(" DVOA: 0x%08x\n", hw->dvoa); in intelfbhw_print_hw_state()
607 printk(" DVOB: 0x%08x\n", hw->dvob); in intelfbhw_print_hw_state()
608 printk(" DVOC: 0x%08x\n", hw->dvoc); in intelfbhw_print_hw_state()
609 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); in intelfbhw_print_hw_state()
610 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); in intelfbhw_print_hw_state()
611 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); in intelfbhw_print_hw_state()
612 printk(" LVDS: 0x%08x\n", hw->lvds); in intelfbhw_print_hw_state()
614 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); in intelfbhw_print_hw_state()
615 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); in intelfbhw_print_hw_state()
616 printk(" DISPARB: 0x%08x\n", hw->disp_arb); in intelfbhw_print_hw_state()
618 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); in intelfbhw_print_hw_state()
619 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); in intelfbhw_print_hw_state()
620 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); in intelfbhw_print_hw_state()
621 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); in intelfbhw_print_hw_state()
625 printk("0x%08x", hw->cursor_a_palette[i]); in intelfbhw_print_hw_state()
632 printk("0x%08x", hw->cursor_b_palette[i]); in intelfbhw_print_hw_state()
638 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); in intelfbhw_print_hw_state()
640 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); in intelfbhw_print_hw_state()
641 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); in intelfbhw_print_hw_state()
642 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); in intelfbhw_print_hw_state()
643 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); in intelfbhw_print_hw_state()
644 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); in intelfbhw_print_hw_state()
645 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); in intelfbhw_print_hw_state()
647 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); in intelfbhw_print_hw_state()
648 printk(" ADD_ID: 0x%08x\n", hw->add_id); in intelfbhw_print_hw_state()
652 hw->swf0x[i]); in intelfbhw_print_hw_state()
656 hw->swf1x[i]); in intelfbhw_print_hw_state()
660 hw->swf3x[i]); in intelfbhw_print_hw_state()
664 hw->fence[i]); in intelfbhw_print_hw_state()
666 printk(" INSTPM 0x%08x\n", hw->instpm); in intelfbhw_print_hw_state()
667 printk(" MEM_MODE 0x%08x\n", hw->mem_mode); in intelfbhw_print_hw_state()
668 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); in intelfbhw_print_hw_state()
669 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); in intelfbhw_print_hw_state()
830 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, in intelfbhw_mode_to_hw() argument
847 hw->vgacntrl |= VGA_DISABLE; in intelfbhw_mode_to_hw()
850 if (hw->pipe_a_conf & PIPECONF_ENABLE) in intelfbhw_mode_to_hw()
852 else if (hw->pipe_b_conf & PIPECONF_ENABLE) in intelfbhw_mode_to_hw()
857 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
858 fp0 = &hw->fpb0; in intelfbhw_mode_to_hw()
859 fp1 = &hw->fpb1; in intelfbhw_mode_to_hw()
860 hs = &hw->hsync_b; in intelfbhw_mode_to_hw()
861 hb = &hw->hblank_b; in intelfbhw_mode_to_hw()
862 ht = &hw->htotal_b; in intelfbhw_mode_to_hw()
863 vs = &hw->vsync_b; in intelfbhw_mode_to_hw()
864 vb = &hw->vblank_b; in intelfbhw_mode_to_hw()
865 vt = &hw->vtotal_b; in intelfbhw_mode_to_hw()
866 ss = &hw->src_size_b; in intelfbhw_mode_to_hw()
867 pipe_conf = &hw->pipe_b_conf; in intelfbhw_mode_to_hw()
869 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
870 fp0 = &hw->fpa0; in intelfbhw_mode_to_hw()
871 fp1 = &hw->fpa1; in intelfbhw_mode_to_hw()
872 hs = &hw->hsync_a; in intelfbhw_mode_to_hw()
873 hb = &hw->hblank_a; in intelfbhw_mode_to_hw()
874 ht = &hw->htotal_a; in intelfbhw_mode_to_hw()
875 vs = &hw->vsync_a; in intelfbhw_mode_to_hw()
876 vb = &hw->vblank_a; in intelfbhw_mode_to_hw()
877 vt = &hw->vtotal_a; in intelfbhw_mode_to_hw()
878 ss = &hw->src_size_a; in intelfbhw_mode_to_hw()
879 pipe_conf = &hw->pipe_a_conf; in intelfbhw_mode_to_hw()
883 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; in intelfbhw_mode_to_hw()
890 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | in intelfbhw_mode_to_hw()
892 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | in intelfbhw_mode_to_hw()
896 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); in intelfbhw_mode_to_hw()
897 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); in intelfbhw_mode_to_hw()
900 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; in intelfbhw_mode_to_hw()
901 hw->adpa |= ADPA_DPMS_D0; in intelfbhw_mode_to_hw()
936 hw->dvob &= ~PORT_ENABLE; in intelfbhw_mode_to_hw()
937 hw->dvoc &= ~PORT_ENABLE; in intelfbhw_mode_to_hw()
940 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; in intelfbhw_mode_to_hw()
941 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; in intelfbhw_mode_to_hw()
942 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; in intelfbhw_mode_to_hw()
945 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; in intelfbhw_mode_to_hw()
948 hw->disp_a_ctrl |= DISPPLANE_15_16BPP; in intelfbhw_mode_to_hw()
951 hw->disp_a_ctrl |= DISPPLANE_16BPP; in intelfbhw_mode_to_hw()
954 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; in intelfbhw_mode_to_hw()
957 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_mode_to_hw()
958 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); in intelfbhw_mode_to_hw()
1037 hw->disp_a_stride = dinfo->pitch; in intelfbhw_mode_to_hw()
1039 hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8; in intelfbhw_mode_to_hw()
1040 DBG_MSG("pitch is %d\n", hw->disp_a_stride); in intelfbhw_mode_to_hw()
1042 hw->disp_a_base = hw->disp_a_stride * var->yoffset + in intelfbhw_mode_to_hw()
1046 if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) { in intelfbhw_mode_to_hw()
1048 hw->disp_a_stride, STRIDE_ALIGNMENT); in intelfbhw_mode_to_hw()
1060 const struct intelfb_hwstate *hw, int blank) in intelfbhw_program_mode() argument
1081 if (hw->pipe_a_conf & PIPECONF_ENABLE) in intelfbhw_program_mode()
1083 else if (hw->pipe_b_conf & PIPECONF_ENABLE) in intelfbhw_program_mode()
1089 dpll = &hw->dpll_b; in intelfbhw_program_mode()
1090 fp0 = &hw->fpb0; in intelfbhw_program_mode()
1091 fp1 = &hw->fpb1; in intelfbhw_program_mode()
1092 pipe_conf = &hw->pipe_b_conf; in intelfbhw_program_mode()
1093 hs = &hw->hsync_b; in intelfbhw_program_mode()
1094 hb = &hw->hblank_b; in intelfbhw_program_mode()
1095 ht = &hw->htotal_b; in intelfbhw_program_mode()
1096 vs = &hw->vsync_b; in intelfbhw_program_mode()
1097 vb = &hw->vblank_b; in intelfbhw_program_mode()
1098 vt = &hw->vtotal_b; in intelfbhw_program_mode()
1099 ss = &hw->src_size_b; in intelfbhw_program_mode()
1112 dpll = &hw->dpll_a; in intelfbhw_program_mode()
1113 fp0 = &hw->fpa0; in intelfbhw_program_mode()
1114 fp1 = &hw->fpa1; in intelfbhw_program_mode()
1115 pipe_conf = &hw->pipe_a_conf; in intelfbhw_program_mode()
1116 hs = &hw->hsync_a; in intelfbhw_program_mode()
1117 hb = &hw->hblank_a; in intelfbhw_program_mode()
1118 ht = &hw->htotal_a; in intelfbhw_program_mode()
1119 vs = &hw->vsync_a; in intelfbhw_program_mode()
1120 vb = &hw->vblank_a; in intelfbhw_program_mode()
1121 vt = &hw->vtotal_a; in intelfbhw_program_mode()
1122 ss = &hw->src_size_a; in intelfbhw_program_mode()
1178 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); in intelfbhw_program_mode()
1195 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); in intelfbhw_program_mode()
1196 OUTREG(DSPASTRIDE, hw->disp_a_stride); in intelfbhw_program_mode()
1197 OUTREG(DSPABASE, hw->disp_a_base); in intelfbhw_program_mode()
1204 OUTREG(DSPABASE, hw->disp_a_base); in intelfbhw_program_mode()