Lines Matching refs:hw
90 return (InByte(cs->hw.njet.isac + 4*offset)); in ReadByteAmd7930()
94 OutByte(cs->hw.njet.isac + 4*AMD_CR, offset); in ReadByteAmd7930()
95 return(InByte(cs->hw.njet.isac + 4*AMD_DR)); in ReadByteAmd7930()
105 OutByte(cs->hw.njet.isac + 4*offset, value); in WriteByteAmd7930()
109 OutByte(cs->hw.njet.isac + 4*AMD_CR, offset); in WriteByteAmd7930()
110 OutByte(cs->hw.njet.isac + 4*AMD_DR, value); in WriteByteAmd7930()
118 OutByte(cs->hw.njet.base+NETJET_IRQMASK1, 0x00); in enpci_setIrqMask()
120 OutByte(cs->hw.njet.base+NETJET_IRQMASK1, TJ_AMD_IRQ); in enpci_setIrqMask()
149 cs->hw.njet.ctrl_reg = 0x07; in reset_enpci()
150 OutByte(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_enpci()
155 cs->hw.njet.ctrl_reg = 0x70; in reset_enpci()
156 OutByte(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_enpci()
161 cs->hw.njet.auxd = 0; // LED-status in reset_enpci()
162 cs->hw.njet.dmactrl = 0; in reset_enpci()
163 OutByte(cs->hw.njet.base + NETJET_AUXCTRL, ~TJ_AMD_IRQ); in reset_enpci()
164 OutByte(cs->hw.njet.base + NETJET_IRQMASK1, TJ_AMD_IRQ); in reset_enpci()
165 OutByte(cs->hw.njet.auxa, cs->hw.njet.auxd); // LED off in reset_enpci()
194 cs->hw.njet.auxd = TJ_AMD_IRQ << 1; in enpci_card_msg()
195 OutByte(cs->hw.njet.base + NETJET_AUXDATA, cs->hw.njet.auxd); in enpci_card_msg()
199 cs->hw.njet.auxd = 0; in enpci_card_msg()
200 OutByte(cs->hw.njet.base + NETJET_AUXDATA, 0x00); in enpci_card_msg()
211 cs->hw.njet.auxd |= TJ_AMD_IRQ << 2; in enpci_card_msg()
212 OutByte(cs->hw.njet.base + NETJET_AUXDATA, cs->hw.njet.auxd); in enpci_card_msg()
224 cs->hw.njet.auxd &= ~(TJ_AMD_IRQ << 2); in enpci_card_msg()
225 OutByte(cs->hw.njet.base + NETJET_AUXDATA, cs->hw.njet.auxd); in enpci_card_msg()
249 sval = InByte(cs->hw.njet.base + NETJET_IRQSTAT1); in enpci_interrupt()
264 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < in enpci_interrupt()
265 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) in enpci_interrupt()
270 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < in enpci_interrupt()
271 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) in enpci_interrupt()
276 if (sval != cs->hw.njet.last_is0) /* we have a DMA interrupt */ in enpci_interrupt()
282 cs->hw.njet.irqstat0 = sval; in enpci_interrupt()
284 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != in enpci_interrupt()
285 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) in enpci_interrupt()
288 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != in enpci_interrupt()
289 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) in enpci_interrupt()
334 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); in setup_enternow_pci()
335 if (!cs->hw.njet.base) { in setup_enternow_pci()
351 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; in setup_enternow_pci()
352 cs->hw.njet.isac = cs->hw.njet.base + 0xC0; // Fenster zum AMD in setup_enternow_pci()
358 cs->hw.njet.ctrl_reg = 0x07; // ge�ndert von 0xff in setup_enternow_pci()
359 OutByte(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in setup_enternow_pci()
365 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */ in setup_enternow_pci()
366 OutByte(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in setup_enternow_pci()
373 cs->hw.njet.auxd = 0x00; // war 0xc0 in setup_enternow_pci()
374 cs->hw.njet.dmactrl = 0; in setup_enternow_pci()
376 OutByte(cs->hw.njet.base + NETJET_AUXCTRL, ~TJ_AMD_IRQ); in setup_enternow_pci()
377 OutByte(cs->hw.njet.base + NETJET_IRQMASK1, TJ_AMD_IRQ); in setup_enternow_pci()
378 OutByte(cs->hw.njet.auxa, cs->hw.njet.auxd); in setup_enternow_pci()
394 cs->hw.njet.base, cs->irq); in setup_enternow_pci()
395 if (check_region(cs->hw.njet.base, bytecnt)) { in setup_enternow_pci()
399 cs->hw.njet.base, in setup_enternow_pci()
400 cs->hw.njet.base + bytecnt); in setup_enternow_pci()
403 request_region(cs->hw.njet.base, bytecnt, "Fn_ISDN"); in setup_enternow_pci()
406 cs->hw.njet.last_is0 = 0; in setup_enternow_pci()