Lines Matching refs:hw
139 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) in gm_phy_write() argument
143 gma_write16(hw, port, GM_SMI_DATA, val); in gm_phy_write()
144 gma_write16(hw, port, GM_SMI_CTRL, in gm_phy_write()
148 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) in gm_phy_write()
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); in gm_phy_write()
157 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) in __gm_phy_read() argument
161 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) in __gm_phy_read()
165 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { in __gm_phy_read()
166 *val = gma_read16(hw, port, GM_SMI_DATA); in __gm_phy_read()
176 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) in gm_phy_read() argument
180 if (__gm_phy_read(hw, port, reg, &v) != 0) in gm_phy_read()
181 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); in gm_phy_read()
185 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) in sky2_set_power_state() argument
192 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_set_power_state()
194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); in sky2_set_power_state()
195 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && in sky2_set_power_state()
198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); in sky2_set_power_state()
206 sky2_write8(hw, B0_POWER_CTRL, in sky2_set_power_state()
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in sky2_set_power_state()
212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) in sky2_set_power_state()
214 sky2_write8(hw, B2_Y2_CLK_GATE, in sky2_set_power_state()
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0); in sky2_set_power_state()
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); in sky2_set_power_state()
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { in sky2_set_power_state()
228 if (hw->ports > 1) in sky2_set_power_state()
232 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { in sky2_set_power_state()
233 sky2_pci_write32(hw, PCI_DEV_REG3, 0); in sky2_set_power_state()
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); in sky2_set_power_state()
236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1); in sky2_set_power_state()
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0); in sky2_set_power_state()
240 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); in sky2_set_power_state()
248 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); in sky2_set_power_state()
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) in sky2_set_power_state()
253 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); in sky2_set_power_state()
256 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) in sky2_set_power_state()
257 sky2_write8(hw, B2_Y2_CLK_GATE, 0); in sky2_set_power_state()
260 sky2_write8(hw, B2_Y2_CLK_GATE, in sky2_set_power_state()
267 sky2_write8(hw, B0_POWER_CTRL, in sky2_set_power_state()
275 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); in sky2_set_power_state()
276 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in sky2_set_power_state()
279 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) in sky2_phy_reset() argument
284 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in sky2_phy_reset()
286 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); in sky2_phy_reset()
288 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ in sky2_phy_reset()
289 gma_write16(hw, port, GM_MC_ADDR_H2, 0); in sky2_phy_reset()
290 gma_write16(hw, port, GM_MC_ADDR_H3, 0); in sky2_phy_reset()
291 gma_write16(hw, port, GM_MC_ADDR_H4, 0); in sky2_phy_reset()
293 reg = gma_read16(hw, port, GM_RX_CTRL); in sky2_phy_reset()
295 gma_write16(hw, port, GM_RX_CTRL, reg); in sky2_phy_reset()
298 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) in sky2_phy_init() argument
300 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); in sky2_phy_init()
304 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { in sky2_phy_init()
305 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); in sky2_phy_init()
311 if (hw->chip_id == CHIP_ID_YUKON_EC) in sky2_phy_init()
316 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); in sky2_phy_init()
319 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in sky2_phy_init()
320 if (hw->copper) { in sky2_phy_init()
321 if (hw->chip_id == CHIP_ID_YUKON_FE) { in sky2_phy_init()
332 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { in sky2_phy_init()
337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in sky2_phy_init()
343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in sky2_phy_init()
345 if (hw->chip_id == CHIP_ID_YUKON_XL) { in sky2_phy_init()
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); in sky2_phy_init()
348 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in sky2_phy_init()
351 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in sky2_phy_init()
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); in sky2_phy_init()
358 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in sky2_phy_init()
365 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in sky2_phy_init()
372 if (hw->copper) { in sky2_phy_init()
417 if (hw->chip_id != CHIP_ID_YUKON_FE) in sky2_phy_init()
418 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); in sky2_phy_init()
420 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); in sky2_phy_init()
421 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in sky2_phy_init()
427 switch (hw->chip_id) { in sky2_phy_init()
432 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); in sky2_phy_init()
438 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); in sky2_phy_init()
442 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_phy_init()
445 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); in sky2_phy_init()
448 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, in sky2_phy_init()
455 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, in sky2_phy_init()
464 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_phy_init()
467 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_phy_init()
470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); in sky2_phy_init()
473 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, in sky2_phy_init()
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, in sky2_phy_init()
483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_phy_init()
493 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) { in sky2_phy_init()
495 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_phy_init()
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); in sky2_phy_init()
499 gm_phy_write(hw, port, 0x18, 0xaa99); in sky2_phy_init()
500 gm_phy_write(hw, port, 0x17, 0x2011); in sky2_phy_init()
503 gm_phy_write(hw, port, 0x18, 0xa204); in sky2_phy_init()
504 gm_phy_write(hw, port, 0x17, 0x2002); in sky2_phy_init()
507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_phy_init()
509 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); in sky2_phy_init()
517 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); in sky2_phy_init()
522 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); in sky2_phy_init()
524 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); in sky2_phy_init()
531 sky2_phy_init(sky2->hw, sky2->port); in sky2_phy_reinit()
535 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) in sky2_mac_init() argument
537 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); in sky2_mac_init()
540 const u8 *addr = hw->dev[port]->dev_addr; in sky2_mac_init()
542 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in sky2_mac_init()
543 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); in sky2_mac_init()
545 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
547 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { in sky2_mac_init()
550 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
552 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); in sky2_mac_init()
553 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
554 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || in sky2_mac_init()
555 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || in sky2_mac_init()
556 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); in sky2_mac_init()
560 reg = gma_read16(hw, port, GM_GP_CTRL); in sky2_mac_init()
562 gma_write16(hw, port, GM_GP_CTRL, reg); in sky2_mac_init()
563 gma_read16(hw, port, GM_GP_CTRL); in sky2_mac_init()
584 hw->chip_id != CHIP_ID_YUKON_EC_U) in sky2_mac_init()
590 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in sky2_mac_init()
598 gma_write16(hw, port, GM_GP_CTRL, reg); in sky2_mac_init()
600 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); in sky2_mac_init()
603 sky2_phy_init(hw, port); in sky2_mac_init()
607 reg = gma_read16(hw, port, GM_PHY_ADDR); in sky2_mac_init()
608 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); in sky2_mac_init()
611 gma_read16(hw, port, i); in sky2_mac_init()
612 gma_write16(hw, port, GM_PHY_ADDR, reg); in sky2_mac_init()
615 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in sky2_mac_init()
618 gma_write16(hw, port, GM_RX_CTRL, in sky2_mac_init()
622 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); in sky2_mac_init()
625 gma_write16(hw, port, GM_TX_PARAM, in sky2_mac_init()
635 if (hw->dev[port]->mtu > ETH_DATA_LEN) in sky2_mac_init()
638 gma_write16(hw, port, GM_SERIAL_MODE, reg); in sky2_mac_init()
641 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); in sky2_mac_init()
644 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); in sky2_mac_init()
647 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); in sky2_mac_init()
648 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); in sky2_mac_init()
649 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); in sky2_mac_init()
652 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); in sky2_mac_init()
653 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), in sky2_mac_init()
657 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); in sky2_mac_init()
662 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); in sky2_mac_init()
665 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); in sky2_mac_init()
666 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); in sky2_mac_init()
668 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { in sky2_mac_init()
669 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); in sky2_mac_init()
670 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); in sky2_mac_init()
671 if (hw->dev[port]->mtu > ETH_DATA_LEN) { in sky2_mac_init()
673 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); in sky2_mac_init()
675 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); in sky2_mac_init()
685 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) in sky2_ramset() argument
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in sky2_ramset()
693 sky2_write32(hw, RB_ADDR(q, RB_START), start); in sky2_ramset()
694 sky2_write32(hw, RB_ADDR(q, RB_END), end); in sky2_ramset()
695 sky2_write32(hw, RB_ADDR(q, RB_WP), start); in sky2_ramset()
696 sky2_write32(hw, RB_ADDR(q, RB_RP), start); in sky2_ramset()
706 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); in sky2_ramset()
707 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); in sky2_ramset()
710 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); in sky2_ramset()
711 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); in sky2_ramset()
716 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in sky2_ramset()
719 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in sky2_ramset()
720 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); in sky2_ramset()
724 static void sky2_qset(struct sky2_hw *hw, u16 q) in sky2_qset() argument
726 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); in sky2_qset()
727 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); in sky2_qset()
728 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); in sky2_qset()
729 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); in sky2_qset()
735 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, in sky2_prefetch_init() argument
738 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); in sky2_prefetch_init()
739 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); in sky2_prefetch_init()
740 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); in sky2_prefetch_init()
741 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); in sky2_prefetch_init()
742 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); in sky2_prefetch_init()
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); in sky2_prefetch_init()
745 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); in sky2_prefetch_init()
757 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) in sky2_put_idx() argument
760 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); in sky2_put_idx()
761 sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)); in sky2_put_idx()
814 sky2_write32(sky2->hw, in rx_set_checksum()
832 struct sky2_hw *hw = sky2->hw; in sky2_rx_stop() local
837 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); in sky2_rx_stop()
840 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) in sky2_rx_stop()
841 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) in sky2_rx_stop()
847 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); in sky2_rx_stop()
850 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); in sky2_rx_stop()
863 pci_unmap_single(sky2->hw->pdev, in sky2_rx_clean()
877 struct sky2_hw *hw = sky2->hw; in sky2_ioctl() local
893 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); in sky2_ioctl()
905 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, in sky2_ioctl()
941 struct sky2_hw *hw = sky2->hw; in sky2_rx_start() local
947 sky2_qset(hw, rxq); in sky2_rx_start()
949 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { in sky2_rx_start()
951 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); in sky2_rx_start()
954 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); in sky2_rx_start()
964 re->mapaddr = pci_map_single(hw->pdev, re->skb->data, in sky2_rx_start()
978 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); in sky2_rx_start()
980 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); in sky2_rx_start()
981 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); in sky2_rx_start()
986 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); in sky2_rx_start()
997 struct sky2_hw *hw = sky2->hw; in sky2_up() local
1001 struct net_device *otherdev = hw->dev[sky2->port^1]; in sky2_up()
1008 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { in sky2_up()
1012 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); in sky2_up()
1014 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); in sky2_up()
1024 sky2->tx_le = pci_alloc_consistent(hw->pdev, in sky2_up()
1038 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, in sky2_up()
1050 sky2_mac_init(hw, port); in sky2_up()
1055 if (hw->chip_id == CHIP_ID_YUKON_FE) in sky2_up()
1058 ramsize = sky2_read8(hw, B2_E_0); in sky2_up()
1063 sky2_ramset(hw, rxqaddr[port], 0, rxspace); in sky2_up()
1064 sky2_ramset(hw, txqaddr[port], rxspace, ramsize); in sky2_up()
1067 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), in sky2_up()
1070 sky2_qset(hw, txqaddr[port]); in sky2_up()
1073 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) in sky2_up()
1074 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); in sky2_up()
1076 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, in sky2_up()
1084 imask = sky2_read32(hw, B0_IMSK); in sky2_up()
1086 sky2_write32(hw, B0_IMSK, imask); in sky2_up()
1092 pci_free_consistent(hw->pdev, RX_LE_BYTES, in sky2_up()
1097 pci_free_consistent(hw->pdev, in sky2_up()
1152 struct sky2_hw *hw = sky2->hw; in sky2_xmit_frame() local
1175 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); in sky2_xmit_frame()
1249 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, in sky2_xmit_frame()
1281 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); in sky2_xmit_frame()
1299 struct pci_dev *pdev = sky2->hw->pdev; in sky2_tx_complete()
1353 struct sky2_hw *hw = sky2->hw; in sky2_down() local
1368 sky2_phy_reset(hw, port); in sky2_down()
1371 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); in sky2_down()
1372 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); in sky2_down()
1374 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in sky2_down()
1377 ctrl = gma_read16(hw, port, GM_GP_CTRL); in sky2_down()
1379 gma_write16(hw, port, GM_GP_CTRL, ctrl); in sky2_down()
1381 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in sky2_down()
1384 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 in sky2_down()
1385 && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) in sky2_down()
1386 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in sky2_down()
1389 sky2_write8(hw, SK_REG(port, TXA_CTRL), in sky2_down()
1393 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); in sky2_down()
1394 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); in sky2_down()
1397 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), in sky2_down()
1401 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), in sky2_down()
1404 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in sky2_down()
1408 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in sky2_down()
1409 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); in sky2_down()
1412 imask = sky2_read32(hw, B0_IMSK); in sky2_down()
1414 sky2_write32(hw, B0_IMSK, imask); in sky2_down()
1417 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); in sky2_down()
1422 pci_free_consistent(hw->pdev, RX_LE_BYTES, in sky2_down()
1426 pci_free_consistent(hw->pdev, in sky2_down()
1440 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) in sky2_phy_speed() argument
1442 if (!hw->copper) in sky2_phy_speed()
1445 if (hw->chip_id == CHIP_ID_YUKON_FE) in sky2_phy_speed()
1460 struct sky2_hw *hw = sky2->hw; in sky2_link_up() local
1465 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); in sky2_link_up()
1467 reg = gma_read16(hw, port, GM_GP_CTRL); in sky2_link_up()
1472 gma_write16(hw, port, GM_GP_CTRL, reg); in sky2_link_up()
1473 gma_read16(hw, port, GM_GP_CTRL); in sky2_link_up()
1496 gma_write16(hw, port, GM_GP_CTRL, reg); in sky2_link_up()
1497 gma_read16(hw, port, GM_GP_CTRL); in sky2_link_up()
1499 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); in sky2_link_up()
1505 sky2_write8(hw, SK_REG(port, LNK_LED_REG), in sky2_link_up()
1508 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) { in sky2_link_up()
1509 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_link_up()
1526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); in sky2_link_up()
1527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led); in sky2_link_up()
1528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_link_up()
1542 struct sky2_hw *hw = sky2->hw; in sky2_link_down() local
1546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); in sky2_link_down()
1548 reg = gma_read16(hw, port, GM_GP_CTRL); in sky2_link_down()
1550 gma_write16(hw, port, GM_GP_CTRL, reg); in sky2_link_down()
1551 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ in sky2_link_down()
1555 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, in sky2_link_down()
1556 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) in sky2_link_down()
1564 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); in sky2_link_down()
1568 sky2_phy_init(hw, port); in sky2_link_down()
1573 struct sky2_hw *hw = sky2->hw; in sky2_autoneg_done() local
1577 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); in sky2_autoneg_done()
1584 if (hw->chip_id != CHIP_ID_YUKON_FE && in sky2_autoneg_done()
1585 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { in sky2_autoneg_done()
1599 sky2->speed = sky2_phy_speed(hw, aux); in sky2_autoneg_done()
1602 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) in sky2_autoneg_done()
1610 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in sky2_autoneg_done()
1612 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in sky2_autoneg_done()
1618 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) in sky2_phy_intr() argument
1620 struct net_device *dev = hw->dev[port]; in sky2_phy_intr()
1625 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); in sky2_phy_intr()
1626 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); in sky2_phy_intr()
1642 sky2->speed = sky2_phy_speed(hw, phystat); in sky2_phy_intr()
1665 struct sky2_hw *hw = sky2->hw; in sky2_tx_timeout() local
1672 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); in sky2_tx_timeout()
1673 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE)); in sky2_tx_timeout()
1682 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); in sky2_tx_timeout()
1683 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); in sky2_tx_timeout()
1693 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); in sky2_tx_timeout()
1694 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); in sky2_tx_timeout()
1698 sky2_qset(hw, txq); in sky2_tx_timeout()
1699 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); in sky2_tx_timeout()
1715 struct sky2_hw *hw = sky2->hw; in sky2_change_mtu() local
1723 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) in sky2_change_mtu()
1731 imask = sky2_read32(hw, B0_IMSK); in sky2_change_mtu()
1732 sky2_write32(hw, B0_IMSK, 0); in sky2_change_mtu()
1737 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); in sky2_change_mtu()
1738 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); in sky2_change_mtu()
1750 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); in sky2_change_mtu()
1752 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); in sky2_change_mtu()
1755 sky2_write32(hw, B0_IMSK, imask); in sky2_change_mtu()
1760 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); in sky2_change_mtu()
1801 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, in sky2_receive()
1806 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, in sky2_receive()
1817 pci_unmap_single(sky2->hw->pdev, re->mapaddr, in sky2_receive()
1821 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, in sky2_receive()
1868 static inline int sky2_more_work(const struct sky2_hw *hw) in sky2_more_work() argument
1870 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX)); in sky2_more_work()
1875 static void sky2_status_intr(struct sky2_hw *hw) in sky2_status_intr() argument
1879 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX); in sky2_status_intr()
1883 while (hw->st_idx != hwidx) { in sky2_status_intr()
1884 struct sky2_status_le *le = hw->st_le + hw->st_idx; in sky2_status_intr()
1890 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); in sky2_status_intr()
1893 dev = hw->dev[le->link]; in sky2_status_intr()
1913 sky2_put_idx(hw, rxqaddr[le->link], in sky2_status_intr()
1927 sky2_tx_done(hw->dev[0], status & 0xfff); in sky2_status_intr()
1928 if (hw->dev[1]) in sky2_status_intr()
1929 sky2_tx_done(hw->dev[1], in sky2_status_intr()
1942 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); in sky2_status_intr()
1946 sky2 = netdev_priv(hw->dev[0]); in sky2_status_intr()
1947 sky2_put_idx(hw, Q_R1, sky2->rx_put); in sky2_status_intr()
1951 sky2 = netdev_priv(hw->dev[1]); in sky2_status_intr()
1952 sky2_put_idx(hw, Q_R2, sky2->rx_put); in sky2_status_intr()
1957 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) in sky2_hw_error() argument
1959 struct net_device *dev = hw->dev[port]; in sky2_hw_error()
1970 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); in sky2_hw_error()
1978 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); in sky2_hw_error()
1984 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); in sky2_hw_error()
1990 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); in sky2_hw_error()
1997 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); in sky2_hw_error()
2001 static void sky2_hw_intr(struct sky2_hw *hw) in sky2_hw_intr() argument
2003 u32 status = sky2_read32(hw, B0_HWE_ISRC); in sky2_hw_intr()
2006 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in sky2_hw_intr()
2011 pci_err = sky2_pci_read16(hw, PCI_STATUS); in sky2_hw_intr()
2014 pci_name(hw->pdev), pci_err); in sky2_hw_intr()
2016 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_hw_intr()
2017 sky2_pci_write16(hw, PCI_STATUS, in sky2_hw_intr()
2019 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in sky2_hw_intr()
2026 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); in sky2_hw_intr()
2030 pci_name(hw->pdev), pex_err); in sky2_hw_intr()
2033 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_hw_intr()
2034 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, in sky2_hw_intr()
2036 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in sky2_hw_intr()
2039 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); in sky2_hw_intr()
2041 sky2_write32(hw, B0_HWE_IMSK, hwmsk); in sky2_hw_intr()
2046 sky2_hw_error(hw, 0, status); in sky2_hw_intr()
2049 sky2_hw_error(hw, 1, status); in sky2_hw_intr()
2052 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) in sky2_mac_intr() argument
2054 struct net_device *dev = hw->dev[port]; in sky2_mac_intr()
2056 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); in sky2_mac_intr()
2064 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in sky2_mac_intr()
2069 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in sky2_mac_intr()
2074 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port, in sky2_descriptor_error() argument
2077 struct net_device *dev = hw->dev[port]; in sky2_descriptor_error()
2084 imask = sky2_read32(hw, B0_IMSK); in sky2_descriptor_error()
2086 sky2_write32(hw, B0_IMSK, imask); in sky2_descriptor_error()
2097 struct sky2_hw *hw = dev_id; in sky2_intr() local
2100 status = sky2_read32(hw, B0_Y2_SP_ISRC2); in sky2_intr()
2107 sky2_hw_intr(hw); in sky2_intr()
2110 sky2_phy_intr(hw, 0); in sky2_intr()
2113 sky2_phy_intr(hw, 1); in sky2_intr()
2116 sky2_mac_intr(hw, 0); in sky2_intr()
2119 sky2_mac_intr(hw, 1); in sky2_intr()
2122 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); in sky2_intr()
2125 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); in sky2_intr()
2128 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); in sky2_intr()
2131 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); in sky2_intr()
2134 sky2_status_intr(hw); in sky2_intr()
2136 sky2_read32(hw, B0_Y2_SP_LISR); in sky2_intr()
2142 static inline u32 sky2_mhz(const struct sky2_hw *hw) in sky2_mhz() argument
2144 switch (hw->chip_id) { in sky2_mhz()
2155 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) in sky2_us2clk() argument
2157 return sky2_mhz(hw) * us; in sky2_us2clk()
2160 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) in sky2_clk2us() argument
2162 return clk / sky2_mhz(hw); in sky2_clk2us()
2166 static int sky2_reset(struct sky2_hw *hw) in sky2_reset() argument
2172 sky2_write8(hw, B0_CTST, CS_RST_CLR); in sky2_reset()
2174 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); in sky2_reset()
2175 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { in sky2_reset()
2177 pci_name(hw->pdev), hw->chip_id); in sky2_reset()
2181 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; in sky2_reset()
2184 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { in sky2_reset()
2186 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], in sky2_reset()
2187 hw->chip_id, hw->chip_rev); in sky2_reset()
2192 if (hw->chip_id <= CHIP_ID_YUKON_EC) { in sky2_reset()
2193 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); in sky2_reset()
2194 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); in sky2_reset()
2198 sky2_write8(hw, B0_CTST, CS_RST_SET); in sky2_reset()
2199 sky2_write8(hw, B0_CTST, CS_RST_CLR); in sky2_reset()
2202 status = sky2_pci_read16(hw, PCI_STATUS); in sky2_reset()
2204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in sky2_reset()
2205 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); in sky2_reset()
2208 sky2_write8(hw, B0_CTST, CS_MRST_CLR); in sky2_reset()
2211 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) in sky2_reset()
2212 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); in sky2_reset()
2215 pmd_type = sky2_read8(hw, B2_PMD_TYP); in sky2_reset()
2216 hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); in sky2_reset()
2218 hw->ports = 1; in sky2_reset()
2219 t8 = sky2_read8(hw, B2_Y2_HW_RES); in sky2_reset()
2221 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in sky2_reset()
2222 ++hw->ports; in sky2_reset()
2225 sky2_set_power_state(hw, PCI_D0); in sky2_reset()
2227 for (i = 0; i < hw->ports; i++) { in sky2_reset()
2228 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); in sky2_reset()
2229 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); in sky2_reset()
2232 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in sky2_reset()
2235 sky2_write32(hw, B2_I2C_IRQ, 1); in sky2_reset()
2238 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); in sky2_reset()
2239 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); in sky2_reset()
2241 sky2_write8(hw, B0_Y2LED, LED_STAT_ON); in sky2_reset()
2244 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); in sky2_reset()
2247 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); in sky2_reset()
2248 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in sky2_reset()
2251 for (i = 0; i < hw->ports; i++) in sky2_reset()
2252 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); in sky2_reset()
2255 for (i = 0; i < hw->ports; i++) { in sky2_reset()
2256 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); in sky2_reset()
2258 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); in sky2_reset()
2259 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); in sky2_reset()
2260 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); in sky2_reset()
2261 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); in sky2_reset()
2262 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); in sky2_reset()
2263 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); in sky2_reset()
2264 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); in sky2_reset()
2265 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); in sky2_reset()
2266 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); in sky2_reset()
2267 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); in sky2_reset()
2268 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); in sky2_reset()
2269 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); in sky2_reset()
2272 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); in sky2_reset()
2274 for (i = 0; i < hw->ports; i++) in sky2_reset()
2275 sky2_phy_reset(hw, i); in sky2_reset()
2277 memset(hw->st_le, 0, STATUS_LE_BYTES); in sky2_reset()
2278 hw->st_idx = 0; in sky2_reset()
2280 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); in sky2_reset()
2281 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); in sky2_reset()
2283 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); in sky2_reset()
2284 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); in sky2_reset()
2287 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); in sky2_reset()
2289 sky2_write16(hw, STAT_TX_IDX_TH, 10); in sky2_reset()
2290 sky2_write8(hw, STAT_FIFO_WM, 16); in sky2_reset()
2293 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) in sky2_reset()
2294 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); in sky2_reset()
2296 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); in sky2_reset()
2298 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); in sky2_reset()
2299 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); in sky2_reset()
2300 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); in sky2_reset()
2303 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); in sky2_reset()
2305 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); in sky2_reset()
2306 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); in sky2_reset()
2307 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); in sky2_reset()
2312 static u32 sky2_supported_modes(const struct sky2_hw *hw) in sky2_supported_modes() argument
2315 if (hw->copper) { in sky2_supported_modes()
2322 if (hw->chip_id != CHIP_ID_YUKON_FE) in sky2_supported_modes()
2334 struct sky2_hw *hw = sky2->hw; in sky2_get_settings() local
2337 ecmd->supported = sky2_supported_modes(hw); in sky2_get_settings()
2339 if (hw->copper) { in sky2_get_settings()
2361 const struct sky2_hw *hw = sky2->hw; in sky2_set_settings() local
2362 u32 supported = sky2_supported_modes(hw); in sky2_set_settings()
2425 strcpy(info->bus_info, pci_name(sky2->hw->pdev)); in sky2_get_drvinfo()
2485 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in sky2_set_rx_csum()
2511 struct sky2_hw *hw = sky2->hw; in sky2_phy_stats() local
2515 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 in sky2_phy_stats()
2516 | (u64) gma_read32(hw, port, GM_TXO_OK_LO); in sky2_phy_stats()
2517 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 in sky2_phy_stats()
2518 | (u64) gma_read32(hw, port, GM_RXO_OK_LO); in sky2_phy_stats()
2521 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); in sky2_phy_stats()
2581 struct sky2_hw *hw = sky2->hw; in sky2_set_mac_address() local
2589 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, in sky2_set_mac_address()
2591 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, in sky2_set_mac_address()
2595 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); in sky2_set_mac_address()
2598 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); in sky2_set_mac_address()
2606 struct sky2_hw *hw = sky2->hw; in sky2_set_multicast() local
2614 reg = gma_read16(hw, port, GM_RX_CTRL); in sky2_set_multicast()
2633 gma_write16(hw, port, GM_MC_ADDR_H1, in sky2_set_multicast()
2635 gma_write16(hw, port, GM_MC_ADDR_H2, in sky2_set_multicast()
2637 gma_write16(hw, port, GM_MC_ADDR_H3, in sky2_set_multicast()
2639 gma_write16(hw, port, GM_MC_ADDR_H4, in sky2_set_multicast()
2642 gma_write16(hw, port, GM_RX_CTRL, reg); in sky2_set_multicast()
2648 static void sky2_led(struct sky2_hw *hw, unsigned port, int on) in sky2_led() argument
2652 switch (hw->chip_id) { in sky2_led()
2654 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_led()
2655 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); in sky2_led()
2656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, in sky2_led()
2663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_led()
2667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in sky2_led()
2668 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in sky2_led()
2687 struct sky2_hw *hw = sky2->hw; in sky2_phys_id() local
2701 if (hw->chip_id == CHIP_ID_YUKON_XL) { in sky2_phys_id()
2702 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_phys_id()
2703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); in sky2_phys_id()
2704 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in sky2_phys_id()
2705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_phys_id()
2707 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); in sky2_phys_id()
2708 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); in sky2_phys_id()
2713 sky2_led(hw, port, onoff); in sky2_phys_id()
2724 if (hw->chip_id == CHIP_ID_YUKON_XL) { in sky2_phys_id()
2725 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); in sky2_phys_id()
2726 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); in sky2_phys_id()
2727 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); in sky2_phys_id()
2728 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); in sky2_phys_id()
2730 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); in sky2_phys_id()
2731 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); in sky2_phys_id()
2783 struct sky2_hw *hw = sky2->hw; in sky2_get_coalesce() local
2785 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) in sky2_get_coalesce()
2788 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); in sky2_get_coalesce()
2789 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); in sky2_get_coalesce()
2791 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); in sky2_get_coalesce()
2793 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) in sky2_get_coalesce()
2796 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); in sky2_get_coalesce()
2797 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); in sky2_get_coalesce()
2799 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); in sky2_get_coalesce()
2801 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) in sky2_get_coalesce()
2804 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); in sky2_get_coalesce()
2805 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); in sky2_get_coalesce()
2808 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); in sky2_get_coalesce()
2818 struct sky2_hw *hw = sky2->hw; in sky2_set_coalesce() local
2819 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); in sky2_set_coalesce()
2834 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); in sky2_set_coalesce()
2836 sky2_write32(hw, STAT_TX_TIMER_INI, in sky2_set_coalesce()
2837 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); in sky2_set_coalesce()
2838 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); in sky2_set_coalesce()
2840 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); in sky2_set_coalesce()
2843 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); in sky2_set_coalesce()
2845 sky2_write32(hw, STAT_LEV_TIMER_INI, in sky2_set_coalesce()
2846 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); in sky2_set_coalesce()
2847 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); in sky2_set_coalesce()
2849 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); in sky2_set_coalesce()
2852 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); in sky2_set_coalesce()
2854 sky2_write32(hw, STAT_ISR_TIMER_INI, in sky2_set_coalesce()
2855 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); in sky2_set_coalesce()
2856 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); in sky2_set_coalesce()
2858 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); in sky2_set_coalesce()
2920 const void __iomem *io = sky2->hw->regs; in sky2_get_regs()
2966 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, in sky2_init_netdev() argument
2978 SET_NETDEV_DEV(dev, &hw->pdev->dev); in sky2_init_netdev()
2979 dev->irq = hw->pdev->irq; in sky2_init_netdev()
2994 sky2->hw = hw; in sky2_init_netdev()
3004 sky2->advertising = sky2_supported_modes(hw); in sky2_init_netdev()
3012 hw->dev[port] = dev; in sky2_init_netdev()
3021 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); in sky2_init_netdev()
3045 struct sky2_hw *hw; in sky2_probe() local
3086 hw = kmalloc(sizeof(*hw), GFP_KERNEL); in sky2_probe()
3087 if (!hw) { in sky2_probe()
3092 memset(hw, 0, sizeof(*hw)); in sky2_probe()
3094 hw->pdev = pdev; in sky2_probe()
3096 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); in sky2_probe()
3097 if (!hw->regs) { in sky2_probe()
3102 hw->pm_cap = pm_cap; in sky2_probe()
3109 reg = sky2_pci_read32(hw, PCI_DEV_REG2); in sky2_probe()
3111 sky2_pci_write32(hw, PCI_DEV_REG2, reg); in sky2_probe()
3116 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, in sky2_probe()
3117 &hw->st_dma); in sky2_probe()
3118 if (!hw->st_le) in sky2_probe()
3121 err = sky2_reset(hw); in sky2_probe()
3127 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], in sky2_probe()
3128 hw->chip_id, hw->chip_rev); in sky2_probe()
3130 dev = sky2_init_netdev(hw, 0, using_dac); in sky2_probe()
3143 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { in sky2_probe()
3150 hw->dev[1] = NULL; in sky2_probe()
3156 DRV_NAME, hw); in sky2_probe()
3163 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); in sky2_probe()
3165 pci_set_drvdata(pdev, hw); in sky2_probe()
3178 sky2_write8(hw, B0_CTST, CS_RST_SET); in sky2_probe()
3179 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); in sky2_probe()
3181 iounmap(hw->regs); in sky2_probe()
3183 kfree(hw); in sky2_probe()
3193 struct sky2_hw *hw = pci_get_drvdata(pdev); in sky2_remove() local
3196 if (!hw) in sky2_remove()
3199 sky2_write32(hw, B0_IMSK, 0); in sky2_remove()
3201 dev0 = hw->dev[0]; in sky2_remove()
3202 dev1 = hw->dev[1]; in sky2_remove()
3207 sky2_set_power_state(hw, PCI_D3hot); in sky2_remove()
3208 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); in sky2_remove()
3209 sky2_write8(hw, B0_CTST, CS_RST_SET); in sky2_remove()
3210 sky2_read8(hw, B0_CTST); in sky2_remove()
3212 free_irq(pdev->irq, hw); in sky2_remove()
3213 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); in sky2_remove()
3220 iounmap(hw->regs); in sky2_remove()
3221 kfree(hw); in sky2_remove()