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Searched refs:bridgereg_t (Results 1 – 14 of 14) sorted by relevance

/linux-2.4.37.9/include/asm-mips64/pci/ !
Dbridge.h50 typedef u32 bridgereg_t; typedef
87 bridgereg_t _pad_000058;
88 bridgereg_t b_wid_aux_err; /* 0x00005C */
89 bridgereg_t _pad_000060;
90 bridgereg_t b_wid_resp_upper; /* 0x000064 */
91 bridgereg_t _pad_000068;
92 bridgereg_t b_wid_resp_lower; /* 0x00006C */
93 bridgereg_t _pad_000070;
94 bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
95 bridgereg_t _pad_000078[2];
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/linux-2.4.37.9/include/asm-ia64/sn/pci/ !
Dbridge.h95 typedef uint32_t bridgereg_t; typedef
121 bridgereg_t _b_wid_id; /* 0x000004 */
122 bridgereg_t _pad_000000;
127 bridgereg_t _b_wid_stat; /* 0x00000C */
128 bridgereg_t _b_pad_000008;
134 bridgereg_t _b_wid_err_upper; /* 0x000014 */
135 bridgereg_t _pad_000010;
140 bridgereg_t _b_wid_err_lower; /* 0x00001C */
141 bridgereg_t _b_pad_000018;
150 bridgereg_t _b_wid_control; /* 0x000024 */
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Dpcibr.h420 bridgereg_t resp_bss_device;
436 bridgereg_t resp_b_resp;
437 bridgereg_t resp_b_int_device;
438 bridgereg_t resp_b_int_enable;
439 bridgereg_t resp_b_int_host;
Dpcibr_private.h40 typedef volatile bridgereg_t *reg_p;
250 volatile bridgereg_t *il_wrbf; /* ptr to b_wr_req_buf[] */
258 volatile bridgereg_t *iw_stat; /* ptr to b_int_status */
259 bridgereg_t iw_ibit; /* bit in b_int_status */
449 bridgereg_t bss_device;
/linux-2.4.37.9/arch/ia64/sn/io/sn2/pcibr/ !
Dpcibr_rrb.c91 bridgereg_t tmp; in do_pcibr_rrb_count_valid()
124 bridgereg_t tmp; in do_pcibr_rrb_count_avail()
160 bridgereg_t reg, tmp = (bridgereg_t)0; in do_pcibr_rrb_alloc()
205 bridgereg_t reg, tmp = (bridgereg_t)0, clr = 0; in do_pcibr_rrb_free()
277 bridgereg_t status; in do_pcibr_rrb_clear()
309 bridgereg_t rrbv; in do_pcibr_rrb_flush()
369 bridgereg_t tmp; in pcibr_rrb_flush()
403 volatile bridgereg_t *wrb_flush; in pcibr_wrb_flush()
Dpcibr_error.c241 bridgereg_t int_status_32; in pcibr_error_dump()
244 bridgereg_t mult_int_32; in pcibr_error_dump()
561 bridgereg_t int_status_32; in pcibr_pioerr_check()
563 bridgereg_t pci_err_lower; in pcibr_pioerr_check()
564 bridgereg_t pci_err_upper; in pcibr_pioerr_check()
649 bridgereg_t int_status_32; in pcibr_error_intr_handler()
891 bridge->b_int_enable &= (bridgereg_t)(~disable_errintr_mask); in pcibr_error_intr_handler()
961 bridge->b_int_rst_stat = (bridgereg_t)pcibr_errintr_group(int_status); in pcibr_error_intr_handler()
1430 if (bridge->b_int_status & (bridgereg_t)BRIDGE_ISR_PCIBUS_PIOERR) in pcibr_pioerror()
1441 bridgereg_t device = bridge->b_device[slot].reg; in pcibr_pioerror()
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Dpcibr_intr.c221 *(bridgereg_t *)(p->force_int_addr) = 1; in sn_dma_flush()
318 bridgereg_t int_dev; in pcibr_intr_alloc()
570 bridgereg_t int_dev; in pcibr_intr_free()
684 bridgereg_t int_enable; in pcibr_intr_connect()
740 bridge->b_int_enable = (bridgereg_t)int_enable; in pcibr_intr_disconnect()
1056 bridgereg_t int_enable; in pcibr_intr_func()
1057 bridgereg_t mask = 1 << wrap->iw_ibit; in pcibr_intr_func()
1072 bridge->b_int_enable = (bridgereg_t)int_enable; in pcibr_intr_func()
Dpcibr_dvr.c132 static int pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
133 void pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
277 bridgereg_t mask) in pcibr_try_set_device()
281 bridgereg_t old; in pcibr_try_set_device()
282 bridgereg_t new; in pcibr_try_set_device()
283 bridgereg_t chg; in pcibr_try_set_device()
284 bridgereg_t bad; in pcibr_try_set_device()
285 bridgereg_t badpmu; in pcibr_try_set_device()
286 bridgereg_t badd32; in pcibr_try_set_device()
287 bridgereg_t badd64; in pcibr_try_set_device()
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Dpcibr_ate.c88 bridgereg_t old_enable, new_enable; in pcibr_init_ext_ate_ram()
Dpcibr_slot.c1343 bridgereg_t devreg; in pcibr_slot_device_init()
/linux-2.4.37.9/include/asm-mips64/sn/sn0/ !
Daddrs.h153 #define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
/linux-2.4.37.9/arch/mips/sgi-ip27/ !
Dip27-irq.c188 bridgereg_t device; in startup_bridge_irq()
Dip27-pci.c304 bridgereg_t devreg; in pci_fixup_isp2x00()
/linux-2.4.37.9/arch/ia64/sn/io/machvec/ !
Dpci_bus_cvlink.c187 bridgereg_t dev_sel; in sn_dma_flush_init()