1 /*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 2001-2003 Silicon Graphics, Inc. All rights reserved.
8 */
9
10 #include <linux/types.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <asm/sn/sgi.h>
14 #include <asm/sn/sn_cpuid.h>
15 #include <asm/sn/addrs.h>
16 #include <asm/sn/arch.h>
17 #include <asm/sn/iograph.h>
18 #include <asm/sn/invent.h>
19 #include <asm/sn/hcl.h>
20 #include <asm/sn/labelcl.h>
21 #include <asm/sn/xtalk/xwidget.h>
22 #include <asm/sn/pci/bridge.h>
23 #include <asm/sn/pci/pciio.h>
24 #include <asm/sn/pci/pcibr.h>
25 #include <asm/sn/pci/pcibr_private.h>
26 #include <asm/sn/pci/pci_defs.h>
27 #include <asm/sn/prio.h>
28 #include <asm/sn/xtalk/xbow.h>
29 #include <asm/sn/ioc3.h>
30 #include <asm/sn/io.h>
31 #include <asm/sn/sn_private.h>
32
33 extern int hubii_check_widget_disabled(nasid_t, int);
34
35
36 /* =====================================================================
37 * ERROR HANDLING
38 */
39
40 #ifdef DEBUG
41 #ifdef ERROR_DEBUG
42 #define BRIDGE_PIOERR_TIMEOUT 100 /* Timeout with ERROR_DEBUG defined */
43 #else
44 #define BRIDGE_PIOERR_TIMEOUT 40 /* Timeout in debug mode */
45 #endif
46 #else
47 #define BRIDGE_PIOERR_TIMEOUT 1 /* Timeout in non-debug mode */
48 #endif
49
50 /* PIC has 64bit interrupt error registers, but BRIDGE has 32bit registers.
51 * Thus 'bridge_errors_to_dump needs' to default to the larger of the two.
52 */
53 #ifdef DEBUG
54 #ifdef ERROR_DEBUG
55 uint64_t bridge_errors_to_dump = ~BRIDGE_ISR_INT_MSK;
56 #else
57 uint64_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_DUMP;
58 #endif
59 #else
60 uint64_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_FATAL |
61 BRIDGE_ISR_PCIBUS_PIOERR;
62 #endif
63
64 int pcibr_llp_control_war_cnt; /* PCIBR_LLP_CONTROL_WAR */
65
66 static struct reg_values xio_cmd_pactyp[] =
67 {
68 {0x0, "RdReq"},
69 {0x1, "RdResp"},
70 {0x2, "WrReqWithResp"},
71 {0x3, "WrResp"},
72 {0x4, "WrReqNoResp"},
73 {0x5, "Reserved(5)"},
74 {0x6, "FetchAndOp"},
75 {0x7, "Reserved(7)"},
76 {0x8, "StoreAndOp"},
77 {0x9, "Reserved(9)"},
78 {0xa, "Reserved(a)"},
79 {0xb, "Reserved(b)"},
80 {0xc, "Reserved(c)"},
81 {0xd, "Reserved(d)"},
82 {0xe, "SpecialReq"},
83 {0xf, "SpecialResp"},
84 {0}
85 };
86
87 static struct reg_desc xio_cmd_bits[] =
88 {
89 {WIDGET_DIDN, -28, "DIDN", "%x"},
90 {WIDGET_SIDN, -24, "SIDN", "%x"},
91 {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
92 {WIDGET_TNUM, -15, "TNUM", "%x"},
93 {WIDGET_COHERENT, 0, "COHERENT"},
94 {WIDGET_DS, 0, "DS"},
95 {WIDGET_GBR, 0, "GBR"},
96 {WIDGET_VBPM, 0, "VBPM"},
97 {WIDGET_ERROR, 0, "ERROR"},
98 {WIDGET_BARRIER, 0, "BARRIER"},
99 {0}
100 };
101
102 #define F(s,n) { 1l<<(s),-(s), n }
103
104 #if defined(FORCE_ERRORS)
105 static struct reg_values space_v[] =
106 {
107 {PCIIO_SPACE_NONE, "none"},
108 {PCIIO_SPACE_ROM, "ROM"},
109 {PCIIO_SPACE_IO, "I/O"},
110 {PCIIO_SPACE_MEM, "MEM"},
111 {PCIIO_SPACE_MEM32, "MEM(32)"},
112 {PCIIO_SPACE_MEM64, "MEM(64)"},
113 {PCIIO_SPACE_CFG, "CFG"},
114 {PCIIO_SPACE_WIN(0), "WIN(0)"},
115 {PCIIO_SPACE_WIN(1), "WIN(1)"},
116 {PCIIO_SPACE_WIN(2), "WIN(2)"},
117 {PCIIO_SPACE_WIN(3), "WIN(3)"},
118 {PCIIO_SPACE_WIN(4), "WIN(4)"},
119 {PCIIO_SPACE_WIN(5), "WIN(5)"},
120 {PCIIO_SPACE_BAD, "BAD"},
121 {0}
122 };
123 static struct reg_desc space_desc[] =
124 {
125 {0xFF, 0, "space", 0, space_v},
126 {0}
127 };
128 #define device_desc device_bits
129 static struct reg_desc device_bits[] =
130 {
131 {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
132 {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
133 {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
134 {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
135 {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
136 {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
137 {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
138 {BRIDGE_DEV_RT, 0, "RT"},
139 {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
140 {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
141 {BRIDGE_DEV_PREF, 0, "PREF"},
142 {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
143 {BRIDGE_DEV_COH, 0, "COH"},
144 {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
145 {BRIDGE_DEV_GBR, 0, "GBR"},
146 {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
147 {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
148 {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
149 {0}
150 };
151 #endif /* FORCE_ERRORS */
152
153 static void
print_bridge_errcmd(uint32_t cmdword,char * errtype)154 print_bridge_errcmd(uint32_t cmdword, char *errtype)
155 {
156 printk("\t Bridge %s Error Command Word Register ", errtype);
157 print_register(cmdword, xio_cmd_bits);
158 }
159
160 static char *pcibr_isr_errs[] =
161 {
162 "", "", "", "", "", "", "", "",
163 "08: GIO non-contiguous byte enable in crosstalk packet", /* BRIDGE ONLY */
164 "09: PCI to Crosstalk read request timeout",
165 "10: PCI retry operation count exhausted.",
166 "11: PCI bus device select timeout",
167 "12: PCI device reported parity error",
168 "13: PCI Address/Cmd parity error ",
169 "14: PCI Bridge detected parity error",
170 "15: PCI abort condition",
171 "16: SSRAM parity error", /* BRIDGE ONLY */
172 "17: LLP Transmitter Retry count wrapped",
173 "18: LLP Transmitter side required Retry",
174 "19: LLP Receiver retry count wrapped",
175 "20: LLP Receiver check bit error",
176 "21: LLP Receiver sequence number error",
177 "22: Request packet overflow",
178 "23: Request operation not supported by bridge",
179 "24: Request packet has invalid address for bridge widget",
180 "25: Incoming request xtalk command word error bit set or invalid sideband",
181 "26: Incoming response xtalk command word error bit set or invalid sideband",
182 "27: Framing error, request cmd data size does not match actual",
183 "28: Framing error, response cmd data size does not match actual",
184 "29: Unexpected response arrived",
185 "30: PMU Access Fault",
186 "31: Multiple errors occurred", /* BRIDGE ONLY */
187
188 /* bits 32-45 are PIC ONLY */
189 "32: PCI-X address or attribute cycle parity error",
190 "33: PCI-X data cycle parity error",
191 "34: PCI-X master timeout (ie. master abort)",
192 "35: PCI-X pio retry counter exhausted",
193 "36: PCI-X SERR",
194 "37: PCI-X PERR",
195 "38: PCI-X target abort",
196 "39: PCI-X read request timeout",
197 "40: PCI / PCI-X device requestin arbitration error",
198 "41: internal RAM parity error",
199 "42: PCI-X unexpected completion cycle to master",
200 "43: PCI-X split completion timeout",
201 "44: PCI-X split completion error message",
202 "45: PCI-X split completion message parity error",
203 };
204
205 #define BEM_ADD_STR(s) printk("%s", (s))
206 #define BEM_ADD_VAR(v) printk("\t%20s: 0x%llx\n", #v, ((unsigned long long)v))
207 #define BEM_ADD_REG(r) printk("\t%20s: ", #r); print_register((r), r ## _desc)
208 #define BEM_ADD_NSPC(n,s) printk("\t%20s: ", n); print_register(s, space_desc)
209 #define BEM_ADD_SPC(s) BEM_ADD_NSPC(#s, s)
210
211 /*
212 * display memory directory state
213 */
214 static void
pcibr_show_dir_state(paddr_t paddr,char * prefix)215 pcibr_show_dir_state(paddr_t paddr, char *prefix)
216 {
217 #ifdef LATER
218 int state;
219 uint64_t vec_ptr;
220 hubreg_t elo;
221 extern char *dir_state_str[];
222 extern void get_dir_ent(paddr_t, int *, uint64_t *, hubreg_t *);
223
224 get_dir_ent(paddr, &state, &vec_ptr, &elo);
225
226 printk("%saddr 0x%lx: state 0x%x owner 0x%lx (%s)\n",
227 prefix, paddr, state, vec_ptr, dir_state_str[state]);
228 #endif
229 }
230
231
232 /*
233 * Dump relevant error information for Bridge error interrupts.
234 */
235 /*ARGSUSED */
236 void
pcibr_error_dump(pcibr_soft_t pcibr_soft)237 pcibr_error_dump(pcibr_soft_t pcibr_soft)
238 {
239 bridge_t *bridge = pcibr_soft->bs_base;
240 uint64_t int_status;
241 bridgereg_t int_status_32;
242 picreg_t int_status_64;
243 uint64_t mult_int;
244 bridgereg_t mult_int_32;
245 picreg_t mult_int_64;
246 uint64_t bit;
247 int number_bits;
248 int i;
249 char *reg_desc;
250 paddr_t addr = (paddr_t)0;
251
252 /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a
253 * 32bit bridgereg_t for BRIDGE, but always process the result as a
254 * 64bit value so the code can be "common" for both PIC and BRIDGE...
255 */
256 if (IS_PIC_SOFT(pcibr_soft)) {
257 int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
258 int_status = (uint64_t)int_status_64;
259 number_bits = PCIBR_ISR_MAX_ERRS_PIC;
260 } else {
261 int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
262 int_status = ((uint64_t)int_status_32) & 0xffffffff;
263 number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE;
264 }
265
266 if (!int_status) {
267 /* No error bits set */
268 return;
269 }
270
271 /* Check if dumping the same error information multiple times */
272 if ( pcibr_soft->bs_errinfo.bserr_intstat == int_status )
273 return;
274 pcibr_soft->bs_errinfo.bserr_intstat = int_status;
275
276 printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%lx for %s\n"
277 " Dumping relevant %s registers for each bit set...\n",
278 int_status, pcibr_soft->bs_name,
279 (IS_PIC_SOFT(pcibr_soft) ? "PIC" :
280 (IS_BRIDGE_SOFT(pcibr_soft) ? "BRIDGE" : "XBRIDGE")));
281
282 for (i = PCIBR_ISR_ERR_START; i < number_bits; i++) {
283 bit = 1ull << i;
284
285 /*
286 * A number of int_status bits are only defined for Bridge.
287 * Ignore them in the case of an XBridge or PIC.
288 */
289 if ((IS_XBRIDGE_SOFT(pcibr_soft) || IS_PIC_SOFT(pcibr_soft)) &&
290 ((bit == BRIDGE_ISR_MULTI_ERR) ||
291 (bit == BRIDGE_ISR_SSRAM_PERR) ||
292 (bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) {
293 continue;
294 }
295
296 /* A number of int_status bits are only valid for PIC's bus0 */
297 if ((IS_PIC_SOFT(pcibr_soft) && (pcibr_soft->bs_busnum != 0)) &&
298 ((bit == BRIDGE_ISR_UNSUPPORTED_XOP) ||
299 (bit == BRIDGE_ISR_LLP_REC_SNERR) ||
300 (bit == BRIDGE_ISR_LLP_REC_CBERR) ||
301 (bit == BRIDGE_ISR_LLP_RCTY) ||
302 (bit == BRIDGE_ISR_LLP_TX_RETRY) ||
303 (bit == BRIDGE_ISR_LLP_TCTY))) {
304 continue;
305 }
306
307 if (int_status & bit) {
308 printk("\t%s\n", pcibr_isr_errs[i]);
309
310 switch (bit) {
311
312 case PIC_ISR_INT_RAM_PERR: /* bit41 INT_RAM_PERR */
313 /* XXX: should breakdown meaning of bits in reg */
314 printk( "\t Internal RAM Parity Error: 0x%lx\n",
315 bridge->p_ate_parity_err_64);
316 break;
317
318 case PIC_ISR_PCIX_ARB_ERR: /* bit40 PCI_X_ARB_ERR */
319 /* XXX: should breakdown meaning of bits in reg */
320 printk( "\t Arbitration Reg: 0x%x\n",
321 bridge->b_arb);
322 break;
323
324 case PIC_ISR_PCIX_REQ_TOUT: /* bit39 PCI_X_REQ_TOUT */
325 /* XXX: should breakdown meaning of attribute bit */
326 printk(
327 "\t PCI-X DMA Request Error Address Reg: 0x%lx\n"
328 "\t PCI-X DMA Request Error Attribute Reg: 0x%lx\n",
329 bridge->p_pcix_dma_req_err_addr_64,
330 bridge->p_pcix_dma_req_err_attr_64);
331 break;
332
333 case PIC_ISR_PCIX_SPLIT_MSG_PE: /* bit45 PCI_X_SPLIT_MES_PE */
334 case PIC_ISR_PCIX_SPLIT_EMSG: /* bit44 PCI_X_SPLIT_EMESS */
335 case PIC_ISR_PCIX_SPLIT_TO: /* bit43 PCI_X_SPLIT_TO */
336 /* XXX: should breakdown meaning of attribute bit */
337 printk(
338 "\t PCI-X Split Request Address Reg: 0x%lx\n"
339 "\t PCI-X Split Request Attribute Reg: 0x%lx\n",
340 bridge->p_pcix_pio_split_addr_64,
341 bridge->p_pcix_pio_split_attr_64);
342 /* FALL THRU */
343
344 case PIC_ISR_PCIX_UNEX_COMP: /* bit42 PCI_X_UNEX_COMP */
345 case PIC_ISR_PCIX_TABORT: /* bit38 PCI_X_TABORT */
346 case PIC_ISR_PCIX_PERR: /* bit37 PCI_X_PERR */
347 case PIC_ISR_PCIX_SERR: /* bit36 PCI_X_SERR */
348 case PIC_ISR_PCIX_MRETRY: /* bit35 PCI_X_MRETRY */
349 case PIC_ISR_PCIX_MTOUT: /* bit34 PCI_X_MTOUT */
350 case PIC_ISR_PCIX_DA_PARITY: /* bit33 PCI_X_DA_PARITY */
351 case PIC_ISR_PCIX_AD_PARITY: /* bit32 PCI_X_AD_PARITY */
352 /* XXX: should breakdown meaning of attribute bit */
353 printk(
354 "\t PCI-X Bus Error Address Reg: 0x%lx\n"
355 "\t PCI-X Bus Error Attribute Reg: 0x%lx\n"
356 "\t PCI-X Bus Error Data Reg: 0x%lx\n",
357 bridge->p_pcix_bus_err_addr_64,
358 bridge->p_pcix_bus_err_attr_64,
359 bridge->p_pcix_bus_err_data_64);
360 break;
361
362 case BRIDGE_ISR_PAGE_FAULT: /* bit30 PMU_PAGE_FAULT */
363 if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft))
364 reg_desc = "Map Fault Address";
365 else
366 reg_desc = "SSRAM Parity Error";
367
368 printk( "\t %s Register: 0x%x\n", reg_desc,
369 bridge->b_ram_perr_or_map_fault);
370 break;
371
372 case BRIDGE_ISR_UNEXP_RESP: /* bit29 UNEXPECTED_RESP */
373 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
374
375 /* PIC in PCI-X mode, dump the PCIX DMA Request registers */
376 if (IS_PIC_SOFT(pcibr_soft) && IS_PCIX(pcibr_soft)) {
377 /* XXX: should breakdown meaning of attr bit */
378 printk(
379 "\t PCI-X DMA Request Error Addr Reg: 0x%lx\n"
380 "\t PCI-X DMA Request Error Attr Reg: 0x%lx\n",
381 bridge->p_pcix_dma_req_err_addr_64,
382 bridge->p_pcix_dma_req_err_attr_64);
383 }
384 break;
385
386 case BRIDGE_ISR_BAD_XRESP_PKT: /* bit28 BAD_RESP_PACKET */
387 case BRIDGE_ISR_RESP_XTLK_ERR: /* bit26 RESP_XTALK_ERROR */
388 if (IS_PIC_SOFT(pcibr_soft)) {
389 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
390 }
391
392 /* If PIC in PCI-X mode, DMA Request Error registers are
393 * valid. But PIC in PCI mode, Response Buffer Address
394 * register are valid.
395 */
396 if (IS_PCIX(pcibr_soft)) {
397 /* XXX: should breakdown meaning of attribute bit */
398 printk(
399 "\t PCI-X DMA Request Error Addr Reg: 0x%lx\n"
400 "\t PCI-X DMA Request Error Attribute Reg: 0x%lx\n",
401 bridge->p_pcix_dma_req_err_addr_64,
402 bridge->p_pcix_dma_req_err_attr_64);
403 } else {
404 addr= (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF)<<32)
405 | bridge->b_wid_resp_lower);
406 printk("\t Bridge Response Buf Error Upper Addr Reg: 0x%x\n"
407 "\t Bridge Response Buf Error Lower Addr Reg: 0x%x\n"
408 "\t dev-num %d buff-num %d addr 0x%lx\n",
409 bridge->b_wid_resp_upper, bridge->b_wid_resp_lower,
410 ((bridge->b_wid_resp_upper >> 20) & 0x3),
411 ((bridge->b_wid_resp_upper >> 16) & 0xF),
412 addr);
413 }
414 if (bit == BRIDGE_ISR_RESP_XTLK_ERR) {
415 /* display memory directory associated with cacheline */
416 pcibr_show_dir_state(addr, "\t ");
417 }
418 break;
419
420 case BRIDGE_ISR_BAD_XREQ_PKT: /* bit27 BAD_XREQ_PACKET */
421 case BRIDGE_ISR_REQ_XTLK_ERR: /* bit25 REQ_XTALK_ERROR */
422 case BRIDGE_ISR_INVLD_ADDR: /* bit24 INVALID_ADDRESS */
423 print_bridge_errcmd(bridge->b_wid_err_cmdword, "");
424 printk(
425 "\t Bridge Error Upper Address Register: 0x%lx\n"
426 "\t Bridge Error Lower Address Register: 0x%lx\n"
427 "\t Bridge Error Address: 0x%lx\n",
428 (uint64_t) bridge->b_wid_err_upper,
429 (uint64_t) bridge->b_wid_err_lower,
430 (((uint64_t) bridge->b_wid_err_upper << 32) |
431 bridge->b_wid_err_lower));
432 break;
433
434 case BRIDGE_ISR_UNSUPPORTED_XOP:/* bit23 UNSUPPORTED_XOP */
435 if (IS_PIC_SOFT(pcibr_soft)) {
436 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
437 printk(
438 "\t Address Holding Link Side Error Reg: 0x%lx\n",
439 bridge->p_addr_lkerr_64);
440 } else {
441 print_bridge_errcmd(bridge->b_wid_err_cmdword, "");
442 printk(
443 "\t Bridge Error Upper Address Register: 0x%lx\n"
444 "\t Bridge Error Lower Address Register: 0x%lx\n"
445 "\t Bridge Error Address: 0x%lx\n",
446 (uint64_t) bridge->b_wid_err_upper,
447 (uint64_t) bridge->b_wid_err_lower,
448 (((uint64_t) bridge->b_wid_err_upper << 32) |
449 bridge->b_wid_err_lower));
450 }
451 break;
452
453 case BRIDGE_ISR_XREQ_FIFO_OFLOW:/* bit22 XREQ_FIFO_OFLOW */
454 /* Link side error registers are only valid for PIC */
455 if (IS_PIC_SOFT(pcibr_soft)) {
456 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux ");
457 printk(
458 "\t Address Holding Link Side Error Reg: 0x%lx\n",
459 bridge->p_addr_lkerr_64);
460 }
461 break;
462
463 case BRIDGE_ISR_SSRAM_PERR: /* bit16 SSRAM_PERR */
464 if (IS_BRIDGE_SOFT(pcibr_soft)) {
465 printk(
466 "\t Bridge SSRAM Parity Error Register: 0x%x\n",
467 bridge->b_ram_perr);
468 }
469 break;
470
471 case BRIDGE_ISR_PCI_ABORT: /* bit15 PCI_ABORT */
472 case BRIDGE_ISR_PCI_PARITY: /* bit14 PCI_PARITY */
473 case BRIDGE_ISR_PCI_SERR: /* bit13 PCI_SERR */
474 case BRIDGE_ISR_PCI_PERR: /* bit12 PCI_PERR */
475 case BRIDGE_ISR_PCI_MST_TIMEOUT:/* bit11 PCI_MASTER_TOUT */
476 case BRIDGE_ISR_PCI_RETRY_CNT: /* bit10 PCI_RETRY_CNT */
477 case BRIDGE_ISR_GIO_B_ENBL_ERR: /* bit08 GIO BENABLE_ERR */
478 printk(
479 "\t PCI Error Upper Address Register: 0x%lx\n"
480 "\t PCI Error Lower Address Register: 0x%lx\n"
481 "\t PCI Error Address: 0x%lx\n",
482 (uint64_t) bridge->b_pci_err_upper,
483 (uint64_t) bridge->b_pci_err_lower,
484 (((uint64_t) bridge->b_pci_err_upper << 32) |
485 bridge->b_pci_err_lower));
486 break;
487
488 case BRIDGE_ISR_XREAD_REQ_TIMEOUT: /* bit09 XREAD_REQ_TOUT */
489 addr = (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF) << 32)
490 | bridge->b_wid_resp_lower);
491 printk(
492 "\t Bridge Response Buf Error Upper Addr Reg: 0x%x\n"
493 "\t Bridge Response Buf Error Lower Addr Reg: 0x%x\n"
494 "\t dev-num %d buff-num %d addr 0x%lx\n",
495 bridge->b_wid_resp_upper, bridge->b_wid_resp_lower,
496 ((bridge->b_wid_resp_upper >> 20) & 0x3),
497 ((bridge->b_wid_resp_upper >> 16) & 0xF),
498 addr);
499 break;
500 }
501 }
502 }
503
504 /* We read the INT_MULT register as a 64bit picreg_t for PIC and a
505 * 32bit bridgereg_t for BRIDGE, but always process the result as a
506 * 64bit value so the code can be "common" for both PIC and BRIDGE...
507 */
508 if (IS_PIC_SOFT(pcibr_soft)) {
509 mult_int_64 = (bridge->p_mult_int_64 & ~BRIDGE_ISR_INT_MSK);
510 mult_int = (uint64_t)mult_int_64;
511 number_bits = PCIBR_ISR_MAX_ERRS_PIC;
512 } else {
513 mult_int_32 = (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK);
514 mult_int = ((uint64_t)mult_int_32) & 0xffffffff;
515 number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE;
516 }
517
518 if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)&&(mult_int & ~BRIDGE_ISR_INT_MSK)) {
519 printk( " %s Multiple Interrupt Register is 0x%lx\n",
520 IS_PIC_SOFT(pcibr_soft) ? "PIC" : "XBridge", mult_int);
521 for (i = PCIBR_ISR_ERR_START; i < number_bits; i++) {
522 if (mult_int & (1ull << i))
523 printk( "\t%s\n", pcibr_isr_errs[i]);
524 }
525 }
526 }
527
528 static uint32_t
pcibr_errintr_group(uint32_t error)529 pcibr_errintr_group(uint32_t error)
530 {
531 uint32_t group = BRIDGE_IRR_MULTI_CLR;
532
533 if (error & BRIDGE_IRR_PCI_GRP)
534 group |= BRIDGE_IRR_PCI_GRP_CLR;
535 if (error & BRIDGE_IRR_SSRAM_GRP)
536 group |= BRIDGE_IRR_SSRAM_GRP_CLR;
537 if (error & BRIDGE_IRR_LLP_GRP)
538 group |= BRIDGE_IRR_LLP_GRP_CLR;
539 if (error & BRIDGE_IRR_REQ_DSP_GRP)
540 group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
541 if (error & BRIDGE_IRR_RESP_BUF_GRP)
542 group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
543 if (error & BRIDGE_IRR_CRP_GRP)
544 group |= BRIDGE_IRR_CRP_GRP_CLR;
545
546 return group;
547
548 }
549
550
551 /* pcibr_pioerr_check():
552 * Check to see if this pcibr has a PCI PIO
553 * TIMEOUT error; if so, bump the timeout-count
554 * on any piomaps that could cover the address.
555 */
556 static void
pcibr_pioerr_check(pcibr_soft_t soft)557 pcibr_pioerr_check(pcibr_soft_t soft)
558 {
559 bridge_t *bridge;
560 uint64_t int_status;
561 bridgereg_t int_status_32;
562 picreg_t int_status_64;
563 bridgereg_t pci_err_lower;
564 bridgereg_t pci_err_upper;
565 iopaddr_t pci_addr;
566 pciio_slot_t slot;
567 pcibr_piomap_t map;
568 iopaddr_t base;
569 size_t size;
570 unsigned win;
571 int func;
572
573 bridge = soft->bs_base;
574
575 /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a
576 * 32bit bridgereg_t for BRIDGE, but always process the result as a
577 * 64bit value so the code can be "common" for both PIC and BRIDGE...
578 */
579 if (IS_PIC_SOFT(soft)) {
580 int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
581 int_status = (uint64_t)int_status_64;
582 } else {
583 int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
584 int_status = ((uint64_t)int_status_32) & 0xffffffff;
585 }
586
587 if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
588 pci_err_lower = bridge->b_pci_err_lower;
589 pci_err_upper = bridge->b_pci_err_upper;
590
591 pci_addr = pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
592 pci_addr = (pci_addr << 32) | pci_err_lower;
593
594 slot = PCIBR_NUM_SLOTS(soft);
595 while (slot-- > 0) {
596 int nfunc = soft->bs_slot[slot].bss_ninfo;
597 pcibr_info_h pcibr_infoh = soft->bs_slot[slot].bss_infos;
598
599 for (func = 0; func < nfunc; func++) {
600 pcibr_info_t pcibr_info = pcibr_infoh[func];
601
602 if (!pcibr_info)
603 continue;
604
605 for (map = pcibr_info->f_piomap;
606 map != NULL; map = map->bp_next) {
607 base = map->bp_pciaddr;
608 size = map->bp_mapsz;
609 win = map->bp_space - PCIIO_SPACE_WIN(0);
610 if (win < 6)
611 base += soft->bs_slot[slot].bss_window[win].bssw_base;
612 else if (map->bp_space == PCIIO_SPACE_ROM)
613 base += pcibr_info->f_rbase;
614 if ((pci_addr >= base) && (pci_addr < (base + size)))
615 atomic_inc(&map->bp_toc[0]);
616 }
617 }
618 }
619 }
620 }
621
622 /*
623 * PCI Bridge Error interrupt handler.
624 * This gets invoked, whenever a PCI bridge sends an error interrupt.
625 * Primarily this servers two purposes.
626 * - If an error can be handled (typically a PIO read/write
627 * error, we try to do it silently.
628 * - If an error cannot be handled, we die violently.
629 * Interrupt due to PIO errors:
630 * - Bridge sends an interrupt, whenever a PCI operation
631 * done by the bridge as the master fails. Operations could
632 * be either a PIO read or a PIO write.
633 * PIO Read operation also triggers a bus error, and it's
634 * We primarily ignore this interrupt in that context..
635 * For PIO write errors, this is the only indication.
636 * and we have to handle with the info from here.
637 *
638 * So, there is no way to distinguish if an interrupt is
639 * due to read or write error!.
640 */
641
642 void
pcibr_error_intr_handler(int irq,void * arg,struct pt_regs * ep)643 pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep)
644 {
645 pcibr_soft_t pcibr_soft;
646 bridge_t *bridge;
647 uint64_t int_status;
648 uint64_t err_status;
649 bridgereg_t int_status_32;
650 picreg_t int_status_64;
651 int number_bits;
652 int i;
653 uint64_t disable_errintr_mask = 0;
654 nasid_t nasid;
655
656
657 #if PCIBR_SOFT_LIST
658 /*
659 * Defensive code for linked pcibr_soft structs
660 */
661 {
662 extern pcibr_list_p pcibr_list;
663 pcibr_list_p entry;
664
665 entry = pcibr_list;
666 while (1) {
667 if (entry == NULL) {
668 panic("pcibr_error_intr_handler:\tmy parameter (0x%p) is not a pcibr_soft!", arg);
669 }
670 if ((intr_arg_t) entry->bl_soft == arg)
671 break;
672 entry = entry->bl_next;
673 }
674 }
675 #endif /* PCIBR_SOFT_LIST */
676 pcibr_soft = (pcibr_soft_t) arg;
677 bridge = pcibr_soft->bs_base;
678
679 /*
680 * pcibr_error_intr_handler gets invoked whenever bridge encounters
681 * an error situation, and the interrupt for that error is enabled.
682 * This routine decides if the error is fatal or not, and takes
683 * action accordingly.
684 *
685 * In the case of PIO read/write timeouts, there is no way
686 * to know if it was a read or write request that timed out.
687 * If the error was due to a "read", a bus error will also occur
688 * and the bus error handling code takes care of it.
689 * If the error is due to a "write", the error is currently logged
690 * by this routine. For SN1 and SN0, if fire-and-forget mode is
691 * disabled, a write error response xtalk packet will be sent to
692 * the II, which will cause an II error interrupt. No write error
693 * recovery actions of any kind currently take place at the pcibr
694 * layer! (e.g., no panic on unrecovered write error)
695 *
696 * Prior to reading the Bridge int_status register we need to ensure
697 * that there are no error bits set in the lower layers (hubii)
698 * that have disabled PIO access to the widget. If so, there is nothing
699 * we can do until the bits clear, so we setup a timeout and try again
700 * later.
701 */
702
703 nasid = NASID_GET(bridge);
704 if (hubii_check_widget_disabled(nasid, pcibr_soft->bs_xid)) {
705 DECLARE_WAIT_QUEUE_HEAD(wq);
706 sleep_on_timeout(&wq, BRIDGE_PIOERR_TIMEOUT*HZ ); /* sleep */
707 pcibr_soft->bs_errinfo.bserr_toutcnt++;
708 /* Let's go recursive */
709 return(pcibr_error_intr_handler(irq, arg, ep));
710 }
711
712 /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a
713 * 32bit bridgereg_t for BRIDGE, but always process the result as a
714 * 64bit value so the code can be "common" for both PIC and BRIDGE...
715 */
716 if (IS_PIC_SOFT(pcibr_soft)) {
717 int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK);
718 int_status = (uint64_t)int_status_64;
719 number_bits = PCIBR_ISR_MAX_ERRS_PIC;
720 } else {
721 int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
722 int_status = ((uint64_t)int_status_32) & 0xffffffff;
723 number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE;
724 }
725
726 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ERROR, pcibr_soft->bs_conn,
727 "pcibr_error_intr_handler: int_status=0x%x\n", int_status));
728
729 /* int_status is which bits we have to clear;
730 * err_status is the bits we haven't handled yet.
731 */
732 err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
733
734 if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
735 /*
736 * No error bit set!!.
737 */
738 return;
739 }
740 /*
741 * If we have a PCIBUS_PIOERR, hand it to the logger.
742 */
743 if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
744 pcibr_pioerr_check(pcibr_soft);
745 }
746
747 if (err_status) {
748 struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
749
750 for (i = PCIBR_ISR_ERR_START; i < number_bits; i++, bs_estat++) {
751 if (err_status & (1ull << i)) {
752 uint32_t errrate = 0;
753 uint32_t errcount = 0;
754 uint32_t errinterval = 0, current_tick = 0;
755 int llp_tx_retry_errors = 0;
756 int is_llp_tx_retry_intr = 0;
757
758 bs_estat->bs_errcount_total++;
759
760 current_tick = jiffies;
761 errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
762 errcount = (bs_estat->bs_errcount_total -
763 bs_estat->bs_lasterr_snapshot);
764
765 /* LLP interrrupt errors are only valid on BUS0 of the PIC */
766 if (pcibr_soft->bs_busnum == 0)
767 is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY==(1ull << i));
768
769 /* Check for the divide by zero condition while
770 * calculating the error rates.
771 */
772
773 if (errinterval) {
774 errrate = errcount / errinterval;
775 /* If able to calculate error rate
776 * on a LLP transmitter retry interrupt, check
777 * if the error rate is nonzero and we have seen
778 * a certain minimum number of errors.
779 *
780 * NOTE : errcount is being compared to
781 * PCIBR_ERRTIME_THRESHOLD to make sure that we are not
782 * seeing cases like x error interrupts per y ticks for
783 * very low x ,y (x > y ) which could result in a
784 * rate > 100/tick.
785 */
786 if (is_llp_tx_retry_intr &&
787 errrate &&
788 (errcount >= PCIBR_ERRTIME_THRESHOLD)) {
789 llp_tx_retry_errors = 1;
790 }
791 } else {
792 errrate = 0;
793 /* Since we are not able to calculate the
794 * error rate check if we exceeded a certain
795 * minimum number of errors for LLP transmitter
796 * retries. Note that this can only happen
797 * within the first tick after the last snapshot.
798 */
799 if (is_llp_tx_retry_intr &&
800 (errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
801 llp_tx_retry_errors = 1;
802 }
803 }
804
805 /*
806 * If a non-zero error rate (which is equivalent to
807 * to 100 errors/tick at least) for the LLP transmitter
808 * retry interrupt was seen, check if we should print
809 * a warning message.
810 */
811
812 if (llp_tx_retry_errors) {
813 static uint32_t last_printed_rate;
814
815 if (errrate > last_printed_rate) {
816 last_printed_rate = errrate;
817 /* Print the warning only if the error rate
818 * for the transmitter retry interrupt
819 * exceeded the previously printed rate.
820 */
821 printk(KERN_WARNING
822 "%s: %s, Excessive error interrupts : %d/tick\n",
823 pcibr_soft->bs_name,
824 pcibr_isr_errs[i],
825 errrate);
826
827 }
828 /*
829 * Update snapshot, and time
830 */
831 bs_estat->bs_lasterr_timestamp = current_tick;
832 bs_estat->bs_lasterr_snapshot =
833 bs_estat->bs_errcount_total;
834
835 }
836 /*
837 * If the error rate is high enough, print the error rate.
838 */
839 if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
840
841 if (errrate > PCIBR_ERRRATE_THRESHOLD) {
842 printk(KERN_NOTICE "%s: %s, Error rate %d/tick",
843 pcibr_soft->bs_name,
844 pcibr_isr_errs[i],
845 errrate);
846 /*
847 * Update snapshot, and time
848 */
849 bs_estat->bs_lasterr_timestamp = current_tick;
850 bs_estat->bs_lasterr_snapshot =
851 bs_estat->bs_errcount_total;
852 }
853 }
854 /* PIC BRINGUP WAR (PV# 856155):
855 * Dont disable PCI_X_ARB_ERR interrupts, we need the
856 * interrupt inorder to clear the DEV_BROKE bits in
857 * b_arb register to re-enable the device.
858 */
859 if (IS_PIC_SOFT(pcibr_soft) &&
860 !(err_status & PIC_ISR_PCIX_ARB_ERR) &&
861 PCIBR_WAR_ENABLED(PV856155, pcibr_soft)) {
862
863 if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
864 /*
865 * We have seen a fairly large number of errors of
866 * this type. Let's disable the interrupt. But flash
867 * a message about the interrupt being disabled.
868 */
869 printk(KERN_NOTICE
870 "%s Disabling error interrupt type %s. Error count %d",
871 pcibr_soft->bs_name,
872 pcibr_isr_errs[i],
873 bs_estat->bs_errcount_total);
874 disable_errintr_mask |= (1ull << i);
875 }
876 } /* PIC: WAR for PV 856155 end-of-if */
877 }
878 }
879 }
880
881 if (disable_errintr_mask) {
882 unsigned s;
883 /*
884 * Disable some high frequency errors as they
885 * could eat up too much cpu time.
886 */
887 s = pcibr_lock(pcibr_soft);
888 if (IS_PIC_SOFT(pcibr_soft)) {
889 bridge->p_int_enable_64 &= (picreg_t)(~disable_errintr_mask);
890 } else {
891 bridge->b_int_enable &= (bridgereg_t)(~disable_errintr_mask);
892 }
893 pcibr_unlock(pcibr_soft, s);
894 }
895 /*
896 * If we leave the PROM cacheable, T5 might
897 * try to do a cache line sized writeback to it,
898 * which will cause a BRIDGE_ISR_INVLD_ADDR.
899 */
900 if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
901 (0x00000000 == bridge->b_wid_err_upper) &&
902 (0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
903 (0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
904 err_status &= ~BRIDGE_ISR_INVLD_ADDR;
905 }
906 /*
907 * The bridge bug (PCIBR_LLP_CONTROL_WAR), where the llp_config or control registers
908 * need to be read back after being written, affects an MP
909 * system since there could be small windows between writing
910 * the register and reading it back on one cpu while another
911 * cpu is fielding an interrupt. If we run into this scenario,
912 * workaround the problem by ignoring the error. (bug 454474)
913 * pcibr_llp_control_war_cnt keeps an approximate number of
914 * times we saw this problem on a system.
915 */
916
917 if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
918 ((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
919 == (BRIDGE_INT_RST_STAT & 0xff0))) {
920 pcibr_llp_control_war_cnt++;
921 err_status &= ~BRIDGE_ISR_INVLD_ADDR;
922 }
923
924 bridge_errors_to_dump |= BRIDGE_ISR_PCIBUS_PIOERR;
925
926 /* Dump/Log Bridge error interrupt info */
927 if (err_status & bridge_errors_to_dump) {
928 printk("BRIDGE ERR_STATUS 0x%lx\n", err_status);
929 pcibr_error_dump(pcibr_soft);
930 }
931
932 /* PIC BRINGUP WAR (PV# 867308):
933 * Make BRIDGE_ISR_LLP_REC_SNERR & BRIDGE_ISR_LLP_REC_CBERR fatal errors
934 * so we know we've hit the problem defined in PV 867308 that we believe
935 * has only been seen in simulation
936 */
937 if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV867308, pcibr_soft) &&
938 (err_status & (BRIDGE_ISR_LLP_REC_SNERR | BRIDGE_ISR_LLP_REC_CBERR))) {
939 printk("BRIDGE ERR_STATUS 0x%lx\n", err_status);
940 pcibr_error_dump(pcibr_soft);
941 panic("PCI Bridge Error interrupt killed the system");
942 }
943
944 if (err_status & BRIDGE_ISR_ERROR_FATAL) {
945 panic("PCI Bridge Error interrupt killed the system");
946 /*NOTREACHED */
947 }
948
949
950 /*
951 * We can't return without re-enabling the interrupt, since
952 * it would cause problems for devices like IOC3 (Lost
953 * interrupts ?.). So, just cleanup the interrupt, and
954 * use saved values later..
955 *
956 * PIC doesn't require groups of interrupts to be cleared...
957 */
958 if (IS_PIC_SOFT(pcibr_soft)) {
959 bridge->p_int_rst_stat_64 = (picreg_t)(int_status | BRIDGE_IRR_MULTI_CLR);
960 } else {
961 bridge->b_int_rst_stat = (bridgereg_t)pcibr_errintr_group(int_status);
962 }
963
964 /* PIC BRINGUP WAR (PV# 856155):
965 * On a PCI_X_ARB_ERR error interrupt clear the DEV_BROKE bits from
966 * the b_arb register to re-enable the device.
967 */
968 if (IS_PIC_SOFT(pcibr_soft) &&
969 (err_status & PIC_ISR_PCIX_ARB_ERR) &&
970 PCIBR_WAR_ENABLED(PV856155, pcibr_soft)) {
971 bridge->b_arb |= (0xf << 20);
972 }
973
974 /* Zero out bserr_intstat field */
975 pcibr_soft->bs_errinfo.bserr_intstat = 0;
976 }
977
978 void
pcibr_error_cleanup(pcibr_soft_t pcibr_soft,int error_code)979 pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
980 {
981 bridge_t *bridge = pcibr_soft->bs_base;
982
983 ASSERT(error_code & IOECODE_PIO);
984 error_code = error_code;
985
986 if (IS_PIC_SOFT(pcibr_soft)) {
987 bridge->p_int_rst_stat_64 = BRIDGE_IRR_PCI_GRP_CLR |
988 PIC_PCIX_GRP_CLR |
989 BRIDGE_IRR_MULTI_CLR;
990 } else {
991 bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR;
992 }
993
994 (void) bridge->b_wid_tflush; /* flushbus */
995 }
996
997 /*ARGSUSED */
998 void
pcibr_device_disable(pcibr_soft_t pcibr_soft,int devnum)999 pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
1000 {
1001 /*
1002 * XXX
1003 * Device failed to handle error. Take steps to
1004 * disable this device ? HOW TO DO IT ?
1005 *
1006 * If there are any Read response buffers associated
1007 * with this device, it's time to get them back!!
1008 *
1009 * We can disassociate any interrupt level associated
1010 * with this device, and disable that interrupt level
1011 *
1012 * For now it's just a place holder
1013 */
1014 }
1015
1016 /*
1017 * pcibr_pioerror
1018 * Handle PIO error that happened at the bridge pointed by pcibr_soft.
1019 *
1020 * Queries the Bus interface attached to see if the device driver
1021 * mapping the device-number that caused error can handle the
1022 * situation. If so, it will clean up any error, and return
1023 * indicating the error was handled. If the device driver is unable
1024 * to handle the error, it expects the bus-interface to disable that
1025 * device, and takes any steps needed here to take away any resources
1026 * associated with this device.
1027 */
1028
1029 /* BEM_ADD_IOE doesn't dump the whole ioerror, it just
1030 * decodes the PCI specific portions -- we count on our
1031 * callers to dump the raw IOE data.
1032 */
1033 #define BEM_ADD_IOE(ioe) \
1034 do { \
1035 if (IOERROR_FIELDVALID(ioe, busspace)) { \
1036 iopaddr_t spc; \
1037 iopaddr_t win; \
1038 short widdev; \
1039 iopaddr_t busaddr; \
1040 \
1041 IOERROR_GETVALUE(spc, ioe, busspace); \
1042 win = spc - PCIIO_SPACE_WIN(0); \
1043 IOERROR_GETVALUE(busaddr, ioe, busaddr); \
1044 IOERROR_GETVALUE(widdev, ioe, widgetdev); \
1045 \
1046 switch (spc) { \
1047 case PCIIO_SPACE_CFG: \
1048 printk("\tPCI Slot %d Func %d CFG space Offset 0x%lx\n",\
1049 pciio_widgetdev_slot_get(widdev), \
1050 pciio_widgetdev_func_get(widdev), \
1051 busaddr); \
1052 break; \
1053 case PCIIO_SPACE_IO: \
1054 printk("\tPCI I/O space Offset 0x%lx\n", busaddr); \
1055 break; \
1056 case PCIIO_SPACE_MEM: \
1057 case PCIIO_SPACE_MEM32: \
1058 case PCIIO_SPACE_MEM64: \
1059 printk("\tPCI MEM space Offset 0x%lx\n", busaddr); \
1060 break; \
1061 default: \
1062 if (win < 6) { \
1063 printk("\tPCI Slot %d Func %d Window %ld Offset 0x%lx\n",\
1064 pciio_widgetdev_slot_get(widdev), \
1065 pciio_widgetdev_func_get(widdev), \
1066 win, \
1067 busaddr); \
1068 } \
1069 break; \
1070 } \
1071 } \
1072 } while (0)
1073
1074 /*ARGSUSED */
1075 int
pcibr_pioerror(pcibr_soft_t pcibr_soft,int error_code,ioerror_mode_t mode,ioerror_t * ioe)1076 pcibr_pioerror(
1077 pcibr_soft_t pcibr_soft,
1078 int error_code,
1079 ioerror_mode_t mode,
1080 ioerror_t *ioe)
1081 {
1082 int retval = IOERROR_HANDLED;
1083
1084 vertex_hdl_t pcibr_vhdl = pcibr_soft->bs_vhdl;
1085 #if defined(FORCE_ERRORS)
1086 bridge_t *bridge = pcibr_soft->bs_base;
1087 #endif
1088
1089 iopaddr_t bad_xaddr;
1090
1091 pciio_space_t raw_space; /* raw PCI space */
1092 iopaddr_t raw_paddr; /* raw PCI address */
1093
1094 pciio_space_t space; /* final PCI space */
1095 pciio_slot_t slot; /* final PCI slot, if appropriate */
1096 pciio_function_t func; /* final PCI func, if appropriate */
1097 iopaddr_t offset; /* final PCI offset */
1098
1099 int cs, cw, cf;
1100 pciio_space_t wx;
1101 iopaddr_t wb;
1102 size_t ws;
1103 iopaddr_t wl;
1104
1105
1106 /*
1107 * We expect to have an "xtalkaddr" coming in,
1108 * and need to construct the slot/space/offset.
1109 */
1110
1111 IOERROR_GETVALUE(bad_xaddr, ioe, xtalkaddr);
1112
1113 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn,
1114 "pcibr_pioerror: pcibr_soft=0x%x, bad_xaddr=0x%x\n",
1115 pcibr_soft, bad_xaddr));
1116
1117 slot = PCIIO_SLOT_NONE;
1118 func = PCIIO_FUNC_NONE;
1119 raw_space = PCIIO_SPACE_NONE;
1120 raw_paddr = 0;
1121
1122 if ((bad_xaddr >= PCIBR_BUS_TYPE0_CFG_DEV0(pcibr_soft)) &&
1123 (bad_xaddr < PCIBR_TYPE1_CFG(pcibr_soft))) {
1124 raw_paddr = bad_xaddr - PCIBR_BUS_TYPE0_CFG_DEV0(pcibr_soft);
1125 slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
1126 raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
1127 raw_space = PCIIO_SPACE_CFG;
1128 }
1129 if ((bad_xaddr >= PCIBR_TYPE1_CFG(pcibr_soft)) &&
1130 (bad_xaddr < (PCIBR_TYPE1_CFG(pcibr_soft) + 0x1000))) {
1131 /* Type 1 config space:
1132 * slot and function numbers not known.
1133 * Perhaps we can read them back?
1134 */
1135 raw_paddr = bad_xaddr - PCIBR_TYPE1_CFG(pcibr_soft);
1136 raw_space = PCIIO_SPACE_CFG;
1137 }
1138 if ((bad_xaddr >= PCIBR_BRIDGE_DEVIO0(pcibr_soft)) &&
1139 (bad_xaddr < PCIBR_BRIDGE_DEVIO(pcibr_soft, BRIDGE_DEV_CNT))) {
1140 int x;
1141
1142 raw_paddr = bad_xaddr - PCIBR_BRIDGE_DEVIO0(pcibr_soft);
1143 x = raw_paddr / BRIDGE_DEVIO_OFF;
1144 raw_paddr %= BRIDGE_DEVIO_OFF;
1145 /* first two devio windows are double-sized */
1146 if ((x == 1) || (x == 3))
1147 raw_paddr += BRIDGE_DEVIO_OFF;
1148 if (x > 0)
1149 x--;
1150 if (x > 1)
1151 x--;
1152 /* x is which devio reg; no guarantee
1153 * PCI slot x will be responding.
1154 * still need to figure out who decodes
1155 * space/offset on the bus.
1156 */
1157 raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
1158 if (raw_space == PCIIO_SPACE_NONE) {
1159 /* Someone got an error because they
1160 * accessed the PCI bus via a DevIO(x)
1161 * window that pcibr has not yet assigned
1162 * to any specific PCI address. It is
1163 * quite possible that the Device(x)
1164 * register has been changed since they
1165 * made their access, but we will give it
1166 * our best decode shot.
1167 */
1168 raw_space = pcibr_soft->bs_slot[x].bss_device
1169 & BRIDGE_DEV_DEV_IO_MEM
1170 ? PCIIO_SPACE_MEM
1171 : PCIIO_SPACE_IO;
1172 raw_paddr +=
1173 (pcibr_soft->bs_slot[x].bss_device &
1174 BRIDGE_DEV_OFF_MASK) <<
1175 BRIDGE_DEV_OFF_ADDR_SHFT;
1176 } else
1177 raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
1178 }
1179 if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
1180 (bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
1181 raw_space = PCIIO_SPACE_MEM32;
1182 raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
1183 }
1184 if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
1185 (bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
1186 raw_space = PCIIO_SPACE_MEM64;
1187 raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
1188 }
1189 if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
1190 (bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
1191 raw_space = PCIIO_SPACE_IO;
1192 raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
1193 }
1194 space = raw_space;
1195 offset = raw_paddr;
1196
1197 if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
1198 /* we've got a space/offset but not which
1199 * PCI slot decodes it. Check through our
1200 * notions of which devices decode where.
1201 *
1202 * Yes, this "duplicates" some logic in
1203 * pcibr_addr_toslot; the difference is,
1204 * this code knows which space we are in,
1205 * and can really really tell what is
1206 * going on (no guessing).
1207 */
1208
1209 for (cs = pcibr_soft->bs_min_slot;
1210 (cs < PCIBR_NUM_SLOTS(pcibr_soft)) &&
1211 (slot == PCIIO_SLOT_NONE); cs++) {
1212 int nf = pcibr_soft->bs_slot[cs].bss_ninfo;
1213 pcibr_info_h pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
1214
1215 for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
1216 pcibr_info_t pcibr_info = pcibr_infoh[cf];
1217
1218 if (!pcibr_info)
1219 continue;
1220 for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
1221 if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
1222 ((wb = pcibr_info->f_window[cw].w_base) != 0) &&
1223 ((ws = pcibr_info->f_window[cw].w_size) != 0) &&
1224 ((wl = wb + ws) > wb) &&
1225 ((wb <= offset) && (wl > offset))) {
1226 /* MEM, MEM32 and MEM64 need to
1227 * compare as equal ...
1228 */
1229 if ((wx == space) ||
1230 (((wx == PCIIO_SPACE_MEM) ||
1231 (wx == PCIIO_SPACE_MEM32) ||
1232 (wx == PCIIO_SPACE_MEM64)) &&
1233 ((space == PCIIO_SPACE_MEM) ||
1234 (space == PCIIO_SPACE_MEM32) ||
1235 (space == PCIIO_SPACE_MEM64)))) {
1236 slot = cs;
1237 func = cf;
1238 space = PCIIO_SPACE_WIN(cw);
1239 offset -= wb;
1240 } /* endif window space match */
1241 } /* endif window valid and addr match */
1242 } /* next window unless slot set */
1243 } /* next func unless slot set */
1244 } /* next slot unless slot set */
1245 /* XXX- if slot is still -1, no PCI devices are
1246 * decoding here using their standard PCI BASE
1247 * registers. This would be a really good place
1248 * to cross-coordinate with the pciio PCI
1249 * address space allocation routines, to find
1250 * out if this address is "allocated" by any of
1251 * our subsidiary devices.
1252 */
1253 }
1254 /* Scan all piomap records on this PCI bus to update
1255 * the TimeOut Counters on all matching maps. If we
1256 * don't already know the slot number, take it from
1257 * the first matching piomap. Note that we have to
1258 * compare maps against raw_space and raw_paddr
1259 * since space and offset could already be
1260 * window-relative.
1261 *
1262 * There is a chance that one CPU could update
1263 * through this path, and another CPU could also
1264 * update due to an interrupt. Closing this hole
1265 * would only result in the possibility of some
1266 * errors never getting logged at all, and since the
1267 * use for bp_toc is as a logical test rather than a
1268 * strict count, the excess counts are not a
1269 * problem.
1270 */
1271 for (cs = pcibr_soft->bs_min_slot;
1272 cs < PCIBR_NUM_SLOTS(pcibr_soft); ++cs) {
1273 int nf = pcibr_soft->bs_slot[cs].bss_ninfo;
1274 pcibr_info_h pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
1275
1276 for (cf = 0; cf < nf; cf++) {
1277 pcibr_info_t pcibr_info = pcibr_infoh[cf];
1278 pcibr_piomap_t map;
1279
1280 if (!pcibr_info)
1281 continue;
1282
1283 for (map = pcibr_info->f_piomap;
1284 map != NULL; map = map->bp_next) {
1285 wx = map->bp_space;
1286 wb = map->bp_pciaddr;
1287 ws = map->bp_mapsz;
1288 cw = wx - PCIIO_SPACE_WIN(0);
1289 if (cw < 6) {
1290 wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
1291 wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
1292 }
1293 if (wx == PCIIO_SPACE_ROM) {
1294 wb += pcibr_info->f_rbase;
1295 wx = PCIIO_SPACE_MEM;
1296 }
1297 if ((wx == PCIIO_SPACE_MEM32) ||
1298 (wx == PCIIO_SPACE_MEM64))
1299 wx = PCIIO_SPACE_MEM;
1300 wl = wb + ws;
1301 if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
1302 atomic_inc(&map->bp_toc[0]);
1303 if (slot == PCIIO_SLOT_NONE) {
1304 slot = cs;
1305 space = map->bp_space;
1306 if (cw < 6)
1307 offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
1308 }
1309 }
1310 }
1311 }
1312 }
1313
1314 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn,
1315 "pcibr_pioerror: offset=0x%x, slot=0x%x, func=0x%x\n",
1316 offset, slot, func));
1317
1318 if (space != PCIIO_SPACE_NONE) {
1319 if (slot != PCIIO_SLOT_NONE) {
1320 if (func != PCIIO_FUNC_NONE) {
1321 IOERROR_SETVALUE(ioe, widgetdev,
1322 pciio_widgetdev_create(slot,func));
1323 }
1324 else {
1325 IOERROR_SETVALUE(ioe, widgetdev,
1326 pciio_widgetdev_create(slot,0));
1327 }
1328 }
1329 IOERROR_SETVALUE(ioe, busspace, space);
1330 IOERROR_SETVALUE(ioe, busaddr, offset);
1331 }
1332 if (mode == MODE_DEVPROBE) {
1333 /*
1334 * During probing, we don't really care what the
1335 * error is. Clean up the error in Bridge, notify
1336 * subsidiary devices, and return success.
1337 */
1338 pcibr_error_cleanup(pcibr_soft, error_code);
1339
1340 /* if appropriate, give the error handler for this slot
1341 * a shot at this probe access as well.
1342 */
1343 return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
1344 pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
1345 }
1346 /*
1347 * If we don't know what "PCI SPACE" the access
1348 * was targeting, we may have problems at the
1349 * Bridge itself. Don't touch any bridge registers,
1350 * and do complain loudly.
1351 */
1352
1353 if (space == PCIIO_SPACE_NONE) {
1354 printk("XIO Bus Error at %s\n"
1355 "\taccess to XIO bus offset 0x%lx\n"
1356 "\tdoes not correspond to any PCI address\n",
1357 pcibr_soft->bs_name, bad_xaddr);
1358
1359 /* caller will dump contents of ioe struct */
1360 return IOERROR_XTALKLEVEL;
1361 }
1362
1363 /*
1364 * Actual PCI Error handling situation.
1365 * Typically happens when a user level process accesses
1366 * PCI space, and it causes some error.
1367 *
1368 * Due to PCI Bridge implementation, we get two indication
1369 * for a read error: an interrupt and a Bus error.
1370 * We like to handle read error in the bus error context.
1371 * But the interrupt comes and goes before bus error
1372 * could make much progress. (NOTE: interrupd does
1373 * come in _after_ bus error processing starts. But it's
1374 * completed by the time bus error code reaches PCI PIO
1375 * error handling.
1376 * Similarly write error results in just an interrupt,
1377 * and error handling has to be done at interrupt level.
1378 * There is no way to distinguish at interrupt time, if an
1379 * error interrupt is due to read/write error..
1380 */
1381
1382 /* We know the xtalk addr, the raw PCI bus space,
1383 * the raw PCI bus address, the decoded PCI bus
1384 * space, the offset within that space, and the
1385 * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
1386 * is known to be involved).
1387 */
1388
1389 /*
1390 * Hand the error off to the handler registered
1391 * for the slot that should have decoded the error,
1392 * or to generic PCI handling (if pciio decides that
1393 * such is appropriate).
1394 */
1395 retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
1396
1397 if (retval != IOERROR_HANDLED) {
1398
1399 /* Generate a generic message for IOERROR_UNHANDLED
1400 * since the subsidiary handlers were silent, and
1401 * did no recovery.
1402 */
1403 if (retval == IOERROR_UNHANDLED) {
1404 retval = IOERROR_PANIC;
1405
1406 /* we may or may not want to print some of this,
1407 * depending on debug level and which error code.
1408 */
1409
1410 printk(KERN_ALERT
1411 "PIO Error on PCI Bus %s",
1412 pcibr_soft->bs_name);
1413 /* this decodes part of the ioe; our caller
1414 * will dump the raw details in DEBUG and
1415 * kdebug kernels.
1416 */
1417 BEM_ADD_IOE(ioe);
1418 }
1419 #if defined(FORCE_ERRORS)
1420 if (0) {
1421 /*
1422 * Dump raw data from Bridge/PCI layer.
1423 */
1424
1425 BEM_ADD_STR("Raw info from Bridge/PCI layer:\n");
1426 if (IS_PIC_SOFT(pcibr_soft)) {
1427 if (bridge->p_int_status_64 & (picreg_t)BRIDGE_ISR_PCIBUS_PIOERR)
1428 pcibr_error_dump(pcibr_soft);
1429 } else {
1430 if (bridge->b_int_status & (bridgereg_t)BRIDGE_ISR_PCIBUS_PIOERR)
1431 pcibr_error_dump(pcibr_soft);
1432 }
1433 BEM_ADD_SPC(raw_space);
1434 BEM_ADD_VAR(raw_paddr);
1435 if (IOERROR_FIELDVALID(ioe, widgetdev)) {
1436 short widdev;
1437 IOERROR_GETVALUE(widdev, ioe, widgetdev);
1438 slot = pciio_widgetdev_slot_get(widdev);
1439 func = pciio_widgetdev_func_get(widdev);
1440 if (slot < PCIBR_NUM_SLOTS(pcibr_soft)) {
1441 bridgereg_t device = bridge->b_device[slot].reg;
1442
1443 BEM_ADD_VAR(slot);
1444 BEM_ADD_VAR(func);
1445 BEM_ADD_REG(device);
1446 }
1447 }
1448 }
1449 #endif /* FORCE_ERRORS */
1450
1451 /*
1452 * Since error could not be handled at lower level,
1453 * error data logged has not been cleared.
1454 * Clean up errors, and
1455 * re-enable bridge to interrupt on error conditions.
1456 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
1457 * dependent on INT_ENABLE register. This write just makes sure
1458 * that if the interrupt was enabled, we do get the interrupt.
1459 *
1460 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
1461 * a group of interrupts. If while handling this error,
1462 * some other error has occurred, that would be
1463 * implicitly cleared by this write.
1464 * Need a way to ensure we don't inadvertently clear some
1465 * other errors.
1466 */
1467 if (IOERROR_FIELDVALID(ioe, widgetdev)) {
1468 short widdev;
1469 IOERROR_GETVALUE(widdev, ioe, widgetdev);
1470 pcibr_device_disable(pcibr_soft,
1471 pciio_widgetdev_slot_get(widdev));
1472 }
1473 if (mode == MODE_DEVUSERERROR)
1474 pcibr_error_cleanup(pcibr_soft, error_code);
1475 }
1476 return retval;
1477 }
1478
1479 /*
1480 * bridge_dmaerror
1481 * Some error was identified in a DMA transaction.
1482 * This routine will identify the <device, address> that caused the error,
1483 * and try to invoke the appropriate bus service to handle this.
1484 */
1485
1486 int
pcibr_dmard_error(pcibr_soft_t pcibr_soft,int error_code,ioerror_mode_t mode,ioerror_t * ioe)1487 pcibr_dmard_error(
1488 pcibr_soft_t pcibr_soft,
1489 int error_code,
1490 ioerror_mode_t mode,
1491 ioerror_t *ioe)
1492 {
1493 vertex_hdl_t pcibr_vhdl = pcibr_soft->bs_vhdl;
1494 bridge_t *bridge = pcibr_soft->bs_base;
1495 bridgereg_t bus_lowaddr, bus_uppraddr;
1496 int retval = 0;
1497 int bufnum;
1498
1499 /*
1500 * In case of DMA errors, bridge should have logged the
1501 * address that caused the error.
1502 * Look up the address, in the bridge error registers, and
1503 * take appropriate action
1504 */
1505 {
1506 short tmp;
1507 IOERROR_GETVALUE(tmp, ioe, widgetnum);
1508 ASSERT(tmp == pcibr_soft->bs_xid);
1509 }
1510 ASSERT(bridge);
1511
1512 /*
1513 * read error log registers
1514 */
1515 bus_lowaddr = bridge->b_wid_resp_lower;
1516 bus_uppraddr = bridge->b_wid_resp_upper;
1517
1518 bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
1519 IOERROR_SETVALUE(ioe, widgetdev,
1520 pciio_widgetdev_create(
1521 BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
1522 0));
1523 IOERROR_SETVALUE(ioe, busaddr,
1524 (bus_lowaddr |
1525 ((iopaddr_t)
1526 (bus_uppraddr &
1527 BRIDGE_ERRUPPR_ADDRMASK) << 32)));
1528
1529 /*
1530 * need to ensure that the xtalk address in ioe
1531 * maps to PCI error address read from bridge.
1532 * How to convert PCI address back to Xtalk address ?
1533 * (better idea: convert XTalk address to PCI address
1534 * and then do the compare!)
1535 */
1536
1537 retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
1538 if (retval != IOERROR_HANDLED) {
1539 short tmp;
1540 IOERROR_GETVALUE(tmp, ioe, widgetdev);
1541 pcibr_device_disable(pcibr_soft, pciio_widgetdev_slot_get(tmp));
1542 }
1543
1544 /*
1545 * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
1546 * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
1547 * not is dependent on INT_ENABLE register. This write just makes sure
1548 * that if the interrupt was enabled, we do get the interrupt.
1549 */
1550 bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
1551
1552 /*
1553 * Also, release the "bufnum" back to buffer pool that could be re-used.
1554 * This is done by "disabling" the buffer for a moment, then restoring
1555 * the original assignment.
1556 */
1557
1558 {
1559 reg_p regp;
1560 bridgereg_t regv;
1561 bridgereg_t mask;
1562
1563 regp = (bufnum & 1)
1564 ? &bridge->b_odd_resp
1565 : &bridge->b_even_resp;
1566
1567 mask = 0xF << ((bufnum >> 1) * 4);
1568
1569 regv = *regp;
1570 *regp = regv & ~mask;
1571 *regp = regv;
1572 }
1573
1574 return retval;
1575 }
1576
1577 /*
1578 * pcibr_dmawr_error:
1579 * Handle a dma write error caused by a device attached to this bridge.
1580 *
1581 * ioe has the widgetnum, widgetdev, and memaddr fields updated
1582 * But we don't know the PCI address that corresponds to "memaddr"
1583 * nor do we know which device driver is generating this address.
1584 *
1585 * There is no easy way to find out the PCI address(es) that map
1586 * to a specific system memory address. Bus handling code is also
1587 * of not much help, since they don't keep track of the DMA mapping
1588 * that have been handed out.
1589 * So it's a dead-end at this time.
1590 *
1591 * If translation is available, we could invoke the error handling
1592 * interface of the device driver.
1593 */
1594 /*ARGSUSED */
1595 int
pcibr_dmawr_error(pcibr_soft_t pcibr_soft,int error_code,ioerror_mode_t mode,ioerror_t * ioe)1596 pcibr_dmawr_error(
1597 pcibr_soft_t pcibr_soft,
1598 int error_code,
1599 ioerror_mode_t mode,
1600 ioerror_t *ioe)
1601 {
1602 vertex_hdl_t pcibr_vhdl = pcibr_soft->bs_vhdl;
1603 int retval;
1604
1605 retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
1606
1607 if (retval != IOERROR_HANDLED) {
1608 short tmp;
1609
1610 IOERROR_GETVALUE(tmp, ioe, widgetdev);
1611 pcibr_device_disable(pcibr_soft, pciio_widgetdev_slot_get(tmp));
1612 }
1613 return retval;
1614 }
1615
1616 /*
1617 * Bridge error handler.
1618 * Interface to handle all errors that involve bridge in some way.
1619 *
1620 * This normally gets called from xtalk error handler.
1621 * ioe has different set of fields set depending on the error that
1622 * was encountered. So, we have a bit field indicating which of the
1623 * fields are valid.
1624 *
1625 * NOTE: This routine could be operating in interrupt context. So,
1626 * don't try to sleep here (till interrupt threads work!!)
1627 */
1628 int
pcibr_error_handler(error_handler_arg_t einfo,int error_code,ioerror_mode_t mode,ioerror_t * ioe)1629 pcibr_error_handler(
1630 error_handler_arg_t einfo,
1631 int error_code,
1632 ioerror_mode_t mode,
1633 ioerror_t *ioe)
1634 {
1635 pcibr_soft_t pcibr_soft;
1636 int retval = IOERROR_BADERRORCODE;
1637
1638 pcibr_soft = (pcibr_soft_t) einfo;
1639
1640 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn,
1641 "pcibr_error_handler: pcibr_soft=0x%x, error_code=0x%x\n",
1642 pcibr_soft, error_code));
1643
1644 #if DEBUG && ERROR_DEBUG
1645 printk( "%s: pcibr_error_handler\n", pcibr_soft->bs_name);
1646 #endif
1647
1648 ASSERT(pcibr_soft != NULL);
1649
1650 if (error_code & IOECODE_PIO)
1651 retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
1652
1653 if (error_code & IOECODE_DMA) {
1654 if (error_code & IOECODE_READ) {
1655 /*
1656 * DMA read error occurs when a device attached to the bridge
1657 * tries to read some data from system memory, and this
1658 * either results in a timeout or access error.
1659 * First case is indicated by the bit "XREAD_REQ_TOUT"
1660 * and second case by "RESP_XTALK_ERROR" bit in bridge error
1661 * interrupt status register.
1662 *
1663 * pcibr_error_intr_handler would get invoked first, and it has
1664 * the responsibility of calling pcibr_error_handler with
1665 * suitable parameters.
1666 */
1667
1668 retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
1669 }
1670 if (error_code & IOECODE_WRITE) {
1671 /*
1672 * A device attached to this bridge has been generating
1673 * bad DMA writes. Find out the device attached, and
1674 * slap on it's wrist.
1675 */
1676
1677 retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
1678 }
1679 }
1680 return retval;
1681
1682 }
1683
1684 /*
1685 * PIC has 2 busses under a single widget so pcibr_attach2 registers this
1686 * wrapper function rather than pcibr_error_handler() for PIC. It's upto
1687 * this wrapper to call pcibr_error_handler() with the correct pcibr_soft
1688 * struct (ie. the pcibr_soft struct for the bus that saw the error).
1689 *
1690 * NOTE: this wrapper function is only registered for PIC ASICs and will
1691 * only be called for a PIC
1692 */
1693 int
pcibr_error_handler_wrapper(error_handler_arg_t einfo,int error_code,ioerror_mode_t mode,ioerror_t * ioe)1694 pcibr_error_handler_wrapper(
1695 error_handler_arg_t einfo,
1696 int error_code,
1697 ioerror_mode_t mode,
1698 ioerror_t *ioe)
1699 {
1700 pcibr_soft_t pcibr_soft = (pcibr_soft_t) einfo;
1701 int pio_retval = -1;
1702 int dma_retval = -1;
1703
1704 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn,
1705 "pcibr_error_handler_wrapper: pcibr_soft=0x%x, "
1706 "error_code=0x%x\n", pcibr_soft, error_code));
1707
1708 /*
1709 * It is possible that both a IOECODE_PIO and a IOECODE_DMA, and both
1710 * IOECODE_READ and IOECODE_WRITE could be set in error_code so we must
1711 * process all. Since we are a wrapper for pcibr_error_handler(), and
1712 * will be calling it several times within this routine, we turn off the
1713 * error_code bits we don't want it to be processing during that call.
1714 */
1715 /*
1716 * If the error was a result of a PIO, we tell what bus on the PIC saw
1717 * the error from the PIO address.
1718 */
1719
1720 if (error_code & IOECODE_PIO) {
1721 iopaddr_t bad_xaddr;
1722 /*
1723 * PIC bus0 PIO space 0x000000 - 0x7fffff or 0x40000000 - 0xbfffffff
1724 * bus1 PIO space 0x800000 - 0xffffff or 0xc0000000 - 0x13fffffff
1725 */
1726 IOERROR_GETVALUE(bad_xaddr, ioe, xtalkaddr);
1727 if ((bad_xaddr <= 0x7fffff) ||
1728 ((bad_xaddr >= 0x40000000) && (bad_xaddr <= 0xbfffffff))) {
1729 /* bus 0 saw the error */
1730 pio_retval = pcibr_error_handler((error_handler_arg_t)pcibr_soft,
1731 (error_code & ~IOECODE_DMA), mode, ioe);
1732 } else if (((bad_xaddr >= 0x800000) && (bad_xaddr <= 0xffffff)) ||
1733 ((bad_xaddr >= 0xc0000000) && (bad_xaddr <= 0x13fffffff))) {
1734 /* bus 1 saw the error */
1735 pcibr_soft = pcibr_soft->bs_peers_soft;
1736 if (!pcibr_soft) {
1737 #if DEBUG
1738 printk(KERN_WARNING "pcibr_error_handler: "
1739 "bs_peers_soft==NULL. bad_xaddr= 0x%x mode= 0x%x\n",
1740 bad_xaddr, mode);
1741 #endif
1742 pio_retval = IOERROR_HANDLED;
1743 } else
1744 pio_retval= pcibr_error_handler((error_handler_arg_t)pcibr_soft,
1745 (error_code & ~IOECODE_DMA), mode, ioe);
1746 } else {
1747 printk(KERN_WARNING "pcibr_error_handler_wrapper(): IOECODE_PIO: "
1748 "saw an invalid pio address: 0x%lx\n", bad_xaddr);
1749 pio_retval = IOERROR_UNHANDLED;
1750 }
1751 }
1752
1753 /*
1754 * If the error was a result of a DMA Write, we tell what bus on the PIC
1755 * saw the error by looking at tnum.
1756 */
1757 if ((error_code & IOECODE_DMA) && (error_code & IOECODE_WRITE)) {
1758 short tmp;
1759 /*
1760 * For DMA writes [X]Bridge encodes the TNUM field of a Xtalk
1761 * packet like this:
1762 * bits value
1763 * 4:3 10b
1764 * 2:0 device number
1765 *
1766 * BUT PIC needs the bus number so it does this:
1767 * bits value
1768 * 4:3 10b
1769 * 2 busnumber
1770 * 1:0 device number
1771 *
1772 * Pull out the bus number from `tnum' and reset the `widgetdev'
1773 * since when hubiio_crb_error_handler() set `widgetdev' it had
1774 * no idea if it was a PIC or a BRIDGE ASIC so it set it based
1775 * off bits 2:0
1776 */
1777 IOERROR_GETVALUE(tmp, ioe, tnum);
1778 IOERROR_SETVALUE(ioe, widgetdev, (tmp & 0x3));
1779 if ((tmp & 0x4) == 0) {
1780 /* bus 0 saw the error. */
1781 dma_retval = pcibr_error_handler((error_handler_arg_t)pcibr_soft,
1782 (error_code & ~(IOECODE_PIO|IOECODE_READ)), mode, ioe);
1783 } else {
1784 /* bus 1 saw the error */
1785 pcibr_soft = pcibr_soft->bs_peers_soft;
1786 dma_retval = pcibr_error_handler((error_handler_arg_t)pcibr_soft,
1787 (error_code & ~(IOECODE_PIO|IOECODE_READ)), mode, ioe);
1788 }
1789 }
1790
1791 /*
1792 * If the error was a result of a DMA READ, XXX ???
1793 */
1794 if ((error_code & IOECODE_DMA) && (error_code & IOECODE_READ)) {
1795 /*
1796 * A DMA Read error will result in a BRIDGE_ISR_RESP_XTLK_ERR
1797 * or BRIDGE_ISR_BAD_XRESP_PKT bridge error interrupt which
1798 * are fatal interrupts (ie. BRIDGE_ISR_ERROR_FATAL) causing
1799 * pcibr_error_intr_handler() to panic the system. So is the
1800 * error handler even going to get called??? It appears that
1801 * the pcibr_dmard_error() attempts to clear the interrupts
1802 * so pcibr_error_intr_handler() won't see them, but there
1803 * appears to be nothing to prevent pcibr_error_intr_handler()
1804 * from running before pcibr_dmard_error() has a chance to
1805 * clear the interrupt.
1806 *
1807 * Since we'll be panicing anyways, don't bother handling the
1808 * error for now until we can fix this race condition mentioned
1809 * above.
1810 */
1811 dma_retval = IOERROR_UNHANDLED;
1812 }
1813
1814 /* XXX: pcibr_error_handler() should probably do the same thing, it over-
1815 * write it's return value as it processes the different "error_code"s.
1816 */
1817 if ((pio_retval == -1) && (dma_retval == -1)) {
1818 return IOERROR_BADERRORCODE;
1819 } else if (dma_retval != IOERROR_HANDLED) {
1820 return dma_retval;
1821 } else if (pio_retval != IOERROR_HANDLED) {
1822 return pio_retval;
1823 } else {
1824 return IOERROR_HANDLED;
1825 }
1826 }
1827