1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8
9 #include <linux/config.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/pci_ids.h>
14 #include <linux/sched.h>
15 #include <linux/ioport.h>
16 #include <asm/sn/types.h>
17 #include <asm/sn/sgi.h>
18 #include <asm/sn/io.h>
19 #include <asm/sn/driver.h>
20 #include <asm/sn/iograph.h>
21 #include <asm/param.h>
22 #include <asm/sn/pio.h>
23 #include <asm/sn/xtalk/xwidget.h>
24 #include <asm/sn/sn_private.h>
25 #include <asm/sn/addrs.h>
26 #include <asm/sn/invent.h>
27 #include <asm/sn/hcl.h>
28 #include <asm/sn/hcl_util.h>
29 #include <asm/sn/intr.h>
30 #include <asm/sn/xtalk/xtalkaddrs.h>
31 #include <asm/sn/klconfig.h>
32 #include <asm/sn/nodepda.h>
33 #include <asm/sn/pci/pciio.h>
34 #include <asm/sn/pci/pcibr.h>
35 #include <asm/sn/pci/pcibr_private.h>
36 #include <asm/sn/pci/pci_bus_cvlink.h>
37 #include <asm/sn/simulator.h>
38 #include <asm/sn/sn_cpuid.h>
39 #include <asm/sn/arch.h>
40
41 extern int bridge_rev_b_data_check_disable;
42
43 vertex_hdl_t busnum_to_pcibr_vhdl[MAX_PCI_XWIDGET];
44 nasid_t busnum_to_nid[MAX_PCI_XWIDGET];
45 void * busnum_to_atedmamaps[MAX_PCI_XWIDGET];
46 unsigned char num_bridges;
47 static int done_probing;
48 extern irqpda_t *irqpdaindr;
49
50 static int pci_bus_map_create(vertex_hdl_t xtalk, int brick_type, char * io_moduleid);
51 vertex_hdl_t devfn_to_vertex(unsigned char busnum, unsigned int devfn);
52
53 extern void register_pcibr_intr(int irq, pcibr_intr_t intr);
54
55 void sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int slot);
56
57 /*
58 * For the given device, initialize whether it is a PIC device.
59 */
60 static void
set_isPIC(struct sn_device_sysdata * device_sysdata)61 set_isPIC(struct sn_device_sysdata *device_sysdata)
62 {
63 pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
64 pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
65
66 device_sysdata->isPIC = IS_PIC_SOFT(pcibr_soft);;
67 }
68
69 /*
70 * pci_bus_cvlink_init() - To be called once during initialization before
71 * SGI IO Infrastructure init is called.
72 */
73 void
pci_bus_cvlink_init(void)74 pci_bus_cvlink_init(void)
75 {
76
77 extern void ioconfig_bus_init(void);
78
79 memset(busnum_to_pcibr_vhdl, 0x0, sizeof(vertex_hdl_t) * MAX_PCI_XWIDGET);
80 memset(busnum_to_nid, 0x0, sizeof(nasid_t) * MAX_PCI_XWIDGET);
81
82 memset(busnum_to_atedmamaps, 0x0, sizeof(void *) * MAX_PCI_XWIDGET);
83
84 num_bridges = 0;
85
86 ioconfig_bus_init();
87 }
88
89 /*
90 * pci_bus_to_vertex() - Given a logical Linux Bus Number returns the associated
91 * pci bus vertex from the SGI IO Infrastructure.
92 */
93 vertex_hdl_t
pci_bus_to_vertex(unsigned char busnum)94 pci_bus_to_vertex(unsigned char busnum)
95 {
96
97 vertex_hdl_t pci_bus = NULL;
98
99
100 /*
101 * First get the xwidget vertex.
102 */
103 pci_bus = busnum_to_pcibr_vhdl[busnum];
104 return(pci_bus);
105 }
106
107 /*
108 * devfn_to_vertex() - returns the vertex of the device given the bus, slot,
109 * and function numbers.
110 */
111 vertex_hdl_t
devfn_to_vertex(unsigned char busnum,unsigned int devfn)112 devfn_to_vertex(unsigned char busnum, unsigned int devfn)
113 {
114
115 int slot = 0;
116 int func = 0;
117 char name[16];
118 vertex_hdl_t pci_bus = NULL;
119 vertex_hdl_t device_vertex = (vertex_hdl_t)NULL;
120
121 /*
122 * Go get the pci bus vertex.
123 */
124 pci_bus = pci_bus_to_vertex(busnum);
125 if (!pci_bus) {
126 /*
127 * During probing, the Linux pci code invents non-existent
128 * bus numbers and pci_dev structures and tries to access
129 * them to determine existence. Don't crib during probing.
130 */
131 if (done_probing)
132 printk("devfn_to_vertex: Invalid bus number %d given.\n", busnum);
133 return(NULL);
134 }
135
136
137 /*
138 * Go get the slot&function vertex.
139 * Should call pciio_slot_func_to_name() when ready.
140 */
141 slot = PCI_SLOT(devfn);
142 func = PCI_FUNC(devfn);
143
144 /*
145 * For a NON Multi-function card the name of the device looks like:
146 * ../pci/1, ../pci/2 ..
147 */
148 if (func == 0) {
149 sprintf(name, "%d", slot);
150 if (hwgraph_traverse(pci_bus, name, &device_vertex) == GRAPH_SUCCESS) {
151 if (device_vertex) {
152 return(device_vertex);
153 }
154 }
155 }
156
157 /*
158 * This maybe a multifunction card. It's names look like:
159 * ../pci/1a, ../pci/1b, etc.
160 */
161 sprintf(name, "%d%c", slot, 'a'+func);
162 if (hwgraph_traverse(pci_bus, name, &device_vertex) != GRAPH_SUCCESS) {
163 if (!device_vertex) {
164 return(NULL);
165 }
166 }
167
168 return(device_vertex);
169 }
170
171 struct sn_flush_nasid_entry flush_nasid_list[MAX_NASIDS];
172
173 // Initialize the data structures for flushing write buffers after a PIO read.
174 // The theory is:
175 // Take an unused int. pin and associate it with a pin that is in use.
176 // After a PIO read, force an interrupt on the unused pin, forcing a write buffer flush
177 // on the in use pin. This will prevent the race condition between PIO read responses and
178 // DMA writes.
179 void
sn_dma_flush_init(unsigned long start,unsigned long end,int idx,int pin,int slot)180 sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int slot) {
181 nasid_t nasid;
182 unsigned long dnasid;
183 int wid_num;
184 int bus;
185 struct sn_flush_device_list *p;
186 bridge_t *b;
187 bridgereg_t dev_sel;
188 extern int isIO9(int);
189 int bwin;
190 int i;
191
192 nasid = NASID_GET(start);
193 wid_num = SWIN_WIDGETNUM(start);
194 bus = (start >> 23) & 0x1;
195 bwin = BWIN_WINDOWNUM(start);
196
197 if (flush_nasid_list[nasid].widget_p == NULL) {
198 flush_nasid_list[nasid].widget_p = (struct sn_flush_device_list **)kmalloc((HUB_WIDGET_ID_MAX+1) *
199 sizeof(struct sn_flush_device_list *), GFP_KERNEL);
200 if (flush_nasid_list[nasid].widget_p <= 0)
201 BUG(); /* Cannot afford to run out of memory. */
202
203 memset(flush_nasid_list[nasid].widget_p, 0, (HUB_WIDGET_ID_MAX+1) * sizeof(struct sn_flush_device_list *));
204 }
205 if (bwin > 0) {
206 bwin--;
207 switch (bwin) {
208 case 0:
209 flush_nasid_list[nasid].iio_itte1 = HUB_L(IIO_ITTE_GET(nasid, 0));
210 wid_num = ((flush_nasid_list[nasid].iio_itte1) >> 8) & 0xf;
211 bus = flush_nasid_list[nasid].iio_itte1 & 0xf;
212 if (bus == 0x4 || bus == 0x8)
213 bus = 0;
214 else
215 bus = 1;
216 break;
217 case 1:
218 flush_nasid_list[nasid].iio_itte2 = HUB_L(IIO_ITTE_GET(nasid, 1));
219 wid_num = ((flush_nasid_list[nasid].iio_itte2) >> 8) & 0xf;
220 bus = flush_nasid_list[nasid].iio_itte2 & 0xf;
221 if (bus == 0x4 || bus == 0x8)
222 bus = 0;
223 else
224 bus = 1;
225 break;
226 case 2:
227 flush_nasid_list[nasid].iio_itte3 = HUB_L(IIO_ITTE_GET(nasid, 2));
228 wid_num = ((flush_nasid_list[nasid].iio_itte3) >> 8) & 0xf;
229 bus = flush_nasid_list[nasid].iio_itte3 & 0xf;
230 if (bus == 0x4 || bus == 0x8)
231 bus = 0;
232 else
233 bus = 1;
234 break;
235 case 3:
236 flush_nasid_list[nasid].iio_itte4 = HUB_L(IIO_ITTE_GET(nasid, 3));
237 wid_num = ((flush_nasid_list[nasid].iio_itte4) >> 8) & 0xf;
238 bus = flush_nasid_list[nasid].iio_itte4 & 0xf;
239 if (bus == 0x4 || bus == 0x8)
240 bus = 0;
241 else
242 bus = 1;
243 break;
244 case 4:
245 flush_nasid_list[nasid].iio_itte5 = HUB_L(IIO_ITTE_GET(nasid, 4));
246 wid_num = ((flush_nasid_list[nasid].iio_itte5) >> 8) & 0xf;
247 bus = flush_nasid_list[nasid].iio_itte5 & 0xf;
248 if (bus == 0x4 || bus == 0x8)
249 bus = 0;
250 else
251 bus = 1;
252 break;
253 case 5:
254 flush_nasid_list[nasid].iio_itte6 = HUB_L(IIO_ITTE_GET(nasid, 5));
255 wid_num = ((flush_nasid_list[nasid].iio_itte6) >> 8) & 0xf;
256 bus = flush_nasid_list[nasid].iio_itte6 & 0xf;
257 if (bus == 0x4 || bus == 0x8)
258 bus = 0;
259 else
260 bus = 1;
261 break;
262 case 6:
263 flush_nasid_list[nasid].iio_itte7 = HUB_L(IIO_ITTE_GET(nasid, 6));
264 wid_num = ((flush_nasid_list[nasid].iio_itte7) >> 8) & 0xf;
265 bus = flush_nasid_list[nasid].iio_itte7 & 0xf;
266 if (bus == 0x4 || bus == 0x8)
267 bus = 0;
268 else
269 bus = 1;
270 break;
271 }
272 }
273
274 // if it's IO9, bus 1, we don't care about slots 1, 3, and 4. This is
275 // because these are the IOC4 slots and we don't flush them.
276 if (isIO9(nasid) && bus == 0 && (slot == 1 || slot == 4)) {
277 return;
278 }
279 if (flush_nasid_list[nasid].widget_p[wid_num] == NULL) {
280 flush_nasid_list[nasid].widget_p[wid_num] = (struct sn_flush_device_list *)kmalloc(
281 DEV_PER_WIDGET * sizeof (struct sn_flush_device_list), GFP_KERNEL);
282 if (flush_nasid_list[nasid].widget_p[wid_num] <= 0)
283 BUG(); /* Cannot afford to run out of memory. */
284
285 memset(flush_nasid_list[nasid].widget_p[wid_num], 0,
286 DEV_PER_WIDGET * sizeof (struct sn_flush_device_list));
287 p = &flush_nasid_list[nasid].widget_p[wid_num][0];
288 for (i=0; i<DEV_PER_WIDGET;i++) {
289 p->bus = -1;
290 p->pin = -1;
291 p++;
292 }
293 }
294
295 p = &flush_nasid_list[nasid].widget_p[wid_num][0];
296 for (i=0;i<DEV_PER_WIDGET; i++) {
297 if (p->pin == pin && p->bus == bus) break;
298 if (p->pin < 0) {
299 p->pin = pin;
300 p->bus = bus;
301 break;
302 }
303 p++;
304 }
305
306 for (i=0; i<PCI_ROM_RESOURCE; i++) {
307 if (p->bar_list[i].start == 0) {
308 p->bar_list[i].start = start;
309 p->bar_list[i].end = end;
310 break;
311 }
312 }
313 b = (bridge_t *)(NODE_SWIN_BASE(nasid, wid_num) | (bus << 23) );
314
315 // If it's IO9, then slot 2 maps to slot 7 and slot 6 maps to slot 8.
316 // To see this is non-trivial. By drawing pictures and reading manuals and talking
317 // to HW guys, we can see that on IO9 bus 1, slots 7 and 8 are always unused.
318 // Further, since we short-circuit slots 1, 3, and 4 above, we only have to worry
319 // about the case when there is a card in slot 2. A multifunction card will appear
320 // to be in slot 6 (from an interrupt point of view) also. That's the most we'll
321 // have to worry about. A four function card will overload the interrupt lines in
322 // slot 2 and 6.
323 // We also need to special case the 12160 device in slot 3. Fortunately, we have
324 // a spare intr. line for pin 4, so we'll use that for the 12160.
325 // All other buses have slot 3 and 4 and slots 7 and 8 unused. Since we can only
326 // see slots 1 and 2 and slots 5 and 6 coming through here for those buses (this
327 // is true only on Pxbricks with 2 physical slots per bus), we just need to add
328 // 2 to the slot number to find an unused slot.
329 // We have convinced ourselves that we will never see a case where two different cards
330 // in two different slots will ever share an interrupt line, so there is no need to
331 // special case this.
332
333 if (isIO9(nasid) && wid_num == 0xc && bus == 0) {
334 if (slot == 2) {
335 p->force_int_addr = (unsigned long)&b->b_force_always[6].intr;
336 dev_sel = b->b_int_device;
337 dev_sel |= (1<<18);
338 b->b_int_device = dev_sel;
339 dnasid = NASID_GET(virt_to_phys(&p->flush_addr));
340 b->p_int_addr_64[6] = (virt_to_phys(&p->flush_addr) & 0xfffffffff) |
341 (dnasid << 36) | (0xfUL << 48);
342 } else if (slot == 3) { /* 12160 SCSI device in IO9 */
343 p->force_int_addr = (unsigned long)&b->b_force_always[4].intr;
344 dev_sel = b->b_int_device;
345 dev_sel |= (2<<12);
346 b->b_int_device = dev_sel;
347 dnasid = NASID_GET(virt_to_phys(&p->flush_addr));
348 b->p_int_addr_64[4] = (virt_to_phys(&p->flush_addr) & 0xfffffffff) |
349 (dnasid << 36) | (0xfUL << 48);
350 } else { /* slot == 6 */
351 p->force_int_addr = (unsigned long)&b->b_force_always[7].intr;
352 dev_sel = b->b_int_device;
353 dev_sel |= (5<<21);
354 b->b_int_device = dev_sel;
355 dnasid = NASID_GET(virt_to_phys(&p->flush_addr));
356 b->p_int_addr_64[7] = (virt_to_phys(&p->flush_addr) & 0xfffffffff) |
357 (dnasid << 36) | (0xfUL << 48);
358 }
359 } else {
360 p->force_int_addr = (unsigned long)&b->b_force_always[pin + 2].intr;
361 dev_sel = b->b_int_device;
362 dev_sel |= ((slot - 1) << ( pin * 3) );
363 b->b_int_device = dev_sel;
364 dnasid = NASID_GET(virt_to_phys(&p->flush_addr));
365 b->p_int_addr_64[pin + 2] = (virt_to_phys(&p->flush_addr) & 0xfffffffff) |
366 (dnasid << 36) | (0xfUL << 48);
367 }
368 }
369
370 /*
371 * Most drivers currently do not properly tell the arch specific pci dma
372 * interfaces whether they can handle A64. Here is where we privately
373 * keep track of this.
374 */
375 static void __init
set_sn_pci64(struct pci_dev * dev)376 set_sn_pci64(struct pci_dev *dev)
377 {
378 unsigned short vendor = dev->vendor;
379 unsigned short device = dev->device;
380
381 if (vendor == PCI_VENDOR_ID_QLOGIC) {
382 if ((device == PCI_DEVICE_ID_QLOGIC_ISP2100) ||
383 (device == PCI_DEVICE_ID_QLOGIC_ISP2200)) {
384 SET_PCIA64(dev);
385 return;
386 }
387 }
388
389 }
390
391 /*
392 * sn_pci_fixup() - This routine is called when platform_pci_fixup() is
393 * invoked at the end of pcibios_init() to link the Linux pci
394 * infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c
395 *
396 * Other platform specific fixup can also be done here.
397 */
398 void
sn_pci_fixup(int arg)399 sn_pci_fixup(int arg)
400 {
401 struct list_head *ln;
402 struct pci_bus *pci_bus = NULL;
403 struct pci_dev *device_dev = NULL;
404 struct sn_widget_sysdata *widget_sysdata;
405 struct sn_device_sysdata *device_sysdata;
406 pciio_intr_t intr_handle;
407 int cpuid;
408 vertex_hdl_t device_vertex;
409 pciio_intr_line_t lines;
410 extern void sn_pci_find_bios(void);
411 extern int numnodes;
412 int cnode;
413
414 if (arg == 0) {
415 #ifdef CONFIG_PROC_FS
416 extern void register_sn_procfs(void);
417 #endif
418
419 sn_pci_find_bios();
420 for (cnode = 0; cnode < numnodes; cnode++) {
421 extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
422 intr_init_vecblk(NODEPDA(cnode), cnode, 0);
423 }
424 #ifdef CONFIG_PROC_FS
425 register_sn_procfs();
426 #endif
427 return;
428 }
429
430
431 done_probing = 1;
432
433 /*
434 * Initialize the pci bus vertex in the pci_bus struct.
435 */
436 for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
437 pci_bus = pci_bus_b(ln);
438 widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata),
439 GFP_KERNEL);
440 if (widget_sysdata <= 0)
441 BUG(); /* Cannot afford to run out of memory */
442
443 widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number);
444 pci_bus->sysdata = (void *)widget_sysdata;
445 }
446
447 /*
448 * set the root start and end so that drivers calling check_region()
449 * won't see a conflict
450 */
451 ioport_resource.start = 0xc000000000000000;
452 ioport_resource.end = 0xcfffffffffffffff;
453
454 /*
455 * Set the root start and end for Mem Resource.
456 */
457 iomem_resource.start = 0;
458 iomem_resource.end = 0xffffffffffffffff;
459
460 /*
461 * Initialize the device vertex in the pci_dev struct.
462 */
463 pci_for_each_dev(device_dev) {
464 unsigned int irq;
465 int idx;
466 u16 cmd;
467 vertex_hdl_t vhdl;
468 unsigned long size;
469 extern int bit_pos_to_irq(int);
470
471 /* Set the device vertex */
472
473 device_sysdata = kmalloc(sizeof(struct sn_device_sysdata),
474 GFP_KERNEL);
475 if (device_sysdata <= 0)
476 BUG(); /* Cannot afford to run out of memory */
477
478 device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
479 device_sysdata->isa64 = 0;
480 device_dev->sysdata = (void *) device_sysdata;
481 set_sn_pci64(device_dev);
482 set_isPIC(device_sysdata);
483
484 pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
485
486 /*
487 * Set the resources address correctly. The assumption here
488 * is that the addresses in the resource structure has been
489 * read from the card and it was set in the card by our
490 * Infrastructure ..
491 */
492 vhdl = device_sysdata->vhdl;
493 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
494 size = 0;
495 size = device_dev->resource[idx].end -
496 device_dev->resource[idx].start;
497 if (size) {
498 device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, 0);
499 device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
500 }
501 else
502 continue;
503
504 device_dev->resource[idx].end =
505 device_dev->resource[idx].start + size;
506
507 if (device_dev->resource[idx].flags & IORESOURCE_IO)
508 cmd |= PCI_COMMAND_IO;
509
510 if (device_dev->resource[idx].flags & IORESOURCE_MEM)
511 cmd |= PCI_COMMAND_MEMORY;
512 }
513 #if 0
514 /*
515 * Software WAR for a Software BUG.
516 * This is only temporary.
517 * See PV 872791
518 */
519
520 /*
521 * Now handle the ROM resource ..
522 */
523 size = device_dev->resource[PCI_ROM_RESOURCE].end -
524 device_dev->resource[PCI_ROM_RESOURCE].start;
525
526 if (size) {
527 device_dev->resource[PCI_ROM_RESOURCE].start =
528 (unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0,
529 size, 0, 0);
530 device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET;
531 device_dev->resource[PCI_ROM_RESOURCE].end =
532 device_dev->resource[PCI_ROM_RESOURCE].start + size;
533 }
534 #endif
535
536 /*
537 * Update the Command Word on the Card.
538 */
539 cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
540 /* bit gets dropped .. no harm */
541 pci_write_config_word(device_dev, PCI_COMMAND, cmd);
542
543 pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
544 device_sysdata = (struct sn_device_sysdata *)device_dev->sysdata;
545 device_vertex = device_sysdata->vhdl;
546
547 irqpdaindr->current = device_dev;
548 intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex);
549
550 irq = intr_handle->pi_irq;
551 irqpdaindr->device_dev[irq] = device_dev;
552 cpuid = intr_handle->pi_cpu;
553 pciio_intr_connect(intr_handle, (intr_func_t)0, (intr_arg_t)0);
554 device_dev->irq = irq;
555 register_pcibr_intr(irq, (pcibr_intr_t)intr_handle);
556
557 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
558 int ibits = ((pcibr_intr_t)intr_handle)->bi_ibits;
559 int i;
560
561 size = device_dev->resource[idx].end -
562 device_dev->resource[idx].start;
563 if (size == 0) continue;
564
565 for (i=0; i<8; i++) {
566 if (ibits & (1 << i) ) {
567 sn_dma_flush_init(device_dev->resource[idx].start,
568 device_dev->resource[idx].end,
569 idx,
570 i,
571 PCI_SLOT(device_dev->devfn));
572 }
573 }
574 }
575
576 }
577 #ifdef ajmtestintr
578 {
579 int slot = PCI_SLOT(device_dev->devfn);
580 static int timer_set = 0;
581 pcibr_intr_t pcibr_intr = (pcibr_intr_t)intr_handle;
582 pcibr_soft_t pcibr_soft = pcibr_intr->bi_soft;
583 extern void intr_test_handle_intr(int, void*, struct pt_regs *);
584
585 if (!timer_set) {
586 intr_test_set_timer();
587 timer_set = 1;
588 }
589 intr_test_register_irq(irq, pcibr_soft, slot);
590 request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
591 }
592 #endif
593 }
594
595 /*
596 * linux_bus_cvlink() Creates a link between the Linux PCI Bus number
597 * to the actual hardware component that it represents:
598 * /dev/hw/linux/busnum/0 -> ../../../hw/module/001c01/slab/0/Ibrick/xtalk/15/pci
599 *
600 * The bus vertex, when called to devfs_generate_path() returns:
601 * hw/module/001c01/slab/0/Ibrick/xtalk/15/pci
602 * hw/module/001c01/slab/1/Pbrick/xtalk/12/pci-x/0
603 * hw/module/001c01/slab/1/Pbrick/xtalk/12/pci-x/1
604 */
605 void
linux_bus_cvlink(void)606 linux_bus_cvlink(void)
607 {
608 char name[8];
609 int index;
610
611 for (index=0; index < MAX_PCI_XWIDGET; index++) {
612 if (!busnum_to_pcibr_vhdl[index])
613 continue;
614
615 sprintf(name, "%x", index);
616 (void) hwgraph_edge_add(linux_busnum, busnum_to_pcibr_vhdl[index],
617 name);
618 }
619 }
620
621 /*
622 * pci_bus_map_create() - Called by pci_bus_to_hcl_cvlink() to finish the job.
623 *
624 * Linux PCI Bus numbers are assigned from lowest module_id numbers
625 * (rack/slot etc.) starting from HUB_WIDGET_ID_MAX down to
626 * HUB_WIDGET_ID_MIN:
627 * widgetnum 15 gets lower Bus Number than widgetnum 14 etc.
628 *
629 * Given 2 modules 001c01 and 001c02 we get the following mappings:
630 * 001c01, widgetnum 15 = Bus number 0
631 * 001c01, widgetnum 14 = Bus number 1
632 * 001c02, widgetnum 15 = Bus number 3
633 * 001c02, widgetnum 14 = Bus number 4
634 * etc.
635 *
636 * The rational for starting Bus Number 0 with Widget number 15 is because
637 * the system boot disks are always connected via Widget 15 Slot 0 of the
638 * I-brick. Linux creates /dev/sd* devices(naming) strating from Bus Number 0
639 * Therefore, /dev/sda1 will be the first disk, on Widget 15 of the lowest
640 * module id(Master Cnode) of the system.
641 *
642 */
643 static int
pci_bus_map_create(vertex_hdl_t xtalk,int brick_type,char * io_moduleid)644 pci_bus_map_create(vertex_hdl_t xtalk, int brick_type, char * io_moduleid)
645 {
646
647 vertex_hdl_t xwidget = NULL;
648 vertex_hdl_t pci_bus = NULL;
649 xwidgetnum_t widgetnum;
650 char pathname[128];
651 graph_error_t rv;
652 int bus;
653 int basebus_num;
654 extern void ioconfig_get_busnum(char *, int *);
655
656 int bus_number;
657
658 /*
659 * PCIX devices
660 * We number busses differently for PCI-X devices.
661 * We start from Lowest Widget on up ..
662 */
663
664 (void) ioconfig_get_busnum((char *)io_moduleid, &basebus_num);
665
666 for (widgetnum = HUB_WIDGET_ID_MIN; widgetnum <= HUB_WIDGET_ID_MAX; widgetnum++) {
667
668 /* Do both buses */
669 for ( bus = 0; bus < 2; bus++ ) {
670 sprintf(pathname, "%d", widgetnum);
671 xwidget = NULL;
672
673 /*
674 * Example - /hw/module/001c16/Pbrick/xtalk/8 is the xwidget
675 * /hw/module/001c16/Pbrick/xtalk/8/pci-x/0 is the bus
676 * /hw/module/001c16/Pbrick/xtalk/8/pci-x/0/1 is device
677 */
678 rv = hwgraph_traverse(xtalk, pathname, &xwidget);
679 if ( (rv != GRAPH_SUCCESS) ) {
680 if (!xwidget) {
681 continue;
682 }
683 }
684
685 if ( bus == 0 )
686 sprintf(pathname, "%d/"EDGE_LBL_PCIX_0, widgetnum);
687 else
688 sprintf(pathname, "%d/"EDGE_LBL_PCIX_1, widgetnum);
689 pci_bus = NULL;
690 if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS)
691 if (!pci_bus) {
692 continue;
693 }
694
695 /*
696 * Assign the correct bus number and also the nasid of this
697 * pci Xwidget.
698 *
699 * Should not be any race here ...
700 */
701 bus_number = basebus_num + bus + io_brick_map_widget(brick_type, widgetnum);
702 #ifdef DEBUG
703 printk("bus_number %d basebus_num %d bus %d io %d pci_bus 0x%x brick_type %d \n",
704 bus_number, basebus_num, bus,
705 io_brick_map_widget(brick_type, widgetnum), pci_bus, brick_type);
706 #endif
707 busnum_to_pcibr_vhdl[bus_number] = pci_bus;
708
709 /*
710 * Pre assign DMA maps needed for 32 Bits Page Map DMA.
711 */
712 busnum_to_atedmamaps[bus_number] = (void *) kmalloc(
713 sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL);
714 if (busnum_to_atedmamaps[bus_number] <= 0)
715 BUG(); /* Cannot afford to run out of memory. */
716
717 memset(busnum_to_atedmamaps[bus_number], 0x0,
718 sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS);
719 }
720 }
721
722 /* AGP/CGbrick */
723
724 for (widgetnum = HUB_WIDGET_ID_MIN; widgetnum <= HUB_WIDGET_ID_MAX; widgetnum++) {
725
726 /* Do both buses */
727 for ( bus = 0; bus < 2; bus++ ) {
728 sprintf(pathname, "%d", widgetnum);
729 xwidget = NULL;
730
731 /*
732 * Example - /hw/module/001c16/slab/0/CGbrick/xtalk/15 is the xwidget
733 * /hw/module/001c16/slab/0/CGbrick/xtalk/15/agp/0 is the bus
734 * /hw/module/001c16/slab/0/CGbrick/xtalk/15/agp/0/1a is device
735 */
736 rv = hwgraph_traverse(xtalk, pathname, &xwidget);
737 if ( (rv != GRAPH_SUCCESS) ) {
738 if (!xwidget) {
739 continue;
740 }
741 }
742
743 if ( bus == 0 )
744 sprintf(pathname, "%d/"EDGE_LBL_AGP_0, widgetnum);
745 else
746 sprintf(pathname, "%d/"EDGE_LBL_AGP_1, widgetnum);
747 pci_bus = NULL;
748 if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS)
749 if (!pci_bus) {
750 continue;
751 }
752
753 /*
754 * Assign the correct bus number and also the nasid of this
755 * pci Xwidget.
756 *
757 * Should not be any race here ...
758 */
759 bus_number = basebus_num + bus + io_brick_map_widget(brick_type, widgetnum);
760 #ifdef DEBUG
761 printk("bus_number %d basebus_num %d bus %d io %d pci_bus 0x%x\n",
762 bus_number, basebus_num, bus,
763 io_brick_map_widget(brick_type, widgetnum), pci_bus);
764 #endif
765 busnum_to_pcibr_vhdl[bus_number] = pci_bus;
766
767 /*
768 * Pre assign DMA maps needed for 32 Bits Page Map DMA.
769 */
770 busnum_to_atedmamaps[bus_number] = (void *) kmalloc(
771 sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL);
772 if (busnum_to_atedmamaps[bus_number] <= 0)
773 BUG(); /* Cannot afford to run out of memory */
774
775 memset(busnum_to_atedmamaps[bus_number], 0x0,
776 sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS);
777 }
778 }
779 return(0);
780 }
781
782 /*
783 * pci_bus_to_hcl_cvlink() - This routine is called after SGI IO Infrastructure
784 * initialization has completed to set up the mappings between Xbridge
785 * and logical pci bus numbers. We also set up the NASID for each of these
786 * xbridges.
787 *
788 * Must be called before pci_init() is invoked.
789 */
790 int
pci_bus_to_hcl_cvlink(void)791 pci_bus_to_hcl_cvlink(void)
792 {
793
794 vertex_hdl_t devfs_hdl = NULL;
795 vertex_hdl_t xtalk = NULL;
796 int rv = 0;
797 char *name;
798 char *tmp_name;
799 int i, ii, j;
800 char *brick_name;
801 extern void ioconfig_bus_new_entries(void);
802 extern int iobrick_type_get_nasid(nasid_t);
803
804 name = kmalloc(256, GFP_KERNEL);
805 if (!name)
806 BUG();
807
808 tmp_name = kmalloc(256, GFP_KERNEL);
809 if (!name)
810 BUG();
811
812 /*
813 * Figure out which IO Brick is connected to the Compute Bricks.
814 */
815 for (i = 0; i < nummodules; i++) {
816 extern int iomoduleid_get(nasid_t);
817 moduleid_t iobrick_id;
818 nasid_t nasid = -1;
819 int n = 0;
820
821 for ( n = 0; n <= MAX_SLABS; n++ ) {
822 if (modules[i]->nodes[n] == -1)
823 continue; /* node is not alive in module */
824
825 nasid = cnodeid_to_nasid(modules[i]->nodes[n]);
826 iobrick_id = iomoduleid_get(nasid);
827 if ((int)iobrick_id > 0) { /* Valid module id */
828 char name[12];
829 memset(name, 0, 12);
830 format_module_id((char *)&(modules[i]->io[n].moduleid), iobrick_id, MODULE_FORMAT_BRIEF);
831 modules[i]->io[n].iobrick_type = (uint64_t)iobrick_type_get_nasid(nasid);
832 }
833 }
834 }
835
836 devfs_hdl = hwgraph_path_to_vertex("hw/module");
837 for (i = 0; i < nummodules ; i++) {
838 for ( j = 0; j < 4; j++ ) {
839 if ( j == 0 )
840 brick_name = EDGE_LBL_IXBRICK;
841 else if ( j == 1 )
842 brick_name = EDGE_LBL_PXBRICK;
843 else if ( j == 2 )
844 brick_name = EDGE_LBL_OPUSBRICK;
845 else /* 3 */
846 brick_name = EDGE_LBL_CGBRICK;
847
848 for ( ii = 0; ii <= MAX_SLABS ; ii++ ) {
849 if (modules[i]->nodes[ii] == -1)
850 continue; /* Missing slab */
851
852 memset(name, 0, 256);
853 memset(tmp_name, 0, 256);
854 format_module_id(name, modules[i]->id, MODULE_FORMAT_BRIEF);
855 sprintf(tmp_name, "/slab/%d/%s/xtalk", geo_slab(modules[i]->geoid[ii]), brick_name);
856 strcat(name, tmp_name);
857 xtalk = NULL;
858 rv = hwgraph_edge_get(devfs_hdl, name, &xtalk);
859 if ( rv == 0 )
860 pci_bus_map_create(xtalk, (int)modules[i]->io[ii].iobrick_type, (char *)&(modules[i]->io[ii].moduleid));
861 }
862 }
863 }
864
865 kfree(name);
866 kfree(tmp_name);
867
868 /*
869 * Create the Linux PCI bus number vertex link.
870 */
871 (void)linux_bus_cvlink();
872 (void)ioconfig_bus_new_entries();
873
874 return(0);
875 }
876