Lines Matching refs:bridgereg_t
95 typedef uint32_t bridgereg_t; typedef
121 bridgereg_t _b_wid_id; /* 0x000004 */
122 bridgereg_t _pad_000000;
127 bridgereg_t _b_wid_stat; /* 0x00000C */
128 bridgereg_t _b_pad_000008;
134 bridgereg_t _b_wid_err_upper; /* 0x000014 */
135 bridgereg_t _pad_000010;
140 bridgereg_t _b_wid_err_lower; /* 0x00001C */
141 bridgereg_t _b_pad_000018;
150 bridgereg_t _b_wid_control; /* 0x000024 */
151 bridgereg_t _b_pad_000020;
157 bridgereg_t _b_wid_req_timeout; /* 0x00002C */
158 bridgereg_t _pad_000028;
160 bridgereg_t _b_wid_int_upper; /* 0x000034 */
161 bridgereg_t _pad_000030;
166 bridgereg_t _b_wid_int_lower; /* 0x00003C */
167 bridgereg_t _b_pad_000038;
173 bridgereg_t _b_wid_err_cmdword; /* 0x000044 */
174 bridgereg_t _pad_000040;
176 bridgereg_t _b_wid_llp; /* 0x00004C */
177 bridgereg_t _pad_000048;
179 bridgereg_t _b_wid_tflush; /* 0x000054 */
180 bridgereg_t _pad_000050;
230 bridgereg_t b_wid_aux_err; /* 0x00005C */
231 bridgereg_t _pad_000058;
233 bridgereg_t b_wid_resp_upper; /* 0x000064 */
234 bridgereg_t _pad_000060;
239 bridgereg_t _b_wid_resp_lower; /* 0x00006C */
240 bridgereg_t _b_pad_000068;
246 bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
247 bridgereg_t _pad_000070;
252 bridgereg_t _b_pad_00007C;
253 bridgereg_t _b_pad_000078;
259 bridgereg_t b_dir_map; /* 0x000084 */
260 bridgereg_t _pad_000080;
262 bridgereg_t _pad_00008C;
263 bridgereg_t _pad_000088;
266 bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */
267 bridgereg_t _pad_000090;
271 bridgereg_t _pad_00009C;
272 bridgereg_t _pad_000098;
275 bridgereg_t b_arb; /* 0x0000A4 */
276 bridgereg_t _pad_0000A0;
278 bridgereg_t _pad_0000AC;
279 bridgereg_t _pad_0000A8;
285 bridgereg_t _b_nic; /* 0x0000B4 */
286 bridgereg_t _b_pad_0000B0;
292 bridgereg_t _pad_0000BC;
293 bridgereg_t _pad_0000B8;
296 bridgereg_t b_bus_timeout; /* 0x0000C4 */
297 bridgereg_t _pad_0000C0;
300 bridgereg_t b_pci_cfg; /* 0x0000CC */
301 bridgereg_t _pad_0000C8;
303 bridgereg_t b_pci_err_upper; /* 0x0000D4 */
304 bridgereg_t _pad_0000D0;
310 bridgereg_t _b_pci_err_lower; /* 0x0000DC */
311 bridgereg_t _b_pad_0000D8;
318 bridgereg_t _pad_0000E0[8];
324 bridgereg_t _b_int_status; /* 0x000104 */
325 bridgereg_t _b_pad_000100;
334 bridgereg_t _b_int_enable; /* 0x00010C */
335 bridgereg_t _b_pad_000108;
344 bridgereg_t _b_int_rst_stat; /* 0x000114 */
345 bridgereg_t _b_pad_000110;
351 bridgereg_t b_int_mode; /* 0x00011C */
352 bridgereg_t _pad_000118;
354 bridgereg_t b_int_device; /* 0x000124 */
355 bridgereg_t _pad_000120;
357 bridgereg_t b_int_host_err; /* 0x00012C */
358 bridgereg_t _pad_000128;
363 bridgereg_t addr; /* 0x0001{34,,,6C} */
364 bridgereg_t _b_pad;
373 bridgereg_t _b_err_int_view; /* 0x000174 */
374 bridgereg_t _b_pad_000170;
383 bridgereg_t _b_mult_int; /* 0x00017C */
384 bridgereg_t _b_pad_000178;
391 bridgereg_t intr; /* 0x0001{84,,,BC} */
392 bridgereg_t __pad;
396 bridgereg_t intr; /* 0x0001{C4,,,FC} */
397 bridgereg_t __pad;
402 bridgereg_t reg; /* 0x0002{04,,,3C} */
403 bridgereg_t __pad;
407 bridgereg_t reg; /* 0x0002{44,,,7C} */
408 bridgereg_t __pad;
412 bridgereg_t reg; /* 0x0002{84,,,8C} */
413 bridgereg_t __pad;
418 bridgereg_t b_resp_status; /* 0x000294 */
419 bridgereg_t _pad_000290;
421 bridgereg_t b_resp_clear; /* 0x00029C */
422 bridgereg_t _pad_000298;
424 bridgereg_t _pad_0002A0[24];
433 bridgereg_t upper; /* 0x0003{04,,,F4} */
434 bridgereg_t _b_pad1;
435 bridgereg_t lower; /* 0x0003{0C,,,FC} */
436 bridgereg_t _b_pad2;
444 bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */
445 bridgereg_t __pad1;
446 bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */
447 bridgereg_t __pad2;
448 bridgereg_t inflight; /* 0x000{414,,,5D4} */
449 bridgereg_t __pad3;
450 bridgereg_t prefetch; /* 0x000{41C,,,5DC} */
451 bridgereg_t __pad4;
452 bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */
453 bridgereg_t __pad5;
454 bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */
455 bridgereg_t __pad6;
456 bridgereg_t max_latency; /* 0x000{434,,,5F4} */
457 bridgereg_t __pad7;
458 bridgereg_t clear_all; /* 0x000{43C,,,5FC} */
459 bridgereg_t __pad8;
511 bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */
512 bridgereg_t _p_pad;
519 bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */
520 bridgereg_t _p_pad;