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Searched refs:KSEG1ADDR (Results 1 – 25 of 105) sorted by relevance

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/linux-2.4.37.9/include/asm-mips/vr41xx/
Deagle.h60 #define IO_PORT_BASE KSEG1ADDR(VR41XX_PCI_IO_BASE)
106 #define NEC_EAGLE_SIO1RB KSEG1ADDR(0x0DFFFEC0)
107 #define NEC_EAGLE_SIO1TH KSEG1ADDR(0x0DFFFEC0)
108 #define NEC_EAGLE_SIO1IE KSEG1ADDR(0x0DFFFEC2)
109 #define NEC_EAGLE_SIO1IID KSEG1ADDR(0x0DFFFEC4)
110 #define NEC_EAGLE_SIO1FC KSEG1ADDR(0x0DFFFEC4)
111 #define NEC_EAGLE_SIO1LC KSEG1ADDR(0x0DFFFEC6)
112 #define NEC_EAGLE_SIO1MC KSEG1ADDR(0x0DFFFEC8)
113 #define NEC_EAGLE_SIO1LS KSEG1ADDR(0x0DFFFECA)
114 #define NEC_EAGLE_SIO1MS KSEG1ADDR(0x0DFFFECC)
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Dtb0229.h47 #define IO_PORT_BASE KSEG1ADDR(VR41XX_PCI_IO_BASE)
69 #define TB0219_RESET_REGS KSEG1ADDR(0x0a00000e)
/linux-2.4.37.9/arch/mips/vr41xx/common/
Dpciu.h26 #define PCIMMAW1REG KSEG1ADDR(0x0f000c00)
27 #define PCIMMAW2REG KSEG1ADDR(0x0f000c04)
28 #define PCITAW1REG KSEG1ADDR(0x0f000c08)
29 #define PCITAW2REG KSEG1ADDR(0x0f000c0c)
30 #define PCIMIOAWREG KSEG1ADDR(0x0f000c10)
36 #define PCICONFDREG KSEG1ADDR(0x0f000c14)
37 #define PCICONFAREG KSEG1ADDR(0x0f000c18)
38 #define PCIMAILREG KSEG1ADDR(0x0f000c1c)
40 #define BUSERRADREG KSEG1ADDR(0x0f000c24)
43 #define INTCNTSTAREG KSEG1ADDR(0x0f000c28)
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Dserial.c52 #define SIURB_TYPE1 KSEG1ADDR(0x0c000000)
53 #define SIUIRSEL_TYPE1 KSEG1ADDR(0x0c000008)
56 #define SIURB_TYPE2 KSEG1ADDR(0x0f000800)
57 #define SIUIRSEL_TYPE2 KSEG1ADDR(0x0f000808)
72 #define DSIURB KSEG1ADDR(0x0f000820)
74 #define MDSIUINTREG KSEG1ADDR(0x0f000096)
/linux-2.4.37.9/include/asm-mips64/mips-boards/
Dgeneric.h32 #define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0))
34 #define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
35 #define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
42 #define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
49 #define SOFTRES_REG (KSEG1ADDR(0x1e800050))
52 #define SOFTRES_REG (KSEG1ADDR(0x1f000500))
59 #define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010))
Datlas.h33 #define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
34 #define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
40 #define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
51 #define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
60 #define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
Dmalta.h31 #define MALTA_BONITO_PORT_BASE (KSEG1ADDR(0x1fd00000))
38 return KSEG1ADDR((addr & 0xffff) << 21); in get_gt_port_base()
45 return KSEG1ADDR(addr); in get_msc_port_base()
71 #define MALTA_JMPRS_REG (KSEG1ADDR(0x1f000210))
/linux-2.4.37.9/include/asm-mips/mips-boards/
Dgeneric.h32 #define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0))
34 #define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
35 #define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
42 #define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
49 #define SOFTRES_REG (KSEG1ADDR(0x1e800050))
52 #define SOFTRES_REG (KSEG1ADDR(0x1f000500))
59 #define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010))
Datlas.h33 #define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
34 #define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
40 #define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
51 #define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
60 #define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
Dmalta.h31 #define MALTA_BONITO_PORT_BASE (KSEG1ADDR(0x1fd00000))
38 return KSEG1ADDR((addr & 0xffff) << 21); in get_gt_port_base()
45 return KSEG1ADDR(addr); in get_msc_port_base()
71 #define MALTA_JMPRS_REG (KSEG1ADDR(0x1f000210))
/linux-2.4.37.9/include/asm-mips/dec/
Dkn02xa.h23 #define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000)
35 #define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */
36 #define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */
41 #define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */
42 #define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */
43 #define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */
44 #define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */
/linux-2.4.37.9/include/asm-mips64/dec/
Dkn02xa.h23 #define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000)
35 #define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */
36 #define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */
41 #define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */
42 #define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */
43 #define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */
44 #define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */
/linux-2.4.37.9/include/asm-mips/lasat/
Dlasatint.h4 #define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
5 #define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
9 #define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
10 #define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
Dpicvue.h2 #define PVC_REG_100 KSEG1ADDR(0x1c820000)
10 #define PVC_REG_200 KSEG1ADDR(0x11000000)
Deeprom.h4 #define AT93C_REG_100 KSEG1ADDR(0x1c810000)
12 #define AT93C_REG_200 KSEG1ADDR(0x11000000)
Dds1603.h4 #define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
11 #define DS1603_REG_200 (KSEG1ADDR(0x11000000))
/linux-2.4.37.9/arch/mips/lasat/
Dsetup.c77 {(void *)KSEG1ADDR(0x1c840000), (void *)KSEG1ADDR(0x1c800000), 2},
78 {(void *)KSEG1ADDR(0x11080000), (void *)KSEG1ADDR(0x11000000), 6}
173 s.iomem_base = (u8 *)KSEG1ADDR(LASAT_UART_REGS_BASE_100); in serial_init()
178 s.iomem_base = (u8 *)KSEG1ADDR(LASAT_UART_REGS_BASE_200); in serial_init()
/linux-2.4.37.9/include/asm-mips/gt64120/ev64120/
Dev64120.h37 #define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
42 #define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
43 #define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
/linux-2.4.37.9/include/asm-mips64/gt64120/ev64120/
Dev64120.h37 #define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
42 #define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
43 #define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
/linux-2.4.37.9/include/asm-mips/it8172/
Dit8172.h339 #define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
340 #define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
342 #define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
343 #define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
345 #define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
346 #define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
/linux-2.4.37.9/drivers/video/
Dmaxinefb.h16 #define MAXINEFB_IMS332_ADDRESS KSEG1ADDR(0x1c140000)
22 #define DS5000_xx_ONBOARD_FBMEM_START KSEG1ADDR(0x0a000000)
/linux-2.4.37.9/drivers/net/
Dsb1250-mac.c692 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
694 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
696 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
698 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
700 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
702 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
704 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
706 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
708 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
710 SBMAC_WRITECSR(KSEG1ADDR( in sbdma_initctx()
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/linux-2.4.37.9/arch/mips/ddb5xxx/ddb5074/
Dtime.c16 return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr); in ddb_rtc_read_data()
21 *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr)=data; in ddb_rtc_write_data()
/linux-2.4.37.9/include/asm-mips/gt64120/ev96100/
Dgt64120_dep.h14 #define GT64120_BASE (KSEG1ADDR(0x14000000))
37 #define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/linux-2.4.37.9/include/asm-mips64/gt64120/ev96100/
Dgt64120_dep.h14 #define GT64120_BASE (KSEG1ADDR(0x14000000))
37 #define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))

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