1 /* 2 * This is a direct copy of the ev96100.h file, with a global 3 * search and replace. The numbers are the same. 4 * 5 * The reason I'm duplicating this is so that the 64120/96100 6 * defines won't be confusing in the source code. 7 */ 8 #ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H 9 #define __ASM_GALILEO_BOARDS_MIPS_EV64120_H 10 11 /* 12 * GT64120 config space base address 13 */ 14 extern unsigned long gt64120_base; 15 16 #define GT64120_BASE (gt64120_base) 17 18 /* 19 * PCI Bus allocation 20 */ 21 #define GT_PCI_MEM_BASE 0x12000000UL 22 #define GT_PCI_MEM_SIZE 0x02000000UL 23 #define GT_PCI_IO_BASE 0x10000000UL 24 #define GT_PCI_IO_SIZE 0x02000000UL 25 #define GT_ISA_IO_BASE PCI_IO_BASE 26 27 /* 28 * Duart I/O ports. 29 */ 30 #define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20) 31 #define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00) 32 33 34 /* 35 * EV64120 interrupt controller register base. 36 */ 37 #define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) 38 39 /* 40 * EV64120 UART register base. 41 */ 42 #define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) 43 #define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) 44 #define EV64120_BASE_BAUD ( 3686400 / 16 ) 45 46 /* 47 * PCI interrupts will come in on either the INTA or INTD interrups lines, 48 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our 49 * boards, they all either come in on IntD or they all come in on IntA, they 50 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the 51 * "requested" interrupt numbers and go through the list whenever we get an 52 * IntA/D. 53 * 54 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and 55 * INTD is 11. 56 */ 57 #define GT_TIMER 4 58 #define GT_INTA 2 59 #define GT_INTD 5 60 61 #endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */ 62