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Searched refs:IO_ADDRESS (Results 1 – 25 of 29) sorted by relevance

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/linux-2.4.37.9/arch/arm/mach-integrator/
Dmm.c56 { IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K , DOMAIN_IO, 0, 1},
57 { IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K , DOMAIN_IO, 0, 1},
58 { IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K , DOMAIN_IO, 0, 1},
59 { IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K , DOMAIN_IO, 0, 1},
60 { IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K , DOMAIN_IO, 0, 1},
61 { IO_ADDRESS(INTEGRATOR_RTC_BASE), INTEGRATOR_RTC_BASE, SZ_4K , DOMAIN_IO, 0, 1},
62 { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K , DOMAIN_IO, 0, 1},
63 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K , DOMAIN_IO, 0, 1},
64 { IO_ADDRESS(INTEGRATOR_KBD_BASE), INTEGRATOR_KBD_BASE, SZ_4K , DOMAIN_IO, 0, 1},
65 { IO_ADDRESS(INTEGRATOR_MOUSE_BASE), INTEGRATOR_MOUSE_BASE, SZ_4K , DOMAIN_IO, 0, 1},
[all …]
Dtime.c17 #define RTC_DR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 0)
18 #define RTC_MR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 4)
19 #define RTC_STAT (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 8)
20 #define RTC_EOI (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 8)
21 #define RTC_LR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 12)
22 #define RTC_CR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 16)
Dcpu.c23 #define CM_ID (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_ID_OFFSET)
24 #define CM_OSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_OSC_OFFSET)
25 #define CM_STAT (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_STAT_OFFSET)
26 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
Darch.c39 .base = IO_ADDRESS(KMI0_BASE),
46 .base = IO_ADDRESS(KMI1_BASE),
Dirq.c38 #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
39 #define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
Dleds.c37 const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE); in integrator_leds_event()
38 const unsigned int hdr_ctrl = IO_ADDRESS(INTEGRATOR_HDR_BASE) + in integrator_leds_event()
Dpci_v3.c446 #define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET)
447 #define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20)
448 #define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24)
/linux-2.4.37.9/include/asm-arm/arch-epxa/
Dtime.h35 *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))|=TIMER0_CR_CI_MSK; in excalibur_timer_interrupt()
60 *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=0; in setup_timer()
61 *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200); in setup_timer()
62 *TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1; in setup_timer()
63 *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK; in setup_timer()
Dhardware.h36 #define IO_ADDRESS(x) ((x) | 0xf0000000) macro
/linux-2.4.37.9/arch/arm/mach-epxa/
Dirq.c35 __raw_writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE))); in mask_irq()
40 __raw_writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE))); in unmask_irq()
56 __raw_writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE))); in epxa_init_irq()
58 __raw_writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i)); in epxa_init_irq()
72 __raw_writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE))); in epxa_init_irq()
Dmm.c37 { IO_ADDRESS(EXC_REGISTERS_BASE), EXC_REGISTERS_BASE, SZ_4K , DOMAIN_IO, 0, 1}, LAST_DESC
/linux-2.4.37.9/include/asm-arm/arch-omaha/
Dtime.h40 p = (unsigned int *)(IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_TCNTB0)); in omaha_gettimeoffset()
68 p = (unsigned int *)(IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_SRCPND)); in omaha_timer_interrupt()
94 p = (unsigned int *)(IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_TCNTB0)); in setup_timer()
99 p = (unsigned int *)(IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_TCON)); in setup_timer()
106 p = (unsigned int *)(IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_TCON)); in setup_timer()
Dsystem.h38 volatile unsigned int wtcon = IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_WTCON); in arch_reset()
39 volatile unsigned int wtdat = IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_WTDAT); in arch_reset()
40 volatile unsigned int wtcnt = IO_ADDRESS(PLAT_PERIPHERAL_BASE+OMAHA_WTCNT); in arch_reset()
Dide.h60 ide_init_hwif_ports(&hw, IO_ADDRESS(0x01C00000), IO_ADDRESS(0x01C00006), NULL); in ide_init_default_hwifs()
Dhardware.h37 #define IO_ADDRESS(x) (x + IO_BASE) macro
/linux-2.4.37.9/include/asm-arm/arch-integrator/
Dtime.h24 #define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000)
25 #define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100)
26 #define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200)
27 #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
Dsystem.h39 unsigned int hdr_ctrl = (IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET); in arch_reset()
Dhardware.h49 #define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) macro
/linux-2.4.37.9/arch/arm/mach-mx1ads/
Dmm.c37 { IO_ADDRESS(MX1ADS_SRAM_BASE), MX1ADS_SRAM_BASE, SZ_128K , DOMAIN_IO, 0, 1},
38 { IO_ADDRESS(MX1ADS_IO_BASE), MX1ADS_IO_BASE, SZ_256K , DOMAIN_IO, 0, 1},
Dirq.c44 #define VA_AITC_BASE IO_ADDRESS(MX1ADS_AITC_BASE)
/linux-2.4.37.9/drivers/mtd/maps/
Dintegrator-flash.c54 #define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
55 #define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
56 #define EBI_CSR1 (IO_ADDRESS(INTEGRATOR_EBI_BASE) + INTEGRATOR_EBI_CSR1_OFFSET)
57 #define EBI_LOCK (IO_ADDRESS(INTEGRATOR_EBI_BASE) + INTEGRATOR_EBI_LOCK_OFFSET)
/linux-2.4.37.9/include/asm-arm/arch-mx1ads/
Dtime.h25 #define TIMER0_VA_BASE (IO_ADDRESS(MX1ADS_TIM1_BASE)+0x00000000)
26 #define TIMER1_VA_BASE (IO_ADDRESS(MX1ADS_TIM2_BASE)+0x00000000)
Dhardware.h34 #define IO_ADDRESS(x) (x | IO_BASE) macro
/linux-2.4.37.9/arch/arm/mach-omaha/
Dcore.c51 #define VA_IC_BASE IO_ADDRESS(PLAT_PERIPHERAL_BASE)
125 { IO_ADDRESS(0x00000000), 0x00000000, 0x1B000000, DOMAIN_IO, 0, 1 },
Dleds.c37 unsigned int ctrl = IO_ADDRESS(PLAT_DBG_LEDS); in omaha_leds_event()

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