1 /*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23 #include <linux/config.h>
24 #include <linux/sched.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/ioport.h>
30 #include <linux/interrupt.h>
31 #include <linux/spinlock.h>
32 #include <linux/init.h>
33
34 #include <asm/hardware.h>
35 #include <asm/irq.h>
36 #include <asm/system.h>
37 #include <asm/mach/pci.h>
38
39 #include <asm/hardware/pci_v3.h>
40
41 /*
42 * The V3 PCI interface chip in Integrator provides several windows from
43 * local bus memory into the PCI memory areas. Unfortunately, there
44 * are not really enough windows for our usage, therefore we reuse
45 * one of the windows for access to PCI configuration space. The
46 * memory map is as follows:
47 *
48 * Local Bus Memory Usage
49 *
50 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
51 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
52 * 60000000 - 60FFFFFF PCI IO. 16M
53 * 68000000 - 68FFFFFF PCI Configuration. 16M
54 *
55 * There are three V3 windows, each described by a pair of V3 registers.
56 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
57 * Base0 and Base1 can be used for any type of PCI memory access. Base2
58 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
59 * uses this only for PCI IO space.
60 *
61 * PCI Memory is mapped so that assigned addresses in PCI Memory match
62 * local bus memory addresses. In other words, if a PCI device is assigned
63 * address 80200000 then that address is a valid local bus address as well
64 * as a valid PCI Memory address. PCI IO addresses are mapped to start
65 * at zero. This means that local bus address 60000000 maps to PCI IO address
66 * 00000000 and so on. Device driver writers need to be aware of this
67 * distinction.
68 *
69 * Normally these spaces are mapped using the following base registers:
70 *
71 * Usage Local Bus Memory Base/Map registers used
72 *
73 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
74 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
75 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
76 * Cfg 68000000 - 68FFFFFF
77 *
78 * This means that I20 and PCI configuration space accesses will fail.
79 * When PCI configuration accesses are needed (via the uHAL PCI
80 * configuration space primitives) we must remap the spaces as follows:
81 *
82 * Usage Local Bus Memory Base/Map registers used
83 *
84 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
85 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
86 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
87 * Cfg 68000000 - 68FFFFFF LB_BASE1/LB_MAP1
88 *
89 * To make this work, the code depends on overlapping windows working.
90 * The V3 chip translates an address by checking its range within
91 * each of the BASE/MAP pairs in turn (in ascending register number
92 * order). It will use the first matching pair. So, for example,
93 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
94 * LB_BASE1/LB_MAP1, the V3 will use the translation from
95 * LB_BASE0/LB_MAP0.
96 *
97 * To allow PCI Configuration space access, the code enlarges the
98 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
99 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
100 * be remapped for use by configuration cycles.
101 *
102 * At the end of the PCI Configuration space accesses,
103 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
104 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
105 * reveal the now restored LB_BASE1/LB_MAP1 window.
106 *
107 * NOTE: We do not set up I2O mapping. I suspect that this is only
108 * for an intelligent (target) device. Using I2O disables most of
109 * the mappings into PCI memory.
110 */
111
112 // V3 access routines
113 #define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
114 #define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
115
116 #define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
117 #define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
118
119 #define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
120 #define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
121
122 /*============================================================================
123 *
124 * routine: uHALir_PCIMakeConfigAddress()
125 *
126 * parameters: bus = which bus
127 * device = which device
128 * function = which function
129 * offset = configuration space register we are interested in
130 *
131 * description: this routine will generate a platform dependant config
132 * address.
133 *
134 * calls: none
135 *
136 * returns: configuration address to play on the PCI bus
137 *
138 * To generate the appropriate PCI configuration cycles in the PCI
139 * configuration address space, you present the V3 with the following pattern
140 * (which is very nearly a type 1 (except that the lower two bits are 00 and
141 * not 01). In order for this mapping to work you need to set up one of
142 * the local to PCI aperatures to 16Mbytes in length translating to
143 * PCI configuration space starting at 0x0000.0000.
144 *
145 * PCI configuration cycles look like this:
146 *
147 * Type 0:
148 *
149 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
150 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
151 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
152 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
153 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
154 *
155 * 31:11 Device select bit.
156 * 10:8 Function number
157 * 7:2 Register number
158 *
159 * Type 1:
160 *
161 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
162 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
163 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
164 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
165 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
166 *
167 * 31:24 reserved
168 * 23:16 bus number (8 bits = 128 possible buses)
169 * 15:11 Device number (5 bits)
170 * 10:8 function number
171 * 7:2 register number
172 *
173 */
174 static spinlock_t v3_lock = SPIN_LOCK_UNLOCKED;
175
176 #define PCI_BUS_NONMEM_START 0x00000000
177 #define PCI_BUS_NONMEM_SIZE 0x10000000
178
179 #define PCI_BUS_PREMEM_START 0x10000000
180 #define PCI_BUS_PREMEM_SIZE 0x10000000
181
182 #if PCI_BUS_NONMEM_START & 0x000fffff
183 #error PCI_BUS_NONMEM_START must be megabyte aligned
184 #endif
185 #if PCI_BUS_PREMEM_START & 0x000fffff
186 #error PCI_BUS_PREMEM_START must be megabyte aligned
187 #endif
188
189 #undef V3_LB_BASE_PREFETCH
190 #define V3_LB_BASE_PREFETCH 0
191
v3_open_config_window(struct pci_dev * dev,int offset)192 static unsigned long v3_open_config_window(struct pci_dev *dev, int offset)
193 {
194 unsigned int address, mapaddress, busnr;
195
196 busnr = dev->bus->number;
197
198 /*
199 * Trap out illegal values
200 */
201 if (offset > 255)
202 BUG();
203 if (busnr > 255)
204 BUG();
205 if (dev->devfn > 255)
206 BUG();
207
208 if (busnr == 0) {
209 int slot = PCI_SLOT(dev->devfn);
210
211 /*
212 * local bus segment so need a type 0 config cycle
213 *
214 * build the PCI configuration "address" with one-hot in
215 * A31-A11
216 *
217 * mapaddress:
218 * 3:1 = config cycle (101)
219 * 0 = PCI A1 & A0 are 0 (0)
220 */
221 address = PCI_FUNC(dev->devfn) << 8;
222 mapaddress = V3_LB_MAP_TYPE_CONFIG;
223
224 if (slot > 12)
225 /*
226 * high order bits are handled by the MAP register
227 */
228 mapaddress |= 1 << (slot - 5);
229 else
230 /*
231 * low order bits handled directly in the address
232 */
233 address |= 1 << (slot + 11);
234 } else {
235 /*
236 * not the local bus segment so need a type 1 config cycle
237 *
238 * address:
239 * 23:16 = bus number
240 * 15:11 = slot number (7:3 of devfn)
241 * 10:8 = func number (2:0 of devfn)
242 *
243 * mapaddress:
244 * 3:1 = config cycle (101)
245 * 0 = PCI A1 & A0 from host bus (1)
246 */
247 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
248 address = (busnr << 16) | (dev->devfn << 8);
249 }
250
251 /*
252 * Set up base0 to see all 512Mbytes of memory space (not
253 * prefetchable), this frees up base1 for re-use by
254 * configuration memory
255 */
256 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
257 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
258
259 /*
260 * Set up base1/map1 to point into configuration space.
261 */
262 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
263 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
264 v3_writew(V3_LB_MAP1, mapaddress);
265
266 return PCI_CONFIG_VADDR + address + offset;
267 }
268
v3_close_config_window(void)269 static void v3_close_config_window(void)
270 {
271 /*
272 * Reassign base1 for use by prefetchable PCI memory
273 */
274 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
275 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
276 V3_LB_BASE_ENABLE);
277 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
278 V3_LB_MAP_TYPE_MEM_MULTIPLE);
279
280 /*
281 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
282 */
283 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
284 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
285 }
286
v3_read_config_byte(struct pci_dev * dev,int where,u8 * val)287 static int v3_read_config_byte(struct pci_dev *dev, int where, u8 *val)
288 {
289 unsigned long addr;
290 unsigned long flags;
291 u8 v;
292
293 spin_lock_irqsave(&v3_lock, flags);
294 addr = v3_open_config_window(dev, where);
295
296 v = __raw_readb(addr);
297
298 v3_close_config_window();
299 spin_unlock_irqrestore(&v3_lock, flags);
300
301 *val = v;
302 return PCIBIOS_SUCCESSFUL;
303 }
304
v3_read_config_word(struct pci_dev * dev,int where,u16 * val)305 static int v3_read_config_word(struct pci_dev *dev, int where, u16 *val)
306 {
307 unsigned long addr;
308 unsigned long flags;
309 u16 v;
310
311 spin_lock_irqsave(&v3_lock, flags);
312 addr = v3_open_config_window(dev, where);
313
314 v = __raw_readw(addr);
315
316 v3_close_config_window();
317 spin_unlock_irqrestore(&v3_lock, flags);
318
319 *val = v;
320 return PCIBIOS_SUCCESSFUL;
321 }
322
v3_read_config_dword(struct pci_dev * dev,int where,u32 * val)323 static int v3_read_config_dword(struct pci_dev *dev, int where, u32 *val)
324 {
325 unsigned long addr;
326 unsigned long flags;
327 u32 v;
328
329 spin_lock_irqsave(&v3_lock, flags);
330 addr = v3_open_config_window(dev, where);
331
332 v = __raw_readl(addr);
333
334 v3_close_config_window();
335 spin_unlock_irqrestore(&v3_lock, flags);
336
337 *val = v;
338 return PCIBIOS_SUCCESSFUL;
339 }
340
v3_write_config_byte(struct pci_dev * dev,int where,u8 val)341 static int v3_write_config_byte(struct pci_dev *dev, int where, u8 val)
342 {
343 unsigned long addr;
344 unsigned long flags;
345
346 spin_lock_irqsave(&v3_lock, flags);
347 addr = v3_open_config_window(dev, where);
348
349 __raw_writeb(val, addr);
350 __raw_readb(addr);
351
352 v3_close_config_window();
353 spin_unlock_irqrestore(&v3_lock, flags);
354
355 return PCIBIOS_SUCCESSFUL;
356 }
357
v3_write_config_word(struct pci_dev * dev,int where,u16 val)358 static int v3_write_config_word(struct pci_dev *dev, int where, u16 val)
359 {
360 unsigned long addr;
361 unsigned long flags;
362
363 spin_lock_irqsave(&v3_lock, flags);
364 addr = v3_open_config_window(dev, where);
365
366 __raw_writew(val, addr);
367 __raw_readw(addr);
368
369 v3_close_config_window();
370 spin_unlock_irqrestore(&v3_lock, flags);
371
372 return PCIBIOS_SUCCESSFUL;
373 }
374
v3_write_config_dword(struct pci_dev * dev,int where,u32 val)375 static int v3_write_config_dword(struct pci_dev *dev, int where, u32 val)
376 {
377 unsigned long addr;
378 unsigned long flags;
379
380 spin_lock_irqsave(&v3_lock, flags);
381 addr = v3_open_config_window(dev, where);
382
383 __raw_writel(val, addr);
384 __raw_readl(addr);
385
386 v3_close_config_window();
387 spin_unlock_irqrestore(&v3_lock, flags);
388
389 return PCIBIOS_SUCCESSFUL;
390 }
391
392 static struct pci_ops pci_v3_ops = {
393 .read_byte = v3_read_config_byte,
394 .read_word = v3_read_config_word,
395 .read_dword = v3_read_config_dword,
396 .write_byte = v3_write_config_byte,
397 .write_word = v3_write_config_word,
398 .write_dword = v3_write_config_dword,
399 };
400
401 static struct resource non_mem = {
402 .name = "PCI non-prefetchable",
403 .start = 0x40000000 + PCI_BUS_NONMEM_START,
404 .end = 0x40000000 + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
405 .flags = IORESOURCE_MEM,
406 };
407
408 static struct resource pre_mem = {
409 .name = "PCI prefetchable",
410 .start = 0x40000000 + PCI_BUS_PREMEM_START,
411 .end = 0x40000000 + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
412 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
413 };
414
pci_v3_setup_resources(struct resource ** resource)415 int __init pci_v3_setup_resources(struct resource **resource)
416 {
417 if (request_resource(&iomem_resource, &non_mem)) {
418 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
419 "memory region\n");
420 return -EBUSY;
421 }
422 if (request_resource(&iomem_resource, &pre_mem)) {
423 release_resource(&non_mem);
424 printk(KERN_ERR "PCI: unable to allocate prefetchable "
425 "memory region\n");
426 return -EBUSY;
427 }
428
429 /*
430 * bus->resource[0] is the IO resource for this bus
431 * bus->resource[1] is the mem resource for this bus
432 * bus->resource[2] is the prefetch mem resource for this bus
433 */
434 resource[0] = &ioport_resource;
435 resource[1] = &non_mem;
436 resource[2] = &pre_mem;
437
438 return 1;
439 }
440
441 /*
442 * These don't seem to be implemented on the Integrator I have, which
443 * means I can't get additional information on the reason for the pm2fb
444 * problems. I suppose I'll just have to mind-meld with the machine. ;)
445 */
446 #define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET)
447 #define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20)
448 #define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24)
449
v3_fault(unsigned long addr,struct pt_regs * regs)450 static int v3_fault(unsigned long addr, struct pt_regs *regs)
451 {
452 unsigned long pc = instruction_pointer(regs);
453 unsigned long instr = *(unsigned long *)pc;
454 #if 0
455 char buf[128];
456
457 sprintf(buf, "V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
458 addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
459 v3_readb(V3_LB_ISTAT));
460 printk(KERN_DEBUG "%s", buf);
461 printascii(buf);
462 #endif
463
464 v3_writeb(V3_LB_ISTAT, 0);
465 __raw_writel(3, SC_PCI);
466
467 /*
468 * If the instruction being executed was a read,
469 * make it look like it read all-ones.
470 */
471 if ((instr & 0x0c100000) == 0x04100000) {
472 int reg = (instr >> 12) & 15;
473 unsigned long val;
474
475 if (instr & 0x00400000)
476 val = 255;
477 else
478 val = -1;
479
480 regs->uregs[reg] = val;
481 regs->ARM_pc += 4;
482 return 0;
483 }
484
485 if ((instr & 0x0e100090) == 0x00100090) {
486 int reg = (instr >> 12) & 15;
487
488 regs->uregs[reg] = -1;
489 regs->ARM_pc += 4;
490 return 0;
491 }
492
493 return 1;
494 }
495
v3_irq(int irq,void * devid,struct pt_regs * regs)496 static void v3_irq(int irq, void *devid, struct pt_regs *regs)
497 {
498 #ifdef CONFIG_DEBUG_LL
499 unsigned long pc = instruction_pointer(regs);
500 unsigned long instr = *(unsigned long *)pc;
501 char buf[128];
502
503 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", irq,
504 pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
505 v3_readb(V3_LB_ISTAT));
506 printascii(buf);
507 #endif
508
509 v3_writew(V3_PCI_STAT, 0xf000);
510 v3_writeb(V3_LB_ISTAT, 0);
511 __raw_writel(3, SC_PCI);
512
513 #ifdef CONFIG_DEBUG_LL
514 /*
515 * If the instruction being executed was a read,
516 * make it look like it read all-ones.
517 */
518 if ((instr & 0x0c100000) == 0x04100000) {
519 int reg = (instr >> 16) & 15;
520 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
521 printascii(buf);
522 }
523 #endif
524 }
525
526 extern int (*external_fault)(unsigned long addr, struct pt_regs *regs);
527
528 /*
529 * V3_LB_BASE? - local bus address
530 * V3_LB_MAP? - pci bus address
531 */
pci_v3_init(void * sysdata)532 void __init pci_v3_init(void *sysdata)
533 {
534 unsigned int pci_cmd;
535 unsigned long flags;
536 unsigned int temp;
537 int ret;
538
539 /*
540 * Hook in our fault handler for PCI errors
541 */
542 external_fault = v3_fault;
543
544 spin_lock_irqsave(&v3_lock, flags);
545
546 /*
547 * Unlock V3 registers, but only if they were previously locked.
548 */
549 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
550 v3_writew(V3_SYSTEM, 0xa05f);
551
552 /*
553 * Setup window 0 - PCI non-prefetchable memory
554 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
555 */
556 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
557 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
558 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
559 V3_LB_MAP_TYPE_MEM);
560
561 /*
562 * Setup window 1 - PCI prefetchable memory
563 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
564 */
565 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
566 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
567 V3_LB_BASE_ENABLE);
568 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
569 V3_LB_MAP_TYPE_MEM_MULTIPLE);
570
571 /*
572 * Setup window 2 - PCI IO
573 */
574 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
575 V3_LB_BASE_ENABLE);
576 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
577
578 /*
579 * Disable PCI to host IO cycles
580 */
581 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
582 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
583 v3_writew(V3_PCI_CFG, temp);
584
585 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
586 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
587
588 /*
589 * Set the V3 FIFO such that writes have higher priority than
590 * reads, and local bus write causes local bus read fifo flush.
591 * Same for PCI.
592 */
593 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
594
595 /*
596 * Re-lock the system register.
597 */
598 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
599 v3_writew(V3_SYSTEM, temp);
600
601 /*
602 * Clear any error conditions, and enable write errors.
603 */
604 v3_writeb(V3_LB_ISTAT, 0);
605 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
606 v3_writeb(V3_LB_IMASK, 0x28);
607 __raw_writel(3, SC_PCI);
608
609 /*
610 * Grab the PCI error interrupt.
611 */
612 ret = request_irq(IRQ_V3INT, v3_irq, 0, "V3 error", NULL);
613 if (ret)
614 printk(KERN_ERR "PCI: unable to grab PCI error "
615 "interrupt: %d\n", ret);
616
617 spin_unlock_irqrestore(&v3_lock, flags);
618
619 pci_scan_bus(0, &pci_v3_ops, sysdata);
620
621 pci_cmd = PCI_COMMAND_MEMORY |
622 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
623
624 v3_writew(V3_PCI_CMD, pci_cmd);
625
626 v3_writeb(V3_LB_ISTAT, ~0x40);
627 v3_writeb(V3_LB_IMASK, 0x68);
628
629 #if 0
630 ret = request_irq(IRQ_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
631 if (ret)
632 printk(KERN_ERR "PCI: unable to grab local bus timeout ".
633 "interrupt: %d\n", ret);
634 #endif
635 }
636