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Searched refs:GT_WRITE (Results 1 – 16 of 16) sorted by relevance

/linux-2.4.37.9/arch/mips/gt64120/momenco_ocelot/
Dsetup.c114 GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21); in PMON_v1_setup()
117 GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21); in PMON_v1_setup()
120 GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21); in PMON_v1_setup()
125 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020); in PMON_v1_setup()
126 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000); in PMON_v1_setup()
127 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024); in PMON_v1_setup()
128 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001); in PMON_v1_setup()
187 GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21); in momenco_ocelot_setup()
188 GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21); in momenco_ocelot_setup()
189 GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21); in momenco_ocelot_setup()
[all …]
/linux-2.4.37.9/arch/mips/gt64120/common/
Dtime.c41 GT_WRITE(GT_INTRCAUSE_OFS, 0); in gt64120_irq()
42 GT_WRITE(GT_HINTRCAUSE_OFS, 0); in gt64120_irq()
69 GT_WRITE(GT_TC_CONTROL_OFS, 0); in gt64120_time_init()
71 GT_WRITE(GT_TC3_OFS, Sys_clock / 100); in gt64120_time_init()
89 GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); in gt64120_time_init()
91 GT_WRITE(GT_INTRCAUSE_OFS, 0x0); in gt64120_time_init()
93 GT_WRITE(GT_INTRMASK_OFS, 0x800); in gt64120_time_init()
95 GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); in gt64120_time_init()
97 GT_WRITE(GT_HINTRMASK_OFS, 0x0); in gt64120_time_init()
Dpci.c69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); in pci0ReadConfigReg()
110 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); in pci0WriteConfigReg()
113 GT_WRITE(GT_PCI0_CFGDATA_OFS, data); in pci0WriteConfigReg()
/linux-2.4.37.9/arch/sh/overdrive/
Dgalileo.c46 #define GT_WRITE(x,v) writel((v),GT64111_REG(x)) macro
93 GT_WRITE(block##_LO_DEC_ADR,GT_MEM_LO_ADR(a));\
94 GT_WRITE(block##_HI_DEC_ADR,GT_MEM_HI_ADR(a+s-1))
97 GT_WRITE(block##_LO_DEC_ADR,GT_MEM_SUB_ADR(a));\
98 GT_WRITE(block##_HI_DEC_ADR,GT_MEM_SUB_ADR(a+s-1))
106 GT_WRITE(PCI_##block##_BANK_SIZE,GT_BAR_MASK((s-1)));\
111 GT_WRITE(PCI_##block##_BANK_SIZE,0),\
116 #define DISABLE_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0x7ff);\
117 GT_WRITE(x##_HI_DEC_ADR,0x00)
119 #define DISABLE_SUB_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0xff);\
[all …]
/linux-2.4.37.9/arch/mips/momentum/ocelot_g/
Dgt-irq.c134 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); in gt64240_p0int_irq()
197 GT_WRITE(GT_INTRCAUSE_OFS, 0); in gt64240_irq()
198 GT_WRITE(GT_HINTRCAUSE_OFS, 0); in gt64240_irq()
246 GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); in gt64240_time_init()
249 GT_WRITE(TIMER_COUNTER0, bus_clock / 100); in gt64240_time_init()
267 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); in gt64240_time_init()
270 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); in gt64240_time_init()
273 GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); in gt64240_time_init()
276 GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); in gt64240_time_init()
Dpci.c130 GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT); in galileo_pcibios_read_config_dword()
134 GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT); in galileo_pcibios_read_config_dword()
143 GT_WRITE(address_reg, address); in galileo_pcibios_read_config_dword()
171 GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT); in galileo_pcibios_read_config_word()
175 GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT); in galileo_pcibios_read_config_word()
184 GT_WRITE(address_reg, address); in galileo_pcibios_read_config_word()
222 GT_WRITE(address_reg, address); in galileo_pcibios_read_config_byte()
260 GT_WRITE(address_reg, address); in galileo_pcibios_write_config_dword()
263 GT_WRITE(data_reg, val); in galileo_pcibios_write_config_dword()
299 GT_WRITE(address_reg, address); in galileo_pcibios_write_config_word()
[all …]
Dsetup.c203 GT_WRITE(0x468, 0xfef73); in momenco_ocelot_g_setup()
220 GT_WRITE(0, tmp | (1<<14)); in setup_l3cache()
Dgt64240_dep.h40 #define GT_WRITE(ofs, data) \ macro
/linux-2.4.37.9/arch/mips/galileo-boards/ev96100/
Dsetup.c149 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | in ev96100_setup()
152 GT_WRITE(GT_PCI0_CFGADDR_OFS, in ev96100_setup()
163 GT_WRITE(GT_PCI0_CFGADDR_OFS, in ev96100_setup()
169 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp); in ev96100_setup()
172 GT_WRITE(GT_PCI0_CFGADDR_OFS, in ev96100_setup()
187 GT_WRITE(GT_PCI0_CFGADDR_OFS, in get_gt_devid()
/linux-2.4.37.9/arch/mips/pci/
Dops-gt64120.c58 GT_WRITE(GT_INTRCAUSE_OFS, intr & ~GT_ERR_BITS); in gt64120_config_access()
61 GT_WRITE(GT_PCI0_CFGADDR_OFS, in gt64120_config_access()
73 GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); in gt64120_config_access()
94 GT_WRITE(GT_INTRCAUSE_OFS, intr & ~GT_ERR_BITS); in gt64120_config_access()
/linux-2.4.37.9/arch/mips/mips-boards/generic/
Dpci.c104 GT_WRITE(GT_PCI0_CFGADDR_OFS, in pcibios_init()
112 GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(GT64120_BASE)); in pcibios_init()
Dinit.c148 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | in prom_init()
151 GT_WRITE(GT_PCI0_CMD_OFS, 0); in prom_init()
/linux-2.4.37.9/drivers/net/
Dgt64240eth.h120 GT_WRITE((gp)->port_offset + (offset), (data))
128 #define GT64240_WRITE(ofs, data) GT_WRITE((ofs), (data))
Dgt64240eth.c677 GT_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask); in enable_ether_irq()
687 GT_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask); in disable_ether_irq()
/linux-2.4.37.9/include/asm-mips/gt64120/
Dgt64120.h453 #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) macro
/linux-2.4.37.9/include/asm-mips64/gt64120/
Dgt64120.h453 #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) macro