1 /*
2 *
3 * Copyright 2002 Momentum Computer
4 * Author: mdharm@momenco.com
5 *
6 * arch/mips/momentum/ocelot_g/gt_irq.c
7 * Interrupt routines for gt64240. Currently it only handles timer irq.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <asm/ptrace.h>
18 #include <linux/config.h>
19 #include <linux/sched.h>
20 #include <linux/kernel_stat.h>
21 #include <asm/io.h>
22 #include "gt64240.h"
23
24 unsigned long bus_clock;
25
26 /*
27 * These are interrupt handlers for the GT on-chip interrupts. They
28 * all come in to the MIPS on a single interrupt line, and have to
29 * be handled and ack'ed differently than other MIPS interrupts.
30 */
31
32 #if CURRENTLY_UNUSED
33
34 struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
35 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
36
37 /*
38 * Hooks IRQ handler to the system. When the system is interrupted
39 * the interrupt service routine is called.
40 *
41 * Inputs :
42 * int_cause - The interrupt cause number. In EVB64120 two parameters
43 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
44 * bit_num - Indicates which bit number in the cause register
45 * isr_ptr - Pointer to the interrupt service routine
46 */
hook_irq_handler(int int_cause,int bit_num,void * isr_ptr)47 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
48 {
49 irq_handlers[int_cause][bit_num].routine = isr_ptr;
50 }
51
52
53 /*
54 * Enables the IRQ on Galileo Chip
55 *
56 * Inputs :
57 * int_cause - The interrupt cause number. In EVB64120 two parameters
58 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
59 * bit_num - Indicates which bit number in the cause register
60 *
61 * Outputs :
62 * 1 if succesful, 0 if failure
63 */
enable_galileo_irq(int int_cause,int bit_num)64 int enable_galileo_irq(int int_cause, int bit_num)
65 {
66 if (int_cause == INT_CAUSE_MAIN)
67 SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
68 else if (int_cause == INT_CAUSE_HIGH)
69 SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
70 (1 << bit_num));
71 else
72 return 0;
73
74 return 1;
75 }
76
77 /*
78 * Disables the IRQ on Galileo Chip
79 *
80 * Inputs :
81 * int_cause - The interrupt cause number. In EVB64120 two parameters
82 * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
83 * bit_num - Indicates which bit number in the cause register
84 *
85 * Outputs :
86 * 1 if succesful, 0 if failure
87 */
disable_galileo_irq(int int_cause,int bit_num)88 int disable_galileo_irq(int int_cause, int bit_num)
89 {
90 if (int_cause == INT_CAUSE_MAIN)
91 RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
92 (1 << bit_num));
93 else if (int_cause == INT_CAUSE_HIGH)
94 RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
95 (1 << bit_num));
96 else
97 return 0;
98 return 1;
99 }
100 #endif /* UNUSED */
101
102 /*
103 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
104 *
105 * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
106 * routine can handle, for now.
107 *
108 * In the future, we'll route more interrupts to this pin, and that's why
109 * we keep this particular structure in the function.
110 */
111
gt64240_p0int_irq(int irq,void * dev_id,struct pt_regs * regs)112 static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs)
113 {
114 uint32_t irq_src, irq_src_mask;
115 int handled;
116
117 /* get the low interrupt cause register */
118 GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src);
119
120 /* get the mask register for this pin */
121 GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask);
122
123 /* mask off only the interrupts we're interested in */
124 irq_src = irq_src & irq_src_mask;
125
126 handled = 0;
127
128 /* Check for timer interrupt */
129 if (irq_src & 0x00000100) {
130 handled = 1;
131 irq_src &= ~0x00000100;
132
133 /* Clear any pending cause bits */
134 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
135
136 /* handle the timer call */
137 do_timer(regs);
138 }
139
140 if (irq_src) {
141 printk(KERN_INFO
142 "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
143 irq_src);
144 }
145 }
146
147 /*
148 * Interrupt handler for interrupts coming from the Galileo chip.
149 * It could be built in ethernet ports etc...
150 */
gt64240_irq(int irq,void * dev_id,struct pt_regs * regs)151 static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs)
152 {
153 unsigned int irq_src, int_high_src, irq_src_mask,
154 int_high_src_mask;
155 int handled;
156
157 #if 0
158 GT_READ(GT_INTRCAUSE_OFS, &irq_src);
159 GT_READ(GT_INTRMASK_OFS, &irq_src_mask);
160 GT_READ(GT_HINTRCAUSE_OFS, &int_high_src);
161 GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask);
162 #endif
163 irq_src = irq_src & irq_src_mask;
164 int_high_src = int_high_src & int_high_src_mask;
165
166 handled = 0;
167
168 /* Execute all interrupt handlers */
169 /* Check for timer interrupt */
170 if (irq_src & 0x00000800) {
171 handled = 1;
172 irq_src &= ~0x00000800;
173 // RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8);
174 do_timer(regs);
175 }
176
177 if (irq_src) {
178 printk(KERN_INFO
179 "Other Galileo interrupt received irq_src %x\n",
180 irq_src);
181 #if CURRENTLY_UNUSED
182 for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) {
183 if (irq_src & (1 << count)) {
184 if (irq_handlers[INT_CAUSE_MAIN][count].
185 routine) {
186 queue_task(&irq_handlers
187 [INT_CAUSE_MAIN][count],
188 &tq_immediate);
189 mark_bh(IMMEDIATE_BH);
190 handled = 1;
191 }
192 }
193 }
194 #endif /* UNUSED */
195 }
196 #if 0
197 GT_WRITE(GT_INTRCAUSE_OFS, 0);
198 GT_WRITE(GT_HINTRCAUSE_OFS, 0);
199 #endif
200
201 #undef GALILEO_I2O
202 #ifdef GALILEO_I2O
203 /*
204 * Future I2O support. We currently attach I2O interrupt handlers to
205 * the Galileo interrupt (int 4) and handle them in do_IRQ.
206 */
207 if (isInBoundDoorBellInterruptSet()) {
208 printk(KERN_INFO "I2O doorbell interrupt received.\n");
209 handled = 1;
210 }
211
212 if (isInBoundPostQueueInterruptSet()) {
213 printk(KERN_INFO "I2O Queue interrupt received.\n");
214 handled = 1;
215 }
216
217 /*
218 * This normally would be outside of the ifdef, but since we're
219 * handling I2O outside of this handler, this printk shows up every
220 * time we get a valid I2O interrupt. So turn this off for now.
221 */
222 if (handled == 0) {
223 if (counter < 50) {
224 printk("Spurious Galileo interrupt...\n");
225 counter++;
226 }
227 }
228 #endif
229 }
230
231 /*
232 * Initializes timer using galileo's built in timer.
233 */
234
235 /*
236 * This will ignore the standard MIPS timer interrupt handler
237 * that is passed in as *irq (=irq0 in ../kernel/time.c).
238 * We will do our own timer interrupt handling.
239 */
gt64240_time_init(void)240 void gt64240_time_init(void)
241 {
242 extern irq_desc_t irq_desc[NR_IRQS];
243 static struct irqaction timer;
244
245 /* Stop the timer -- we'll use timer #0 */
246 GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
247
248 /* Load timer value for 100 Hz */
249 GT_WRITE(TIMER_COUNTER0, bus_clock / 100);
250
251 /*
252 * Create the IRQ structure entry for the timer. Since we're too early
253 * in the boot process to use the "request_irq()" call, we'll hard-code
254 * the values to the correct interrupt line.
255 */
256 timer.handler = >64240_p0int_irq;
257 timer.flags = SA_SHIRQ | SA_INTERRUPT;
258 timer.name = "timer";
259 timer.dev_id = NULL;
260 timer.next = NULL;
261 timer.mask = 0;
262 irq_desc[6].action = &timer;
263
264 enable_irq(6);
265
266 /* Clear any pending cause bits */
267 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
268
269 /* Enable the interrupt for timer 0 */
270 GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
271
272 /* Enable the timer interrupt for GT-64240 pin P0_INT# */
273 GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
274
275 /* Configure and start the timer */
276 GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
277 }
278
gt64240_irq_init(void)279 void gt64240_irq_init(void)
280 {
281 #if CURRENTLY_UNUSED
282 int i, j;
283
284 /* Reset irq handlers pointers to NULL */
285 for (i = 0; i < MAX_CAUSE_REGS; i++) {
286 for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
287 irq_handlers[i][j].next = NULL;
288 irq_handlers[i][j].sync = 0;
289 irq_handlers[i][j].routine = NULL;
290 irq_handlers[i][j].data = NULL;
291 }
292 }
293 #endif
294 }
295