1 /*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * MIPS boards specific PCI support.
19 */
20 #include <linux/config.h>
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25
26 #include <asm/mips-boards/generic.h>
27 #include <asm/gt64120/gt64120.h>
28 #include <asm/mips-boards/bonito64.h>
29 #ifdef CONFIG_MIPS_MALTA
30 #include <asm/mips-boards/malta.h>
31 #endif
32 #include <asm/mips-boards/msc01_pci.h>
33
34 extern struct pci_ops bonito64_pci_ops;
35 extern struct pci_ops gt64120_pci_ops;
36 extern struct pci_ops msc_pci_ops;
37
malta_fixup(void)38 static void __init malta_fixup(void)
39 {
40 #ifdef CONFIG_MIPS_MALTA
41 struct pci_dev *pdev;
42 unsigned char reg_val;
43
44 pci_for_each_dev(pdev) {
45 if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
46 && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB)
47 && (PCI_SLOT(pdev->devfn) == 0x0a)) {
48 /*
49 * IDE Decode enable.
50 */
51 pci_read_config_byte(pdev, 0x41, ®_val);
52 pci_write_config_byte(pdev, 0x41, reg_val | 0x80);
53 pci_read_config_byte(pdev, 0x43, ®_val);
54 pci_write_config_byte(pdev, 0x43, reg_val | 0x80);
55 }
56
57 if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
58 && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0)
59 && (PCI_SLOT(pdev->devfn) == 0x0a)) {
60 /*
61 * Set top of main memory accessible by ISA or DMA
62 * devices to 16 Mb.
63 */
64 pci_read_config_byte(pdev, 0x69, ®_val);
65 pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
66 }
67 }
68
69 /*
70 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
71 * Controller.
72 * This should be done in the bios/bootprom and will be fixed in
73 * a later revision of YAMON (the MIPS boards boot prom).
74 */
75 /* Entering config state. */
76 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
77
78 /* Activate floppy controller. */
79 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
80 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
81 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
82 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
83
84 /* Exit config state. */
85 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
86 #endif
87 }
88
pcibios_init(void)89 void __init pcibios_init(void)
90 {
91 printk("PCI: Probing PCI hardware on host bus 0.\n");
92
93 switch (mips_revision_corid) {
94 case MIPS_REVISION_CORID_QED_RM5261:
95 case MIPS_REVISION_CORID_CORE_LV:
96 case MIPS_REVISION_CORID_CORE_FPGA:
97 /*
98 * Due to a bug in the Galileo system controller, we need
99 * to setup the PCI BAR for the Galileo internal registers.
100 * This should be done in the bios/bootprom and will be
101 * fixed in a later revision of YAMON (the MIPS boards
102 * boot prom).
103 */
104 GT_WRITE(GT_PCI0_CFGADDR_OFS,
105 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
106 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
107 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
108 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
109 GT_PCI0_CFGADDR_CONFIGEN_BIT );
110
111 /* Perform the write */
112 GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(GT64120_BASE));
113
114 pci_scan_bus(0, >64120_pci_ops, NULL);
115 break;
116
117 case MIPS_REVISION_CORID_BONITO64:
118 case MIPS_REVISION_CORID_CORE_20K:
119 pci_scan_bus(0, &bonito64_pci_ops, NULL);
120 break;
121
122 case MIPS_REVISION_CORID_CORE_MSC:
123 pci_scan_bus(0, &msc_pci_ops, NULL);
124 break;
125 }
126
127 malta_fixup();
128 }
129
130 struct pci_fixup pcibios_fixups[] = {
131 { 0 }
132 };
133
134 /*
135 * Called after each bus is probed, but before its children
136 * are examined.
137 */
pcibios_fixup_bus(struct pci_bus * b)138 void __devinit pcibios_fixup_bus(struct pci_bus *b)
139 {
140 pci_read_bridge_bases(b);
141 }
142
pcibios_assign_all_busses(void)143 unsigned int pcibios_assign_all_busses(void)
144 {
145 return 1;
146 }
147