1 /*
2 * Copyright 2002 Momentum Computer
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25 #include <linux/config.h>
26 #include <linux/types.h>
27 #include <linux/pci.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/version.h>
31 #include <asm/pci.h>
32 #include <asm/io.h>
33 #include "gt64240.h"
34
35 #include <linux/init.h>
36
37 #define SELF 0
38 #define MASTER_ABORT_BIT 0x100
39
40 /*
41 * These functions and structures provide the BIOS scan and mapping of the PCI
42 * devices.
43 */
44
45 #define MAX_PCI_DEVS 10
46
47 void gt64240_board_pcibios_fixup_bus(struct pci_bus* c);
48
49 /* Functions to implement "pci ops" */
50 static int galileo_pcibios_read_config_word(struct pci_dev *dev,
51 int offset, u16 * val);
52 static int galileo_pcibios_read_config_byte(struct pci_dev *dev,
53 int offset, u8 * val);
54 static int galileo_pcibios_read_config_dword(struct pci_dev *dev,
55 int offset, u32 * val);
56 static int galileo_pcibios_write_config_byte(struct pci_dev *dev,
57 int offset, u8 val);
58 static int galileo_pcibios_write_config_word(struct pci_dev *dev,
59 int offset, u16 val);
60 static int galileo_pcibios_write_config_dword(struct pci_dev *dev,
61 int offset, u32 val);
62
63 /*
64 * General-purpose PCI functions.
65 */
66
67
68 /*
69 * pci_range_ck -
70 *
71 * Check if the pci device that are trying to access does really exists
72 * on the evaluation board.
73 *
74 * Inputs :
75 * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
76 * dev - number of device on the specific pci bus
77 *
78 * Outpus :
79 * 0 - if OK , 1 - if failure
80 */
pci_range_ck(unsigned char bus,unsigned char dev)81 static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
82 {
83 /* Accessing device 31 crashes the GT-64240. */
84 if (dev < 5)
85 return 0;
86 return -1;
87 }
88
89 /*
90 * galileo_pcibios_(read/write)_config_(dword/word/byte) -
91 *
92 * reads/write a dword/word/byte register from the configuration space
93 * of a device.
94 *
95 * Note that bus 0 and bus 1 are local, and we assume all other busses are
96 * bridged from bus 1. This is a safe assumption, since any other
97 * configuration will require major modifications to the CP7000G
98 *
99 * Inputs :
100 * bus - bus number
101 * dev - device number
102 * offset - register offset in the configuration space
103 * val - value to be written / read
104 *
105 * Outputs :
106 * PCIBIOS_SUCCESSFUL when operation was succesfull
107 * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
108 * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
109 */
110
galileo_pcibios_read_config_dword(struct pci_dev * device,int offset,u32 * val)111 static int galileo_pcibios_read_config_dword(struct pci_dev *device,
112 int offset, u32* val)
113 {
114 int dev, bus, func;
115 uint32_t address_reg, data_reg;
116 uint32_t address;
117
118 bus = device->bus->number;
119 dev = PCI_SLOT(device->devfn);
120 func = PCI_FUNC(device->devfn);
121
122 /* verify the range */
123 if (pci_range_ck(bus, dev))
124 return PCIBIOS_DEVICE_NOT_FOUND;
125
126 /* select the GT-64240 registers to communicate with the PCI bus */
127 if (bus == 0) {
128 address_reg = PCI_0CONFIGURATION_ADDRESS;
129 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
130 GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT);
131 } else {
132 address_reg = PCI_1CONFIGURATION_ADDRESS;
133 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
134 GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT);
135 if (bus == 1)
136 bus = 0;
137 }
138
139 address = (bus << 16) | (dev << 11) | (func << 8) |
140 (offset & 0xfc) | 0x80000000;
141
142 /* start the configuration cycle */
143 GT_WRITE(address_reg, address);
144
145 /* read the data */
146 GT_READ(data_reg, val);
147
148 return PCIBIOS_SUCCESSFUL;
149 }
150
151
galileo_pcibios_read_config_word(struct pci_dev * device,int offset,u16 * val)152 static int galileo_pcibios_read_config_word(struct pci_dev *device,
153 int offset, u16* val)
154 {
155 int dev, bus, func;
156 uint32_t address_reg, data_reg;
157 uint32_t address;
158
159 bus = device->bus->number;
160 dev = PCI_SLOT(device->devfn);
161 func = PCI_FUNC(device->devfn);
162
163 /* verify the range */
164 if (pci_range_ck(bus, dev))
165 return PCIBIOS_DEVICE_NOT_FOUND;
166
167 /* select the GT-64240 registers to communicate with the PCI bus */
168 if (bus == 0) {
169 address_reg = PCI_0CONFIGURATION_ADDRESS;
170 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
171 GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT);
172 } else {
173 address_reg = PCI_1CONFIGURATION_ADDRESS;
174 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
175 GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT);
176 if (bus == 1)
177 bus = 0;
178 }
179
180 address = (bus << 16) | (dev << 11) | (func << 8) |
181 (offset & 0xfc) | 0x80000000;
182
183 /* start the configuration cycle */
184 GT_WRITE(address_reg, address);
185
186 /* read the data */
187 GT_READ_16(data_reg + (offset & 0x3), val);
188
189 return PCIBIOS_SUCCESSFUL;
190 }
191
galileo_pcibios_read_config_byte(struct pci_dev * device,int offset,u8 * val)192 static int galileo_pcibios_read_config_byte(struct pci_dev *device,
193 int offset, u8* val)
194 {
195 int dev, bus, func;
196 uint32_t address_reg, data_reg;
197 uint32_t address;
198
199 bus = device->bus->number;
200 dev = PCI_SLOT(device->devfn);
201 func = PCI_FUNC(device->devfn);
202
203 /* verify the range */
204 if (pci_range_ck(bus, dev))
205 return PCIBIOS_DEVICE_NOT_FOUND;
206
207 /* select the GT-64240 registers to communicate with the PCI bus */
208 if (bus == 0) {
209 address_reg = PCI_0CONFIGURATION_ADDRESS;
210 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
211 } else {
212 address_reg = PCI_1CONFIGURATION_ADDRESS;
213 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
214 if (bus == 1)
215 bus = 0;
216 }
217
218 address = (bus << 16) | (dev << 11) | (func << 8) |
219 (offset & 0xfc) | 0x80000000;
220
221 /* start the configuration cycle */
222 GT_WRITE(address_reg, address);
223
224 /* write the data */
225 GT_READ_8(data_reg + (offset & 0x3), val);
226
227 return PCIBIOS_SUCCESSFUL;
228 }
229
galileo_pcibios_write_config_dword(struct pci_dev * device,int offset,u32 val)230 static int galileo_pcibios_write_config_dword(struct pci_dev *device,
231 int offset, u32 val)
232 {
233 int dev, bus, func;
234 uint32_t address_reg, data_reg;
235 uint32_t address;
236
237 bus = device->bus->number;
238 dev = PCI_SLOT(device->devfn);
239 func = PCI_FUNC(device->devfn);
240
241 /* verify the range */
242 if (pci_range_ck(bus, dev))
243 return PCIBIOS_DEVICE_NOT_FOUND;
244
245 /* select the GT-64240 registers to communicate with the PCI bus */
246 if (bus == 0) {
247 address_reg = PCI_0CONFIGURATION_ADDRESS;
248 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
249 } else {
250 address_reg = PCI_1CONFIGURATION_ADDRESS;
251 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
252 if (bus == 1)
253 bus = 0;
254 }
255
256 address = (bus << 16) | (dev << 11) | (func << 8) |
257 (offset & 0xfc) | 0x80000000;
258
259 /* start the configuration cycle */
260 GT_WRITE(address_reg, address);
261
262 /* write the data */
263 GT_WRITE(data_reg, val);
264
265 return PCIBIOS_SUCCESSFUL;
266 }
267
268
galileo_pcibios_write_config_word(struct pci_dev * device,int offset,u16 val)269 static int galileo_pcibios_write_config_word(struct pci_dev *device,
270 int offset, u16 val)
271 {
272 int dev, bus, func;
273 uint32_t address_reg, data_reg;
274 uint32_t address;
275
276 bus = device->bus->number;
277 dev = PCI_SLOT(device->devfn);
278 func = PCI_FUNC(device->devfn);
279
280 /* verify the range */
281 if (pci_range_ck(bus, dev))
282 return PCIBIOS_DEVICE_NOT_FOUND;
283
284 /* select the GT-64240 registers to communicate with the PCI bus */
285 if (bus == 0) {
286 address_reg = PCI_0CONFIGURATION_ADDRESS;
287 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
288 } else {
289 address_reg = PCI_1CONFIGURATION_ADDRESS;
290 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
291 if (bus == 1)
292 bus = 0;
293 }
294
295 address = (bus << 16) | (dev << 11) | (func << 8) |
296 (offset & 0xfc) | 0x80000000;
297
298 /* start the configuration cycle */
299 GT_WRITE(address_reg, address);
300
301 /* write the data */
302 GT_WRITE_16(data_reg + (offset & 0x3), val);
303
304 return PCIBIOS_SUCCESSFUL;
305 }
306
galileo_pcibios_write_config_byte(struct pci_dev * device,int offset,u8 val)307 static int galileo_pcibios_write_config_byte(struct pci_dev *device,
308 int offset, u8 val)
309 {
310 int dev, bus, func;
311 uint32_t address_reg, data_reg;
312 uint32_t address;
313
314 bus = device->bus->number;
315 dev = PCI_SLOT(device->devfn);
316 func = PCI_FUNC(device->devfn);
317
318 /* verify the range */
319 if (pci_range_ck(bus, dev))
320 return PCIBIOS_DEVICE_NOT_FOUND;
321
322 /* select the GT-64240 registers to communicate with the PCI bus */
323 if (bus == 0) {
324 address_reg = PCI_0CONFIGURATION_ADDRESS;
325 data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER;
326 } else {
327 address_reg = PCI_1CONFIGURATION_ADDRESS;
328 data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER;
329 if (bus == 1)
330 bus = 0;
331 }
332
333 address = (bus << 16) | (dev << 11) | (func << 8) |
334 (offset & 0xfc) | 0x80000000;
335
336 /* start the configuration cycle */
337 GT_WRITE(address_reg, address);
338
339 /* write the data */
340 GT_WRITE_8(data_reg + (offset & 0x3), val);
341
342 return PCIBIOS_SUCCESSFUL;
343 }
344
345 struct pci_ops galileo_pci_ops = {
346 galileo_pcibios_read_config_byte,
347 galileo_pcibios_read_config_word,
348 galileo_pcibios_read_config_dword,
349 galileo_pcibios_write_config_byte,
350 galileo_pcibios_write_config_word,
351 galileo_pcibios_write_config_dword
352 };
353
354 struct pci_fixup pcibios_fixups[] = {
355 {0}
356 };
357
pcibios_fixup_bus(struct pci_bus * c)358 void __init pcibios_fixup_bus(struct pci_bus *c)
359 {
360 gt64240_board_pcibios_fixup_bus(c);
361 }
362
363
364 /********************************************************************
365 * pci0P2PConfig - This function set the PCI_0 P2P configurate.
366 * For more information on the P2P read PCI spec.
367 *
368 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
369 * Boundry.
370 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
371 * Boundry.
372 * unsigned int busNum - The CPI bus number to which the PCI interface
373 * is connected.
374 * unsigned int devNum - The PCI interface's device number.
375 *
376 * Returns: true.
377 */
pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh,unsigned int busNum,unsigned int devNum)378 void pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh,
379 unsigned int busNum,unsigned int devNum)
380 {
381 uint32_t regData;
382
383 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
384 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
385 GT_WRITE(PCI_0P2P_CONFIGURATION, regData);
386 }
387
388 /********************************************************************
389 * pci1P2PConfig - This function set the PCI_1 P2P configurate.
390 * For more information on the P2P read PCI spec.
391 *
392 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
393 * Boundry.
394 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
395 * Boundry.
396 * unsigned int busNum - The CPI bus number to which the PCI interface
397 * is connected.
398 * unsigned int devNum - The PCI interface's device number.
399 *
400 * Returns: true.
401 */
pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh,unsigned int busNum,unsigned int devNum)402 void pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh,
403 unsigned int busNum,unsigned int devNum)
404 {
405 uint32_t regData;
406
407 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
408 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
409 GT_WRITE(PCI_1P2P_CONFIGURATION, regData);
410 }
411
pcibios_init(void)412 void __init pcibios_init(void)
413 {
414 /* Reset PCI I/O and PCI MEM values */
415 ioport_resource.start = 0xe0000000;
416 ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
417 iomem_resource.start = 0xc0000000;
418 iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
419
420 pci_scan_bus(0, &galileo_pci_ops, NULL);
421 pci_scan_bus(1, &galileo_pci_ops, NULL);
422 }
423
pcibios_assign_all_busses(void)424 unsigned __init int pcibios_assign_all_busses(void)
425 {
426 return 1;
427 }
428