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Searched refs:x86_pmu (Results 1 – 14 of 14) sorted by relevance

/linux-6.1.9/arch/x86/events/intel/
Dlbr.c129 if (pmi && x86_pmu.version >= 4) in __intel_pmu_lbr_enable()
137 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; in __intel_pmu_lbr_enable()
167 for (i = 0; i < x86_pmu.lbr_nr; i++) in intel_pmu_lbr_reset_32()
168 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
175 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_reset_64()
176 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
177 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
178 if (x86_pmu.lbr_has_info) in intel_pmu_lbr_reset_64()
179 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
186 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
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Dcore.c2235 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); in __intel_pmu_snapshot_branch_stack()
2511 if (left == x86_pmu.max_period) { in icl_set_topdown_event_period()
2677 x86_pmu.num_topdown_events - 1); in icl_update_topdown_event()
2752 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) in intel_pmu_enable_fixed()
2759 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { in intel_pmu_enable_fixed()
2874 if (x86_pmu.version >= 2) { in intel_pmu_reset()
2880 if (x86_pmu.lbr_nr) { in intel_pmu_reset()
2910 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || in x86_pmu_handle_guest_pebs()
2915 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) { in x86_pmu_handle_guest_pebs()
2968 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); in handle_pmi_common()
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Dds.c129 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; in intel_pmu_pebs_data_source_adl()
133 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; in intel_pmu_pebs_data_source_adl()
262 if (x86_pmu.pebs_no_tlb) { in load_latency_data()
272 if (!x86_pmu.pebs_block) { in load_latency_data()
458 size_t bsiz = x86_pmu.pebs_buffer_size; in alloc_pebs_buffer()
462 if (!x86_pmu.pebs) in alloc_pebs_buffer()
473 if (x86_pmu.intel_cap.pebs_format < 2) { in alloc_pebs_buffer()
487 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); in alloc_pebs_buffer()
497 if (!x86_pmu.pebs) in release_pebs_buffer()
505 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
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Dp6.c201 static __initconst const struct x86_pmu p6_pmu = {
242 x86_pmu.attr_rdpmc_broken = 1; in p6_pmu_rdpmc_quirk()
243 x86_pmu.attr_rdpmc = 0; in p6_pmu_rdpmc_quirk()
249 x86_pmu = p6_pmu; in p6_pmu_init()
Dp4.c922 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in p4_pmu_disable_all()
1001 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in p4_pmu_enable_all()
1026 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in p4_pmu_set_period()
1043 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in p4_pmu_handle_irq()
1062 if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) in p4_pmu_handle_irq()
1335 static __initconst const struct x86_pmu p4_pmu = {
1387 x86_pmu = p4_pmu; in p4_pmu_init()
1398 for (i = 0; i < x86_pmu.num_counters; i++) { in p4_pmu_init()
Dknc.c290 static const struct x86_pmu knc_pmu __initconst = {
316 x86_pmu = knc_pmu; in knc_pmu_init()
Dbts.c590 if (!boot_cpu_has(X86_FEATURE_DTES64) || !x86_pmu.bts) in bts_init()
/linux-6.1.9/arch/x86/events/
Dcore.c47 struct x86_pmu x86_pmu __read_mostly;
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
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Dperf_event.h692 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
712 bool __Fp = x86_pmu._field; \
735 struct x86_pmu { struct
987 __quirk.next = x86_pmu.quirks; \
988 x86_pmu.quirks = &__quirk; \
1046 extern struct x86_pmu x86_pmu __read_mostly;
1048 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period);
1049 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update);
1061 return x86_pmu.lbr_sel_map && in x86_pmu_has_lbr_callstack()
1062 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; in x86_pmu_has_lbr_callstack()
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/linux-6.1.9/arch/x86/events/amd/
Dcore.c324 if (!(x86_pmu.flags & PMU_FL_PAIR)) in amd_is_pair_event_code()
333 DEFINE_STATIC_CALL_RET0(amd_pmu_branch_hw_config, *x86_pmu.hw_config);
350 if ((x86_pmu.flags & PMU_FL_PAIR) && amd_is_pair_event_code(&event->hw)) in amd_core_hw_config()
379 if (has_branch_stack(event) && !x86_pmu.lbr_nr) in amd_pmu_hw_config()
406 for (i = 0; i < x86_pmu.num_counters; i++) { in __amd_put_nb_event_constraints()
473 for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) { in __amd_get_nb_event_constraints()
516 for (i = 0; i < x86_pmu.num_counters; i++) { in amd_alloc_nb()
528 if (x86_pmu.lbr_nr) in amd_pmu_cpu_reset()
531 if (x86_pmu.version < 2) in amd_pmu_cpu_reset()
552 if (!x86_pmu.amd_nb_constraints) in amd_pmu_cpu_prepare()
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Dbrs.c65 x86_pmu.lbr_nr = 16; in amd_brs_detect()
68 x86_pmu.lbr_sel_map = NULL; in amd_brs_detect()
69 x86_pmu.lbr_sel_mask = 0; in amd_brs_detect()
89 if (!x86_pmu.lbr_nr) in amd_brs_setup_filter()
151 if (event->attr.sample_period <= x86_pmu.lbr_nr) in amd_brs_hw_config()
173 return (cfg->msroff ? cfg->msroff : x86_pmu.lbr_nr) - 1; in amd_brs_get_tos()
201 pr_cont("%d-deep BRS, ", x86_pmu.lbr_nr); in amd_brs_init()
305 if (WARN_ON_ONCE(cfg.msroff >= x86_pmu.lbr_nr)) in amd_brs_drain()
Dlbr.c170 for (i = 0; i < x86_pmu.lbr_nr; i++) { in amd_pmu_lbr_read()
251 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_setup_filter()
327 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_reset()
331 for (i = 0; i < x86_pmu.lbr_nr; i++) { in amd_pmu_lbr_reset()
346 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_add()
365 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_del()
394 if (!cpuc->lbr_users || !x86_pmu.lbr_nr) in amd_pmu_lbr_enable_all()
415 if (!cpuc->lbr_users || !x86_pmu.lbr_nr) in amd_pmu_lbr_disable_all()
429 if (x86_pmu.version < 2 || !boot_cpu_has(X86_FEATURE_AMD_LBR_V2)) in amd_pmu_lbr_init()
434 x86_pmu.lbr_nr = ebx.split.lbr_v2_stack_sz; in amd_pmu_lbr_init()
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/linux-6.1.9/arch/x86/events/zhaoxin/
Dcore.c262 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
370 if (x86_pmu.enabled_ack) in zhaoxin_pmu_handle_irq()
427 if (x86_pmu.event_constraints) { in zhaoxin_get_event_constraints()
428 for_each_event_constraint(c, x86_pmu.event_constraints) { in zhaoxin_get_event_constraints()
459 static const struct x86_pmu zhaoxin_pmu __initconst = {
498 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(zx_arch_events_map)) { in zhaoxin_arch_events_quirk()
529 x86_pmu = zhaoxin_pmu; in zhaoxin_pmu_init()
532 x86_pmu.version = version; in zhaoxin_pmu_init()
533 x86_pmu.num_counters = eax.split.num_counters; in zhaoxin_pmu_init()
534 x86_pmu.cntval_bits = eax.split.bit_width; in zhaoxin_pmu_init()
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/linux-6.1.9/arch/x86/xen/
Dpmu.c508 if (x86_pmu.handle_irq(&regs)) in xen_pmu_irq_handler()