Lines Matching refs:x86_pmu
2235 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); in __intel_pmu_snapshot_branch_stack()
2511 if (left == x86_pmu.max_period) { in icl_set_topdown_event_period()
2677 x86_pmu.num_topdown_events - 1); in icl_update_topdown_event()
2752 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) in intel_pmu_enable_fixed()
2759 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { in intel_pmu_enable_fixed()
2874 if (x86_pmu.version >= 2) { in intel_pmu_reset()
2880 if (x86_pmu.lbr_nr) { in intel_pmu_reset()
2910 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || in x86_pmu_handle_guest_pebs()
2915 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) { in x86_pmu_handle_guest_pebs()
2968 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); in handle_pmi_common()
2978 x86_pmu.drain_pebs(regs, &data); in handle_pmi_common()
3154 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) in intel_alt_er()
3770 unsigned long flags = x86_pmu.large_pebs_flags; in intel_pmu_large_pebs_flags()
3787 if (!x86_pmu.bts_active) in intel_pmu_bts_config()
3819 ((x86_pmu.num_topdown_events - 1) << 8))
3839 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) in require_mem_loads_aux_event()
3878 if (x86_pmu.pebs_aliases) in intel_pmu_hw_config()
3879 x86_pmu.pebs_aliases(event); in intel_pmu_hw_config()
3991 if (x86_pmu.version < 3) in intel_pmu_hw_config()
4026 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; in intel_guest_get_msrs()
4037 if (!x86_pmu.pebs) in intel_guest_get_msrs()
4048 if (x86_pmu.pebs_no_isolation) { in intel_guest_get_msrs()
4057 if (!kvm_pmu || !x86_pmu.pebs_ept) in intel_guest_get_msrs()
4066 if (x86_pmu.intel_cap.pebs_baseline) { in intel_guest_get_msrs()
4101 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in core_guest_get_msrs()
4119 *nr = x86_pmu.num_counters; in core_guest_get_msrs()
4134 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in core_pmu_enable_all()
4441 cpuc->pebs_record_size = x86_pmu.pebs_record_size; in intel_cpuc_prepare()
4443 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { in intel_cpuc_prepare()
4449 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { in intel_cpuc_prepare()
4457 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { in intel_cpuc_prepare()
4504 if (!cpu_type && x86_pmu.get_hybrid_cpu_type) in init_hybrid_pmu()
4505 cpu_type = x86_pmu.get_hybrid_cpu_type(); in init_hybrid_pmu()
4507 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { in init_hybrid_pmu()
4508 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) { in init_hybrid_pmu()
4509 pmu = &x86_pmu.hybrid_pmu[i]; in init_hybrid_pmu()
4561 if (x86_pmu.flags & PMU_FL_TFA) { in intel_pmu_cpu_starting()
4567 if (x86_pmu.version > 1) in intel_pmu_cpu_starting()
4568 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); in intel_pmu_cpu_starting()
4579 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { in intel_pmu_cpu_starting()
4584 x86_pmu.intel_cap.perf_metrics = 0; in intel_pmu_cpu_starting()
4585 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); in intel_pmu_cpu_starting()
4592 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { in intel_pmu_cpu_starting()
4607 if (x86_pmu.lbr_sel_map) in intel_pmu_cpu_starting()
4610 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { in intel_pmu_cpu_starting()
4695 if (x86_pmu.intel_cap.pebs_output_pt_available) in intel_aux_output_init()
4696 x86_pmu.assign = intel_pmu_assign_event; in intel_aux_output_init()
4702 if (!x86_pmu.intel_cap.pebs_output_pt_available) in intel_pmu_aux_output_match()
4757 static __initconst const struct x86_pmu core_pmu = {
4805 static __initconst const struct x86_pmu intel_pmu = {
4892 x86_pmu.pebs = 0; in intel_clovertown_quirk()
4893 x86_pmu.pebs_constraints = NULL; in intel_clovertown_quirk()
4931 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); in intel_check_pebs_isolation()
4936 WARN_ON_ONCE(x86_pmu.check_microcode); in intel_pebs_isolation_quirk()
4937 x86_pmu.check_microcode = intel_check_pebs_isolation; in intel_pebs_isolation_quirk()
4955 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) in intel_snb_check_microcode()
4961 if (x86_pmu.pebs_broken) { in intel_snb_check_microcode()
4963 x86_pmu.pebs_broken = 0; in intel_snb_check_microcode()
4966 x86_pmu.pebs_broken = 1; in intel_snb_check_microcode()
4972 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; in is_lbr_from()
4974 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; in is_lbr_from()
5032 x86_pmu.check_microcode = intel_snb_check_microcode; in intel_sandybridge_quirk()
5053 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { in intel_arch_events_quirk()
5064 ebx.full = x86_pmu.events_maskl; in intel_nehalem_quirk()
5074 x86_pmu.events_maskl = ebx.full; in intel_nehalem_quirk()
5093 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; in intel_ht_bug()
5095 x86_pmu.start_scheduling = intel_start_scheduling; in intel_ht_bug()
5096 x86_pmu.commit_scheduling = intel_commit_scheduling; in intel_ht_bug()
5097 x86_pmu.stop_scheduling = intel_stop_scheduling; in intel_ht_bug()
5228 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); in freeze_on_smi_show()
5249 if (x86_pmu.attr_freeze_on_smi == val) in freeze_on_smi_store()
5252 x86_pmu.attr_freeze_on_smi = val; in freeze_on_smi_store()
5313 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); in branches_show()
5358 return x86_pmu.pebs ? attr->mode : 0; in pebs_is_visible()
5364 return x86_pmu.lbr_nr ? attr->mode : 0; in lbr_is_visible()
5370 return x86_pmu.version >= 2 ? attr->mode : 0; in exra_is_visible()
5377 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; in default_is_visible()
5697 x86_pmu.lbr_sel_map = NULL; in intel_pmu_check_extra_regs()
5706 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { in intel_pmu_check_hybrid_pmus()
5707 pmu = &x86_pmu.hybrid_pmu[i]; in intel_pmu_check_hybrid_pmus()
5769 x86_pmu = core_pmu; in intel_pmu_init()
5771 x86_pmu = intel_pmu; in intel_pmu_init()
5773 x86_pmu.version = version; in intel_pmu_init()
5774 x86_pmu.num_counters = eax.split.num_counters; in intel_pmu_init()
5775 x86_pmu.cntval_bits = eax.split.bit_width; in intel_pmu_init()
5776 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
5778 x86_pmu.events_maskl = ebx.full; in intel_pmu_init()
5779 x86_pmu.events_mask_len = eax.split.mask_length; in intel_pmu_init()
5781 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); in intel_pmu_init()
5782 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; in intel_pmu_init()
5791 x86_pmu.num_counters_fixed = in intel_pmu_init()
5794 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1; in intel_pmu_init()
5796 x86_pmu.num_counters_fixed = fls(fixed_mask); in intel_pmu_init()
5802 x86_pmu.intel_cap.capabilities = capabilities; in intel_pmu_init()
5805 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { in intel_pmu_init()
5806 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; in intel_pmu_init()
5807 x86_pmu.lbr_read = intel_pmu_lbr_read_32; in intel_pmu_init()
5818 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; in intel_pmu_init()
5819 if (x86_pmu.intel_cap.anythread_deprecated) in intel_pmu_init()
5844 x86_pmu.event_constraints = intel_core2_event_constraints; in intel_pmu_init()
5845 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; in intel_pmu_init()
5860 x86_pmu.event_constraints = intel_nehalem_event_constraints; in intel_pmu_init()
5861 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; in intel_pmu_init()
5862 x86_pmu.enable_all = intel_pmu_nhm_enable_all; in intel_pmu_init()
5863 x86_pmu.extra_regs = intel_nehalem_extra_regs; in intel_pmu_init()
5864 x86_pmu.limit_period = nhm_limit_period; in intel_pmu_init()
5877 x86_pmu.pebs_no_tlb = 1; in intel_pmu_init()
5894 x86_pmu.event_constraints = intel_gen_event_constraints; in intel_pmu_init()
5895 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; in intel_pmu_init()
5896 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; in intel_pmu_init()
5913 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
5914 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; in intel_pmu_init()
5915 x86_pmu.extra_regs = intel_slm_extra_regs; in intel_pmu_init()
5916 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
5932 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
5933 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; in intel_pmu_init()
5934 x86_pmu.extra_regs = intel_glm_extra_regs; in intel_pmu_init()
5940 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
5941 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
5942 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
5943 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
5958 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
5959 x86_pmu.extra_regs = intel_glm_extra_regs; in intel_pmu_init()
5964 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
5965 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
5966 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
5967 x86_pmu.pebs_capable = ~0ULL; in intel_pmu_init()
5968 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
5969 x86_pmu.flags |= PMU_FL_PEBS_ALL; in intel_pmu_init()
5970 x86_pmu.get_event_constraints = glp_get_event_constraints; in intel_pmu_init()
5982 x86_pmu.late_ack = true; in intel_pmu_init()
5991 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
5992 x86_pmu.extra_regs = intel_tnt_extra_regs; in intel_pmu_init()
5997 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
5998 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
5999 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
6000 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6001 x86_pmu.get_event_constraints = tnt_get_event_constraints; in intel_pmu_init()
6009 x86_pmu.mid_ack = true; in intel_pmu_init()
6016 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
6017 x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints; in intel_pmu_init()
6018 x86_pmu.extra_regs = intel_grt_extra_regs; in intel_pmu_init()
6020 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
6021 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6022 x86_pmu.pebs_block = true; in intel_pmu_init()
6023 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
6024 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6025 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; in intel_pmu_init()
6028 x86_pmu.pebs_latency_data = adl_latency_data_small; in intel_pmu_init()
6029 x86_pmu.get_event_constraints = tnt_get_event_constraints; in intel_pmu_init()
6030 x86_pmu.limit_period = spr_limit_period; in intel_pmu_init()
6048 x86_pmu.event_constraints = intel_westmere_event_constraints; in intel_pmu_init()
6049 x86_pmu.enable_all = intel_pmu_nhm_enable_all; in intel_pmu_init()
6050 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; in intel_pmu_init()
6051 x86_pmu.extra_regs = intel_westmere_extra_regs; in intel_pmu_init()
6052 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6080 x86_pmu.event_constraints = intel_snb_event_constraints; in intel_pmu_init()
6081 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; in intel_pmu_init()
6082 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
6084 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
6086 x86_pmu.extra_regs = intel_snb_extra_regs; in intel_pmu_init()
6090 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6091 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6122 x86_pmu.event_constraints = intel_ivb_event_constraints; in intel_pmu_init()
6123 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; in intel_pmu_init()
6124 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; in intel_pmu_init()
6125 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6127 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
6129 x86_pmu.extra_regs = intel_snb_extra_regs; in intel_pmu_init()
6131 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6132 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6154 x86_pmu.late_ack = true; in intel_pmu_init()
6160 x86_pmu.event_constraints = intel_hsw_event_constraints; in intel_pmu_init()
6161 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; in intel_pmu_init()
6162 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
6163 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; in intel_pmu_init()
6164 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6166 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6167 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6169 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
6170 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
6171 x86_pmu.lbr_double_abort = true; in intel_pmu_init()
6186 x86_pmu.late_ack = true; in intel_pmu_init()
6202 x86_pmu.event_constraints = intel_bdw_event_constraints; in intel_pmu_init()
6203 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; in intel_pmu_init()
6204 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
6205 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; in intel_pmu_init()
6206 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6208 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6209 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6211 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
6212 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
6213 x86_pmu.limit_period = bdw_limit_period; in intel_pmu_init()
6231 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
6232 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; in intel_pmu_init()
6233 x86_pmu.extra_regs = intel_knl_extra_regs; in intel_pmu_init()
6236 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6237 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6253 x86_pmu.late_ack = true; in intel_pmu_init()
6264 x86_pmu.event_constraints = intel_skl_event_constraints; in intel_pmu_init()
6265 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; in intel_pmu_init()
6266 x86_pmu.extra_regs = intel_skl_extra_regs; in intel_pmu_init()
6267 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; in intel_pmu_init()
6268 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6270 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6271 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6273 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
6274 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
6290 x86_pmu.flags |= PMU_FL_TFA; in intel_pmu_init()
6291 x86_pmu.get_event_constraints = tfa_get_event_constraints; in intel_pmu_init()
6292 x86_pmu.enable_all = intel_tfa_pmu_enable_all; in intel_pmu_init()
6293 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; in intel_pmu_init()
6302 x86_pmu.pebs_ept = 1; in intel_pmu_init()
6310 x86_pmu.late_ack = true; in intel_pmu_init()
6316 x86_pmu.event_constraints = intel_icl_event_constraints; in intel_pmu_init()
6317 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; in intel_pmu_init()
6318 x86_pmu.extra_regs = intel_icl_extra_regs; in intel_pmu_init()
6319 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
6320 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6321 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6322 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6324 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
6325 x86_pmu.get_event_constraints = icl_get_event_constraints; in intel_pmu_init()
6332 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init()
6333 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
6335 x86_pmu.num_topdown_events = 4; in intel_pmu_init()
6346 x86_pmu.late_ack = true; in intel_pmu_init()
6350 x86_pmu.event_constraints = intel_spr_event_constraints; in intel_pmu_init()
6351 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; in intel_pmu_init()
6352 x86_pmu.extra_regs = intel_spr_extra_regs; in intel_pmu_init()
6353 x86_pmu.limit_period = spr_limit_period; in intel_pmu_init()
6354 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
6355 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6356 x86_pmu.pebs_block = true; in intel_pmu_init()
6357 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6358 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6359 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; in intel_pmu_init()
6360 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; in intel_pmu_init()
6362 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
6363 x86_pmu.get_event_constraints = spr_get_event_constraints; in intel_pmu_init()
6370 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init()
6371 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
6373 x86_pmu.num_topdown_events = 8; in intel_pmu_init()
6392 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS, in intel_pmu_init()
6395 if (!x86_pmu.hybrid_pmu) in intel_pmu_init()
6398 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS; in intel_pmu_init()
6400 x86_pmu.pebs_aliases = NULL; in intel_pmu_init()
6401 x86_pmu.pebs_prec_dist = true; in intel_pmu_init()
6402 x86_pmu.pebs_block = true; in intel_pmu_init()
6403 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
6404 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
6405 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; in intel_pmu_init()
6406 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; in intel_pmu_init()
6407 x86_pmu.lbr_pt_coexist = true; in intel_pmu_init()
6409 x86_pmu.pebs_latency_data = adl_latency_data_small; in intel_pmu_init()
6410 x86_pmu.num_topdown_events = 8; in intel_pmu_init()
6416 x86_pmu.filter_match = intel_pmu_filter_match; in intel_pmu_init()
6417 x86_pmu.get_event_constraints = adl_get_event_constraints; in intel_pmu_init()
6418 x86_pmu.hw_config = adl_hw_config; in intel_pmu_init()
6419 x86_pmu.limit_period = spr_limit_period; in intel_pmu_init()
6420 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; in intel_pmu_init()
6427 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init()
6436 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; in intel_pmu_init()
6441 pmu->num_counters = x86_pmu.num_counters + 2; in intel_pmu_init()
6442 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1; in intel_pmu_init()
6444 pmu->num_counters = x86_pmu.num_counters; in intel_pmu_init()
6445 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; in intel_pmu_init()
6456 pmu->num_counters = x86_pmu.num_counters; in intel_pmu_init()
6457 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; in intel_pmu_init()
6464 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; in intel_pmu_init()
6475 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; in intel_pmu_init()
6479 pmu->num_counters = x86_pmu.num_counters; in intel_pmu_init()
6480 pmu->num_counters_fixed = x86_pmu.num_counters_fixed; in intel_pmu_init()
6481 pmu->max_pebs_events = x86_pmu.max_pebs_events; in intel_pmu_init()
6485 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; in intel_pmu_init()
6500 switch (x86_pmu.version) { in intel_pmu_init()
6502 x86_pmu.event_constraints = intel_v1_event_constraints; in intel_pmu_init()
6512 x86_pmu.event_constraints = intel_gen_event_constraints; in intel_pmu_init()
6524 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) in intel_pmu_init()
6525 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; in intel_pmu_init()
6526 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1; in intel_pmu_init()
6527 x86_pmu.event_constraints = intel_v5_gen_event_constraints; in intel_pmu_init()
6543 x86_pmu.attr_update = attr_update; in intel_pmu_init()
6550 x86_pmu.attr_update = hybrid_attr_update; in intel_pmu_init()
6553 intel_pmu_check_num_counters(&x86_pmu.num_counters, in intel_pmu_init()
6554 &x86_pmu.num_counters_fixed, in intel_pmu_init()
6555 &x86_pmu.intel_ctrl, in intel_pmu_init()
6559 if (x86_pmu.intel_cap.anythread_deprecated) in intel_pmu_init()
6560 x86_pmu.format_attrs = intel_arch_formats_attr; in intel_pmu_init()
6562 intel_pmu_check_event_constraints(x86_pmu.event_constraints, in intel_pmu_init()
6563 x86_pmu.num_counters, in intel_pmu_init()
6564 x86_pmu.num_counters_fixed, in intel_pmu_init()
6565 x86_pmu.intel_ctrl); in intel_pmu_init()
6571 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) in intel_pmu_init()
6572 x86_pmu.lbr_nr = 0; in intel_pmu_init()
6573 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_init()
6574 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && in intel_pmu_init()
6575 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) in intel_pmu_init()
6576 x86_pmu.lbr_nr = 0; in intel_pmu_init()
6579 if (x86_pmu.lbr_nr) { in intel_pmu_init()
6582 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); in intel_pmu_init()
6585 if (x86_pmu.disable_all == intel_pmu_disable_all) { in intel_pmu_init()
6596 intel_pmu_check_extra_regs(x86_pmu.extra_regs); in intel_pmu_init()
6599 if (x86_pmu.intel_cap.full_width_write) { in intel_pmu_init()
6600 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
6601 x86_pmu.perfctr = MSR_IA32_PMC0; in intel_pmu_init()
6605 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) in intel_pmu_init()
6606 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; in intel_pmu_init()
6628 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) in fixup_ht_bug()
6640 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); in fixup_ht_bug()
6642 x86_pmu.start_scheduling = NULL; in fixup_ht_bug()
6643 x86_pmu.commit_scheduling = NULL; in fixup_ht_bug()
6644 x86_pmu.stop_scheduling = NULL; in fixup_ht_bug()