Lines Matching refs:x86_pmu
129 if (pmi && x86_pmu.version >= 4) in __intel_pmu_lbr_enable()
137 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; in __intel_pmu_lbr_enable()
167 for (i = 0; i < x86_pmu.lbr_nr; i++) in intel_pmu_lbr_reset_32()
168 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
175 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_reset_64()
176 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
177 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
178 if (x86_pmu.lbr_has_info) in intel_pmu_lbr_reset_64()
179 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
186 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
193 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_reset()
196 x86_pmu.lbr_reset(); in intel_pmu_lbr_reset()
211 rdmsrl(x86_pmu.lbr_tos, tos); in intel_pmu_lbr_tos()
284 wrmsrl(x86_pmu.lbr_from + idx, val); in wrlbr_from()
289 wrmsrl(x86_pmu.lbr_to + idx, val); in wrlbr_to()
294 wrmsrl(x86_pmu.lbr_info + idx, val); in wrlbr_info()
304 rdmsrl(x86_pmu.lbr_from + idx, val); in rdlbr_from()
316 rdmsrl(x86_pmu.lbr_to + idx, val); in rdlbr_to()
328 rdmsrl(x86_pmu.lbr_info + idx, val); in rdlbr_info()
363 bool need_info = x86_pmu.lbr_has_info; in intel_pmu_lbr_restore()
368 mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_restore()
374 for (; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_restore()
382 wrmsrl(x86_pmu.lbr_tos, tos); in intel_pmu_lbr_restore()
395 if (!entries[x86_pmu.lbr_nr - 1].from) in intel_pmu_arch_lbr_restore()
398 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_arch_lbr_restore()
419 return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL); in lbr_is_reset_in_cstate()
446 x86_pmu.lbr_restore(ctx); in __intel_pmu_lbr_restore()
455 bool need_info = x86_pmu.lbr_has_info; in intel_pmu_lbr_save()
460 mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_save()
462 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_save()
480 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_arch_lbr_save()
486 if (i < x86_pmu.lbr_nr) in intel_pmu_arch_lbr_save()
487 entries[x86_pmu.lbr_nr - 1].from = 0; in intel_pmu_arch_lbr_save()
510 x86_pmu.lbr_save(ctx); in __intel_pmu_lbr_save()
582 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_add()
612 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) in intel_pmu_lbr_add()
663 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_del()
673 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) in intel_pmu_lbr_del()
711 unsigned long mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_read_32()
716 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_read_32()
726 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); in intel_pmu_lbr_read_32()
746 unsigned long mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_read_64()
751 int num = x86_pmu.lbr_nr; in intel_pmu_lbr_read_64()
774 if (x86_pmu.lbr_has_info) { in intel_pmu_lbr_read_64()
782 if (x86_pmu.lbr_has_tsx) { in intel_pmu_lbr_read_64()
790 if (x86_pmu.lbr_from_flags) { in intel_pmu_lbr_read_64()
795 if (x86_pmu.lbr_has_tsx) { in intel_pmu_lbr_read_64()
802 if (x86_pmu.lbr_to_cycles) { in intel_pmu_lbr_read_64()
816 if (abort && x86_pmu.lbr_double_abort && out > 0) in intel_pmu_lbr_read_64()
877 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_store_lbr()
938 x86_pmu.lbr_read(cpuc); in intel_pmu_lbr_read()
1027 v = x86_pmu.lbr_sel_map[i]; in intel_pmu_setup_hw_lbr_filter()
1058 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); in intel_pmu_setup_hw_lbr_filter()
1062 x86_pmu.lbr_has_info) in intel_pmu_setup_hw_lbr_filter()
1075 if (!x86_pmu.lbr_nr) in intel_pmu_setup_lbr_filter()
1088 if (x86_pmu.lbr_sel_map) in intel_pmu_setup_lbr_filter()
1277 x86_pmu.lbr_nr = 4; in intel_pmu_lbr_init_core()
1278 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_core()
1279 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; in intel_pmu_lbr_init_core()
1280 x86_pmu.lbr_to = MSR_LBR_CORE_TO; in intel_pmu_lbr_init_core()
1291 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_nhm()
1292 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_nhm()
1293 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_nhm()
1294 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_nhm()
1296 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_nhm()
1297 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; in intel_pmu_lbr_init_nhm()
1311 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_snb()
1312 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_snb()
1313 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_snb()
1314 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_snb()
1316 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_snb()
1317 x86_pmu.lbr_sel_map = snb_lbr_sel_map; in intel_pmu_lbr_init_snb()
1338 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_hsw()
1339 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_hsw()
1340 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_hsw()
1341 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_hsw()
1343 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_hsw()
1344 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; in intel_pmu_lbr_init_hsw()
1354 x86_pmu.lbr_nr = 32; in intel_pmu_lbr_init_skl()
1355 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_skl()
1356 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_skl()
1357 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_skl()
1358 x86_pmu.lbr_info = MSR_LBR_INFO_0; in intel_pmu_lbr_init_skl()
1360 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_skl()
1361 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; in intel_pmu_lbr_init_skl()
1387 x86_pmu.lbr_nr = 8; in intel_pmu_lbr_init_atom()
1388 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_atom()
1389 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; in intel_pmu_lbr_init_atom()
1390 x86_pmu.lbr_to = MSR_LBR_CORE_TO; in intel_pmu_lbr_init_atom()
1401 x86_pmu.lbr_nr = 8; in intel_pmu_lbr_init_slm()
1402 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_slm()
1403 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; in intel_pmu_lbr_init_slm()
1404 x86_pmu.lbr_to = MSR_LBR_CORE_TO; in intel_pmu_lbr_init_slm()
1406 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_slm()
1407 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; in intel_pmu_lbr_init_slm()
1419 x86_pmu.lbr_nr = 8; in intel_pmu_lbr_init_knl()
1420 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_knl()
1421 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_knl()
1422 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_knl()
1424 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_knl()
1425 x86_pmu.lbr_sel_map = snb_lbr_sel_map; in intel_pmu_lbr_init_knl()
1428 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP) in intel_pmu_lbr_init_knl()
1429 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS; in intel_pmu_lbr_init_knl()
1434 switch (x86_pmu.intel_cap.lbr_format) { in intel_pmu_lbr_init()
1436 x86_pmu.lbr_has_tsx = 1; in intel_pmu_lbr_init()
1437 x86_pmu.lbr_from_flags = 1; in intel_pmu_lbr_init()
1443 x86_pmu.lbr_from_flags = 1; in intel_pmu_lbr_init()
1447 x86_pmu.lbr_has_tsx = 1; in intel_pmu_lbr_init()
1450 x86_pmu.lbr_has_info = 1; in intel_pmu_lbr_init()
1454 x86_pmu.lbr_from_flags = 1; in intel_pmu_lbr_init()
1455 x86_pmu.lbr_to_cycles = 1; in intel_pmu_lbr_init()
1459 if (x86_pmu.lbr_has_info) { in intel_pmu_lbr_init()
1476 x86_pmu.lbr_nr * sizeof(struct lbr_entry); in get_lbr_state_size()
1519 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask; in intel_pmu_arch_lbr_init()
1520 x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset; in intel_pmu_arch_lbr_init()
1521 x86_pmu.lbr_lip = eax.split.lbr_lip; in intel_pmu_arch_lbr_init()
1522 x86_pmu.lbr_cpl = ebx.split.lbr_cpl; in intel_pmu_arch_lbr_init()
1523 x86_pmu.lbr_filter = ebx.split.lbr_filter; in intel_pmu_arch_lbr_init()
1524 x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack; in intel_pmu_arch_lbr_init()
1525 x86_pmu.lbr_mispred = ecx.split.lbr_mispred; in intel_pmu_arch_lbr_init()
1526 x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr; in intel_pmu_arch_lbr_init()
1527 x86_pmu.lbr_br_type = ecx.split.lbr_br_type; in intel_pmu_arch_lbr_init()
1528 x86_pmu.lbr_nr = lbr_nr; in intel_pmu_arch_lbr_init()
1530 if (x86_pmu.lbr_mispred) in intel_pmu_arch_lbr_init()
1532 if (x86_pmu.lbr_timed_lbr) in intel_pmu_arch_lbr_init()
1534 if (x86_pmu.lbr_br_type) in intel_pmu_arch_lbr_init()
1553 x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0; in intel_pmu_arch_lbr_init()
1554 x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0; in intel_pmu_arch_lbr_init()
1555 x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0; in intel_pmu_arch_lbr_init()
1558 if (!x86_pmu.lbr_cpl || in intel_pmu_arch_lbr_init()
1559 !x86_pmu.lbr_filter || in intel_pmu_arch_lbr_init()
1560 !x86_pmu.lbr_call_stack) in intel_pmu_arch_lbr_init()
1563 if (!x86_pmu.lbr_cpl) { in intel_pmu_arch_lbr_init()
1566 } else if (!x86_pmu.lbr_filter) { in intel_pmu_arch_lbr_init()
1576 x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK; in intel_pmu_arch_lbr_init()
1577 x86_pmu.lbr_ctl_map = arch_lbr_ctl_map; in intel_pmu_arch_lbr_init()
1579 if (!x86_pmu.lbr_cpl && !x86_pmu.lbr_filter) in intel_pmu_arch_lbr_init()
1580 x86_pmu.lbr_ctl_map = NULL; in intel_pmu_arch_lbr_init()
1582 x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset; in intel_pmu_arch_lbr_init()
1584 x86_pmu.lbr_save = intel_pmu_arch_lbr_xsaves; in intel_pmu_arch_lbr_init()
1585 x86_pmu.lbr_restore = intel_pmu_arch_lbr_xrstors; in intel_pmu_arch_lbr_init()
1586 x86_pmu.lbr_read = intel_pmu_arch_lbr_read_xsave; in intel_pmu_arch_lbr_init()
1589 x86_pmu.lbr_save = intel_pmu_arch_lbr_save; in intel_pmu_arch_lbr_init()
1590 x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore; in intel_pmu_arch_lbr_init()
1591 x86_pmu.lbr_read = intel_pmu_arch_lbr_read; in intel_pmu_arch_lbr_init()
1611 int lbr_fmt = x86_pmu.intel_cap.lbr_format; in x86_perf_get_lbr()
1613 lbr->nr = x86_pmu.lbr_nr; in x86_perf_get_lbr()
1614 lbr->from = x86_pmu.lbr_from; in x86_perf_get_lbr()
1615 lbr->to = x86_pmu.lbr_to; in x86_perf_get_lbr()
1616 lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; in x86_perf_get_lbr()