262 	wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);  in zhaoxin_pmu_enable_all()
370 	if (x86_pmu.enabled_ack)  in zhaoxin_pmu_handle_irq()
427 	if (x86_pmu.event_constraints) {  in zhaoxin_get_event_constraints()
428 		for_each_event_constraint(c, x86_pmu.event_constraints) {  in zhaoxin_get_event_constraints()
459 static const struct x86_pmu zhaoxin_pmu __initconst = {
498 	for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(zx_arch_events_map)) {  in zhaoxin_arch_events_quirk()
529 	x86_pmu = zhaoxin_pmu;  in zhaoxin_pmu_init()
532 	x86_pmu.version			= version;  in zhaoxin_pmu_init()
533 	x86_pmu.num_counters		= eax.split.num_counters;  in zhaoxin_pmu_init()
534 	x86_pmu.cntval_bits		= eax.split.bit_width;  in zhaoxin_pmu_init()
535 	x86_pmu.cntval_mask		= (1ULL << eax.split.bit_width) - 1;  in zhaoxin_pmu_init()
536 	x86_pmu.events_maskl		= ebx.full;  in zhaoxin_pmu_init()
537 	x86_pmu.events_mask_len		= eax.split.mask_length;  in zhaoxin_pmu_init()
539 	x86_pmu.num_counters_fixed = edx.split.num_counters_fixed;  in zhaoxin_pmu_init()
546 			x86_pmu.max_period = x86_pmu.cntval_mask >> 1;  in zhaoxin_pmu_init()
549 			x86_pmu.enabled_ack = 1;  in zhaoxin_pmu_init()
551 			x86_pmu.event_constraints = zxc_event_constraints;  in zhaoxin_pmu_init()
574 			x86_pmu.event_constraints = zxd_event_constraints;  in zhaoxin_pmu_init()
585 			x86_pmu.event_constraints = zxd_event_constraints;  in zhaoxin_pmu_init()
601 	x86_pmu.intel_ctrl = (1 << (x86_pmu.num_counters)) - 1;  in zhaoxin_pmu_init()
602 	x86_pmu.intel_ctrl |= ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;  in zhaoxin_pmu_init()
604 	if (x86_pmu.event_constraints) {  in zhaoxin_pmu_init()
605 		for_each_event_constraint(c, x86_pmu.event_constraints) {  in zhaoxin_pmu_init()
606 			c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;  in zhaoxin_pmu_init()
607 			c->weight += x86_pmu.num_counters;  in zhaoxin_pmu_init()