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Searched refs:radeon_get_ib_value (Results 1 – 7 of 7) sorted by relevance

/linux-3.4.99/drivers/gpu/drm/radeon/
Devergreen_cs.c751 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
752 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
753 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
754 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
755 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
756 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
757 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
758 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1004 header = radeon_get_ib_value(p, idx); in evergreen_cs_packet_parse()
1066 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in evergreen_cs_packet_next_reloc()
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Dr600_cs.c800 header = radeon_get_ib_value(p, idx); in r600_cs_packet_parse()
862 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in r600_cs_packet_next_reloc_mm()
908 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in r600_cs_packet_next_reloc_nomm()
981 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_packet_parse_vline()
992 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { in r600_cs_packet_parse_vline()
997 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { in r600_cs_packet_parse_vline()
1011 header = radeon_get_ib_value(p, h_idx); in r600_cs_packet_parse_vline()
1012 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in r600_cs_packet_parse_vline()
1140 tmp =radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1144 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
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Dr300.c632 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
1188 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r300_packet3_check()
1199 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { in r300_packet3_check()
1203 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1214 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { in r300_packet3_check()
1218 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1226 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1233 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1240 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1247 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
Dr100.c125 value = radeon_get_ib_value(p, idx); in r100_reloc_pitch_offset()
161 c = radeon_get_ib_value(p, idx++) & 0x1F; in r100_packet3_load_vbpntr()
177 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
190 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
203 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
204 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1301 header = radeon_get_ib_value(p, idx); in r100_cs_packet_parse()
1367 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { in r100_cs_packet_parse_vline()
1381 header = radeon_get_ib_value(p, h_idx); in r100_cs_packet_parse_vline()
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Dr200.c159 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
Dradeon_ring.c39 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) in radeon_get_ib_value() function
Dradeon.h850 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);