Lines Matching refs:radeon_get_ib_value
751 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
752 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
753 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
754 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
755 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
756 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
757 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
758 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1004 header = radeon_get_ib_value(p, idx); in evergreen_cs_packet_parse()
1066 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in evergreen_cs_packet_next_reloc()
1116 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in evergreen_cs_packet_parse_vline()
1127 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) { in evergreen_cs_packet_parse_vline()
1132 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) { in evergreen_cs_packet_parse_vline()
1146 header = radeon_get_ib_value(p, h_idx); in evergreen_cs_packet_parse_vline()
1147 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in evergreen_cs_packet_parse_vline()
1311 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1329 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1357 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1361 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1365 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1369 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1379 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1391 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1403 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1415 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1421 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1425 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1439 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_check_reg()
1450 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_check_reg()
1462 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1466 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1475 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_check_reg()
1484 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_check_reg()
1496 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1504 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1516 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1534 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1556 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1564 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1576 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1585 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1692 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1703 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1720 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1736 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1748 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1755 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1895 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_check_reg()
1945 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1959 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
2025 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2052 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2079 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
2080 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2191 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2192 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2204 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2205 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2228 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2229 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2250 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2251 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2272 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2273 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2329 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2379 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2380 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2461 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2462 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2480 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2481 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2505 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2506 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2517 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2529 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2530 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2541 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()