1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "evergreend.h"
31 #include "evergreen_reg_safe.h"
32 #include "cayman_reg_safe.h"
33 
34 #define MAX(a,b)                   (((a)>(b))?(a):(b))
35 #define MIN(a,b)                   (((a)<(b))?(a):(b))
36 
37 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
38 					  struct radeon_cs_reloc **cs_reloc);
39 
40 struct evergreen_cs_track {
41 	u32			group_size;
42 	u32			nbanks;
43 	u32			npipes;
44 	u32			row_size;
45 	/* value we track */
46 	u32			nsamples;		/* unused */
47 	struct radeon_bo	*cb_color_bo[12];
48 	u32			cb_color_bo_offset[12];
49 	struct radeon_bo	*cb_color_fmask_bo[8];	/* unused */
50 	struct radeon_bo	*cb_color_cmask_bo[8];	/* unused */
51 	u32			cb_color_info[12];
52 	u32			cb_color_view[12];
53 	u32			cb_color_pitch[12];
54 	u32			cb_color_slice[12];
55 	u32			cb_color_slice_idx[12];
56 	u32			cb_color_attrib[12];
57 	u32			cb_color_cmask_slice[8];/* unused */
58 	u32			cb_color_fmask_slice[8];/* unused */
59 	u32			cb_target_mask;
60 	u32			cb_shader_mask; /* unused */
61 	u32			vgt_strmout_config;
62 	u32			vgt_strmout_buffer_config;
63 	struct radeon_bo	*vgt_strmout_bo[4];
64 	u32			vgt_strmout_bo_offset[4];
65 	u32			vgt_strmout_size[4];
66 	u32			db_depth_control;
67 	u32			db_depth_view;
68 	u32			db_depth_slice;
69 	u32			db_depth_size;
70 	u32			db_z_info;
71 	u32			db_z_read_offset;
72 	u32			db_z_write_offset;
73 	struct radeon_bo	*db_z_read_bo;
74 	struct radeon_bo	*db_z_write_bo;
75 	u32			db_s_info;
76 	u32			db_s_read_offset;
77 	u32			db_s_write_offset;
78 	struct radeon_bo	*db_s_read_bo;
79 	struct radeon_bo	*db_s_write_bo;
80 	bool			sx_misc_kill_all_prims;
81 	bool			cb_dirty;
82 	bool			db_dirty;
83 	bool			streamout_dirty;
84 	u32			htile_offset;
85 	u32			htile_surface;
86 	struct radeon_bo	*htile_bo;
87 };
88 
evergreen_cs_get_aray_mode(u32 tiling_flags)89 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
90 {
91 	if (tiling_flags & RADEON_TILING_MACRO)
92 		return ARRAY_2D_TILED_THIN1;
93 	else if (tiling_flags & RADEON_TILING_MICRO)
94 		return ARRAY_1D_TILED_THIN1;
95 	else
96 		return ARRAY_LINEAR_GENERAL;
97 }
98 
evergreen_cs_get_num_banks(u32 nbanks)99 static u32 evergreen_cs_get_num_banks(u32 nbanks)
100 {
101 	switch (nbanks) {
102 	case 2:
103 		return ADDR_SURF_2_BANK;
104 	case 4:
105 		return ADDR_SURF_4_BANK;
106 	case 8:
107 	default:
108 		return ADDR_SURF_8_BANK;
109 	case 16:
110 		return ADDR_SURF_16_BANK;
111 	}
112 }
113 
evergreen_cs_track_init(struct evergreen_cs_track * track)114 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
115 {
116 	int i;
117 
118 	for (i = 0; i < 8; i++) {
119 		track->cb_color_fmask_bo[i] = NULL;
120 		track->cb_color_cmask_bo[i] = NULL;
121 		track->cb_color_cmask_slice[i] = 0;
122 		track->cb_color_fmask_slice[i] = 0;
123 	}
124 
125 	for (i = 0; i < 12; i++) {
126 		track->cb_color_bo[i] = NULL;
127 		track->cb_color_bo_offset[i] = 0xFFFFFFFF;
128 		track->cb_color_info[i] = 0;
129 		track->cb_color_view[i] = 0xFFFFFFFF;
130 		track->cb_color_pitch[i] = 0;
131 		track->cb_color_slice[i] = 0xfffffff;
132 		track->cb_color_slice_idx[i] = 0;
133 	}
134 	track->cb_target_mask = 0xFFFFFFFF;
135 	track->cb_shader_mask = 0xFFFFFFFF;
136 	track->cb_dirty = true;
137 
138 	track->db_depth_slice = 0xffffffff;
139 	track->db_depth_view = 0xFFFFC000;
140 	track->db_depth_size = 0xFFFFFFFF;
141 	track->db_depth_control = 0xFFFFFFFF;
142 	track->db_z_info = 0xFFFFFFFF;
143 	track->db_z_read_offset = 0xFFFFFFFF;
144 	track->db_z_write_offset = 0xFFFFFFFF;
145 	track->db_z_read_bo = NULL;
146 	track->db_z_write_bo = NULL;
147 	track->db_s_info = 0xFFFFFFFF;
148 	track->db_s_read_offset = 0xFFFFFFFF;
149 	track->db_s_write_offset = 0xFFFFFFFF;
150 	track->db_s_read_bo = NULL;
151 	track->db_s_write_bo = NULL;
152 	track->db_dirty = true;
153 	track->htile_bo = NULL;
154 	track->htile_offset = 0xFFFFFFFF;
155 	track->htile_surface = 0;
156 
157 	for (i = 0; i < 4; i++) {
158 		track->vgt_strmout_size[i] = 0;
159 		track->vgt_strmout_bo[i] = NULL;
160 		track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
161 	}
162 	track->streamout_dirty = true;
163 	track->sx_misc_kill_all_prims = false;
164 }
165 
166 struct eg_surface {
167 	/* value gathered from cs */
168 	unsigned	nbx;
169 	unsigned	nby;
170 	unsigned	format;
171 	unsigned	mode;
172 	unsigned	nbanks;
173 	unsigned	bankw;
174 	unsigned	bankh;
175 	unsigned	tsplit;
176 	unsigned	mtilea;
177 	unsigned	nsamples;
178 	/* output value */
179 	unsigned	bpe;
180 	unsigned	layer_size;
181 	unsigned	palign;
182 	unsigned	halign;
183 	unsigned long	base_align;
184 };
185 
evergreen_surface_check_linear(struct radeon_cs_parser * p,struct eg_surface * surf,const char * prefix)186 static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
187 					  struct eg_surface *surf,
188 					  const char *prefix)
189 {
190 	surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
191 	surf->base_align = surf->bpe;
192 	surf->palign = 1;
193 	surf->halign = 1;
194 	return 0;
195 }
196 
evergreen_surface_check_linear_aligned(struct radeon_cs_parser * p,struct eg_surface * surf,const char * prefix)197 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
198 						  struct eg_surface *surf,
199 						  const char *prefix)
200 {
201 	struct evergreen_cs_track *track = p->track;
202 	unsigned palign;
203 
204 	palign = MAX(64, track->group_size / surf->bpe);
205 	surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
206 	surf->base_align = track->group_size;
207 	surf->palign = palign;
208 	surf->halign = 1;
209 	if (surf->nbx & (palign - 1)) {
210 		if (prefix) {
211 			dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
212 				 __func__, __LINE__, prefix, surf->nbx, palign);
213 		}
214 		return -EINVAL;
215 	}
216 	return 0;
217 }
218 
evergreen_surface_check_1d(struct radeon_cs_parser * p,struct eg_surface * surf,const char * prefix)219 static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
220 				      struct eg_surface *surf,
221 				      const char *prefix)
222 {
223 	struct evergreen_cs_track *track = p->track;
224 	unsigned palign;
225 
226 	palign = track->group_size / (8 * surf->bpe * surf->nsamples);
227 	palign = MAX(8, palign);
228 	surf->layer_size = surf->nbx * surf->nby * surf->bpe;
229 	surf->base_align = track->group_size;
230 	surf->palign = palign;
231 	surf->halign = 8;
232 	if ((surf->nbx & (palign - 1))) {
233 		if (prefix) {
234 			dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
235 				 __func__, __LINE__, prefix, surf->nbx, palign,
236 				 track->group_size, surf->bpe, surf->nsamples);
237 		}
238 		return -EINVAL;
239 	}
240 	if ((surf->nby & (8 - 1))) {
241 		if (prefix) {
242 			dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
243 				 __func__, __LINE__, prefix, surf->nby);
244 		}
245 		return -EINVAL;
246 	}
247 	return 0;
248 }
249 
evergreen_surface_check_2d(struct radeon_cs_parser * p,struct eg_surface * surf,const char * prefix)250 static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
251 				      struct eg_surface *surf,
252 				      const char *prefix)
253 {
254 	struct evergreen_cs_track *track = p->track;
255 	unsigned palign, halign, tileb, slice_pt;
256 	unsigned mtile_pr, mtile_ps, mtileb;
257 
258 	tileb = 64 * surf->bpe * surf->nsamples;
259 	slice_pt = 1;
260 	if (tileb > surf->tsplit) {
261 		slice_pt = tileb / surf->tsplit;
262 	}
263 	tileb = tileb / slice_pt;
264 	/* macro tile width & height */
265 	palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
266 	halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
267 	mtileb = (palign / 8) * (halign / 8) * tileb;;
268 	mtile_pr = surf->nbx / palign;
269 	mtile_ps = (mtile_pr * surf->nby) / halign;
270 	surf->layer_size = mtile_ps * mtileb * slice_pt;
271 	surf->base_align = (palign / 8) * (halign / 8) * tileb;
272 	surf->palign = palign;
273 	surf->halign = halign;
274 
275 	if ((surf->nbx & (palign - 1))) {
276 		if (prefix) {
277 			dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
278 				 __func__, __LINE__, prefix, surf->nbx, palign);
279 		}
280 		return -EINVAL;
281 	}
282 	if ((surf->nby & (halign - 1))) {
283 		if (prefix) {
284 			dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
285 				 __func__, __LINE__, prefix, surf->nby, halign);
286 		}
287 		return -EINVAL;
288 	}
289 
290 	return 0;
291 }
292 
evergreen_surface_check(struct radeon_cs_parser * p,struct eg_surface * surf,const char * prefix)293 static int evergreen_surface_check(struct radeon_cs_parser *p,
294 				   struct eg_surface *surf,
295 				   const char *prefix)
296 {
297 	/* some common value computed here */
298 	surf->bpe = r600_fmt_get_blocksize(surf->format);
299 
300 	switch (surf->mode) {
301 	case ARRAY_LINEAR_GENERAL:
302 		return evergreen_surface_check_linear(p, surf, prefix);
303 	case ARRAY_LINEAR_ALIGNED:
304 		return evergreen_surface_check_linear_aligned(p, surf, prefix);
305 	case ARRAY_1D_TILED_THIN1:
306 		return evergreen_surface_check_1d(p, surf, prefix);
307 	case ARRAY_2D_TILED_THIN1:
308 		return evergreen_surface_check_2d(p, surf, prefix);
309 	default:
310 		dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
311 				__func__, __LINE__, prefix, surf->mode);
312 		return -EINVAL;
313 	}
314 	return -EINVAL;
315 }
316 
evergreen_surface_value_conv_check(struct radeon_cs_parser * p,struct eg_surface * surf,const char * prefix)317 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
318 					      struct eg_surface *surf,
319 					      const char *prefix)
320 {
321 	switch (surf->mode) {
322 	case ARRAY_2D_TILED_THIN1:
323 		break;
324 	case ARRAY_LINEAR_GENERAL:
325 	case ARRAY_LINEAR_ALIGNED:
326 	case ARRAY_1D_TILED_THIN1:
327 		return 0;
328 	default:
329 		dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
330 				__func__, __LINE__, prefix, surf->mode);
331 		return -EINVAL;
332 	}
333 
334 	switch (surf->nbanks) {
335 	case 0: surf->nbanks = 2; break;
336 	case 1: surf->nbanks = 4; break;
337 	case 2: surf->nbanks = 8; break;
338 	case 3: surf->nbanks = 16; break;
339 	default:
340 		dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
341 			 __func__, __LINE__, prefix, surf->nbanks);
342 		return -EINVAL;
343 	}
344 	switch (surf->bankw) {
345 	case 0: surf->bankw = 1; break;
346 	case 1: surf->bankw = 2; break;
347 	case 2: surf->bankw = 4; break;
348 	case 3: surf->bankw = 8; break;
349 	default:
350 		dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
351 			 __func__, __LINE__, prefix, surf->bankw);
352 		return -EINVAL;
353 	}
354 	switch (surf->bankh) {
355 	case 0: surf->bankh = 1; break;
356 	case 1: surf->bankh = 2; break;
357 	case 2: surf->bankh = 4; break;
358 	case 3: surf->bankh = 8; break;
359 	default:
360 		dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
361 			 __func__, __LINE__, prefix, surf->bankh);
362 		return -EINVAL;
363 	}
364 	switch (surf->mtilea) {
365 	case 0: surf->mtilea = 1; break;
366 	case 1: surf->mtilea = 2; break;
367 	case 2: surf->mtilea = 4; break;
368 	case 3: surf->mtilea = 8; break;
369 	default:
370 		dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
371 			 __func__, __LINE__, prefix, surf->mtilea);
372 		return -EINVAL;
373 	}
374 	switch (surf->tsplit) {
375 	case 0: surf->tsplit = 64; break;
376 	case 1: surf->tsplit = 128; break;
377 	case 2: surf->tsplit = 256; break;
378 	case 3: surf->tsplit = 512; break;
379 	case 4: surf->tsplit = 1024; break;
380 	case 5: surf->tsplit = 2048; break;
381 	case 6: surf->tsplit = 4096; break;
382 	default:
383 		dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
384 			 __func__, __LINE__, prefix, surf->tsplit);
385 		return -EINVAL;
386 	}
387 	return 0;
388 }
389 
evergreen_cs_track_validate_cb(struct radeon_cs_parser * p,unsigned id)390 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
391 {
392 	struct evergreen_cs_track *track = p->track;
393 	struct eg_surface surf;
394 	unsigned pitch, slice, mslice;
395 	unsigned long offset;
396 	int r;
397 
398 	mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
399 	pitch = track->cb_color_pitch[id];
400 	slice = track->cb_color_slice[id];
401 	surf.nbx = (pitch + 1) * 8;
402 	surf.nby = ((slice + 1) * 64) / surf.nbx;
403 	surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
404 	surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
405 	surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
406 	surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
407 	surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
408 	surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
409 	surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
410 	surf.nsamples = 1;
411 
412 	if (!r600_fmt_is_valid_color(surf.format)) {
413 		dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
414 			 __func__, __LINE__, surf.format,
415 			id, track->cb_color_info[id]);
416 		return -EINVAL;
417 	}
418 
419 	r = evergreen_surface_value_conv_check(p, &surf, "cb");
420 	if (r) {
421 		return r;
422 	}
423 
424 	r = evergreen_surface_check(p, &surf, "cb");
425 	if (r) {
426 		dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
427 			 __func__, __LINE__, id, track->cb_color_pitch[id],
428 			 track->cb_color_slice[id], track->cb_color_attrib[id],
429 			 track->cb_color_info[id]);
430 		return r;
431 	}
432 
433 	offset = track->cb_color_bo_offset[id] << 8;
434 	if (offset & (surf.base_align - 1)) {
435 		dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
436 			 __func__, __LINE__, id, offset, surf.base_align);
437 		return -EINVAL;
438 	}
439 
440 	offset += surf.layer_size * mslice;
441 	if (offset > radeon_bo_size(track->cb_color_bo[id])) {
442 		/* old ddx are broken they allocate bo with w*h*bpp but
443 		 * program slice with ALIGN(h, 8), catch this and patch
444 		 * command stream.
445 		 */
446 		if (!surf.mode) {
447 			volatile u32 *ib = p->ib->ptr;
448 			unsigned long tmp, nby, bsize, size, min = 0;
449 
450 			/* find the height the ddx wants */
451 			if (surf.nby > 8) {
452 				min = surf.nby - 8;
453 			}
454 			bsize = radeon_bo_size(track->cb_color_bo[id]);
455 			tmp = track->cb_color_bo_offset[id] << 8;
456 			for (nby = surf.nby; nby > min; nby--) {
457 				size = nby * surf.nbx * surf.bpe * surf.nsamples;
458 				if ((tmp + size * mslice) <= bsize) {
459 					break;
460 				}
461 			}
462 			if (nby > min) {
463 				surf.nby = nby;
464 				slice = ((nby * surf.nbx) / 64) - 1;
465 				if (!evergreen_surface_check(p, &surf, "cb")) {
466 					/* check if this one works */
467 					tmp += surf.layer_size * mslice;
468 					if (tmp <= bsize) {
469 						ib[track->cb_color_slice_idx[id]] = slice;
470 						goto old_ddx_ok;
471 					}
472 				}
473 			}
474 		}
475 		dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
476 			 "offset %d, max layer %d, bo size %ld, slice %d)\n",
477 			 __func__, __LINE__, id, surf.layer_size,
478 			track->cb_color_bo_offset[id] << 8, mslice,
479 			radeon_bo_size(track->cb_color_bo[id]), slice);
480 		dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
481 			 __func__, __LINE__, surf.nbx, surf.nby,
482 			surf.mode, surf.bpe, surf.nsamples,
483 			surf.bankw, surf.bankh,
484 			surf.tsplit, surf.mtilea);
485 		return -EINVAL;
486 	}
487 old_ddx_ok:
488 
489 	return 0;
490 }
491 
evergreen_cs_track_validate_htile(struct radeon_cs_parser * p,unsigned nbx,unsigned nby)492 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
493 						unsigned nbx, unsigned nby)
494 {
495 	struct evergreen_cs_track *track = p->track;
496 	unsigned long size;
497 
498 	if (track->htile_bo == NULL) {
499 		dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
500 				__func__, __LINE__, track->db_z_info);
501 		return -EINVAL;
502 	}
503 
504 	if (G_028ABC_LINEAR(track->htile_surface)) {
505 		/* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
506 		nbx = round_up(nbx, 16 * 8);
507 		/* height is npipes htiles aligned == npipes * 8 pixel aligned */
508 		nby = round_up(nby, track->npipes * 8);
509 	} else {
510 		switch (track->npipes) {
511 		case 8:
512 			nbx = round_up(nbx, 64 * 8);
513 			nby = round_up(nby, 64 * 8);
514 			break;
515 		case 4:
516 			nbx = round_up(nbx, 64 * 8);
517 			nby = round_up(nby, 32 * 8);
518 			break;
519 		case 2:
520 			nbx = round_up(nbx, 32 * 8);
521 			nby = round_up(nby, 32 * 8);
522 			break;
523 		case 1:
524 			nbx = round_up(nbx, 32 * 8);
525 			nby = round_up(nby, 16 * 8);
526 			break;
527 		default:
528 			dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
529 					__func__, __LINE__, track->npipes);
530 			return -EINVAL;
531 		}
532 	}
533 	/* compute number of htile */
534 	nbx = nbx / 8;
535 	nby = nby / 8;
536 	size = nbx * nby * 4;
537 	size += track->htile_offset;
538 
539 	if (size > radeon_bo_size(track->htile_bo)) {
540 		dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
541 				__func__, __LINE__, radeon_bo_size(track->htile_bo),
542 				size, nbx, nby);
543 		return -EINVAL;
544 	}
545 	return 0;
546 }
547 
evergreen_cs_track_validate_stencil(struct radeon_cs_parser * p)548 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
549 {
550 	struct evergreen_cs_track *track = p->track;
551 	struct eg_surface surf;
552 	unsigned pitch, slice, mslice;
553 	unsigned long offset;
554 	int r;
555 
556 	mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
557 	pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
558 	slice = track->db_depth_slice;
559 	surf.nbx = (pitch + 1) * 8;
560 	surf.nby = ((slice + 1) * 64) / surf.nbx;
561 	surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
562 	surf.format = G_028044_FORMAT(track->db_s_info);
563 	surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
564 	surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
565 	surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
566 	surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
567 	surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
568 	surf.nsamples = 1;
569 
570 	if (surf.format != 1) {
571 		dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
572 			 __func__, __LINE__, surf.format);
573 		return -EINVAL;
574 	}
575 	/* replace by color format so we can use same code */
576 	surf.format = V_028C70_COLOR_8;
577 
578 	r = evergreen_surface_value_conv_check(p, &surf, "stencil");
579 	if (r) {
580 		return r;
581 	}
582 
583 	r = evergreen_surface_check(p, &surf, NULL);
584 	if (r) {
585 		/* old userspace doesn't compute proper depth/stencil alignment
586 		 * check that alignment against a bigger byte per elements and
587 		 * only report if that alignment is wrong too.
588 		 */
589 		surf.format = V_028C70_COLOR_8_8_8_8;
590 		r = evergreen_surface_check(p, &surf, "stencil");
591 		if (r) {
592 			dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
593 				 __func__, __LINE__, track->db_depth_size,
594 				 track->db_depth_slice, track->db_s_info, track->db_z_info);
595 		}
596 		return r;
597 	}
598 
599 	offset = track->db_s_read_offset << 8;
600 	if (offset & (surf.base_align - 1)) {
601 		dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
602 			 __func__, __LINE__, offset, surf.base_align);
603 		return -EINVAL;
604 	}
605 	offset += surf.layer_size * mslice;
606 	if (offset > radeon_bo_size(track->db_s_read_bo)) {
607 		dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
608 			 "offset %ld, max layer %d, bo size %ld)\n",
609 			 __func__, __LINE__, surf.layer_size,
610 			(unsigned long)track->db_s_read_offset << 8, mslice,
611 			radeon_bo_size(track->db_s_read_bo));
612 		dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
613 			 __func__, __LINE__, track->db_depth_size,
614 			 track->db_depth_slice, track->db_s_info, track->db_z_info);
615 		return -EINVAL;
616 	}
617 
618 	offset = track->db_s_write_offset << 8;
619 	if (offset & (surf.base_align - 1)) {
620 		dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
621 			 __func__, __LINE__, offset, surf.base_align);
622 		return -EINVAL;
623 	}
624 	offset += surf.layer_size * mslice;
625 	if (offset > radeon_bo_size(track->db_s_write_bo)) {
626 		dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
627 			 "offset %ld, max layer %d, bo size %ld)\n",
628 			 __func__, __LINE__, surf.layer_size,
629 			(unsigned long)track->db_s_write_offset << 8, mslice,
630 			radeon_bo_size(track->db_s_write_bo));
631 		return -EINVAL;
632 	}
633 
634 	/* hyperz */
635 	if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
636 		r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
637 		if (r) {
638 			return r;
639 		}
640 	}
641 
642 	return 0;
643 }
644 
evergreen_cs_track_validate_depth(struct radeon_cs_parser * p)645 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
646 {
647 	struct evergreen_cs_track *track = p->track;
648 	struct eg_surface surf;
649 	unsigned pitch, slice, mslice;
650 	unsigned long offset;
651 	int r;
652 
653 	mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
654 	pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
655 	slice = track->db_depth_slice;
656 	surf.nbx = (pitch + 1) * 8;
657 	surf.nby = ((slice + 1) * 64) / surf.nbx;
658 	surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
659 	surf.format = G_028040_FORMAT(track->db_z_info);
660 	surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
661 	surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
662 	surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
663 	surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
664 	surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
665 	surf.nsamples = 1;
666 
667 	switch (surf.format) {
668 	case V_028040_Z_16:
669 		surf.format = V_028C70_COLOR_16;
670 		break;
671 	case V_028040_Z_24:
672 	case V_028040_Z_32_FLOAT:
673 		surf.format = V_028C70_COLOR_8_8_8_8;
674 		break;
675 	default:
676 		dev_warn(p->dev, "%s:%d depth invalid format %d\n",
677 			 __func__, __LINE__, surf.format);
678 		return -EINVAL;
679 	}
680 
681 	r = evergreen_surface_value_conv_check(p, &surf, "depth");
682 	if (r) {
683 		dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
684 			 __func__, __LINE__, track->db_depth_size,
685 			 track->db_depth_slice, track->db_z_info);
686 		return r;
687 	}
688 
689 	r = evergreen_surface_check(p, &surf, "depth");
690 	if (r) {
691 		dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
692 			 __func__, __LINE__, track->db_depth_size,
693 			 track->db_depth_slice, track->db_z_info);
694 		return r;
695 	}
696 
697 	offset = track->db_z_read_offset << 8;
698 	if (offset & (surf.base_align - 1)) {
699 		dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
700 			 __func__, __LINE__, offset, surf.base_align);
701 		return -EINVAL;
702 	}
703 	offset += surf.layer_size * mslice;
704 	if (offset > radeon_bo_size(track->db_z_read_bo)) {
705 		dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
706 			 "offset %ld, max layer %d, bo size %ld)\n",
707 			 __func__, __LINE__, surf.layer_size,
708 			(unsigned long)track->db_z_read_offset << 8, mslice,
709 			radeon_bo_size(track->db_z_read_bo));
710 		return -EINVAL;
711 	}
712 
713 	offset = track->db_z_write_offset << 8;
714 	if (offset & (surf.base_align - 1)) {
715 		dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
716 			 __func__, __LINE__, offset, surf.base_align);
717 		return -EINVAL;
718 	}
719 	offset += surf.layer_size * mslice;
720 	if (offset > radeon_bo_size(track->db_z_write_bo)) {
721 		dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
722 			 "offset %ld, max layer %d, bo size %ld)\n",
723 			 __func__, __LINE__, surf.layer_size,
724 			(unsigned long)track->db_z_write_offset << 8, mslice,
725 			radeon_bo_size(track->db_z_write_bo));
726 		return -EINVAL;
727 	}
728 
729 	/* hyperz */
730 	if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
731 		r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
732 		if (r) {
733 			return r;
734 		}
735 	}
736 
737 	return 0;
738 }
739 
evergreen_cs_track_validate_texture(struct radeon_cs_parser * p,struct radeon_bo * texture,struct radeon_bo * mipmap,unsigned idx)740 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
741 					       struct radeon_bo *texture,
742 					       struct radeon_bo *mipmap,
743 					       unsigned idx)
744 {
745 	struct eg_surface surf;
746 	unsigned long toffset, moffset;
747 	unsigned dim, llevel, mslice, width, height, depth, i;
748 	u32 texdw[8];
749 	int r;
750 
751 	texdw[0] = radeon_get_ib_value(p, idx + 0);
752 	texdw[1] = radeon_get_ib_value(p, idx + 1);
753 	texdw[2] = radeon_get_ib_value(p, idx + 2);
754 	texdw[3] = radeon_get_ib_value(p, idx + 3);
755 	texdw[4] = radeon_get_ib_value(p, idx + 4);
756 	texdw[5] = radeon_get_ib_value(p, idx + 5);
757 	texdw[6] = radeon_get_ib_value(p, idx + 6);
758 	texdw[7] = radeon_get_ib_value(p, idx + 7);
759 	dim = G_030000_DIM(texdw[0]);
760 	llevel = G_030014_LAST_LEVEL(texdw[5]);
761 	mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
762 	width = G_030000_TEX_WIDTH(texdw[0]) + 1;
763 	height =  G_030004_TEX_HEIGHT(texdw[1]) + 1;
764 	depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
765 	surf.format = G_03001C_DATA_FORMAT(texdw[7]);
766 	surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
767 	surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
768 	surf.nby = r600_fmt_get_nblocksy(surf.format, height);
769 	surf.mode = G_030004_ARRAY_MODE(texdw[1]);
770 	surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
771 	surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
772 	surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
773 	surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
774 	surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
775 	surf.nsamples = 1;
776 	toffset = texdw[2] << 8;
777 	moffset = texdw[3] << 8;
778 
779 	if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
780 		dev_warn(p->dev, "%s:%d texture invalid format %d\n",
781 			 __func__, __LINE__, surf.format);
782 		return -EINVAL;
783 	}
784 	switch (dim) {
785 	case V_030000_SQ_TEX_DIM_1D:
786 	case V_030000_SQ_TEX_DIM_2D:
787 	case V_030000_SQ_TEX_DIM_CUBEMAP:
788 	case V_030000_SQ_TEX_DIM_1D_ARRAY:
789 	case V_030000_SQ_TEX_DIM_2D_ARRAY:
790 		depth = 1;
791 	case V_030000_SQ_TEX_DIM_3D:
792 		break;
793 	default:
794 		dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
795 			 __func__, __LINE__, dim);
796 		return -EINVAL;
797 	}
798 
799 	r = evergreen_surface_value_conv_check(p, &surf, "texture");
800 	if (r) {
801 		return r;
802 	}
803 
804 	/* align height */
805 	evergreen_surface_check(p, &surf, NULL);
806 	surf.nby = ALIGN(surf.nby, surf.halign);
807 
808 	r = evergreen_surface_check(p, &surf, "texture");
809 	if (r) {
810 		dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
811 			 __func__, __LINE__, texdw[0], texdw[1], texdw[4],
812 			 texdw[5], texdw[6], texdw[7]);
813 		return r;
814 	}
815 
816 	/* check texture size */
817 	if (toffset & (surf.base_align - 1)) {
818 		dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
819 			 __func__, __LINE__, toffset, surf.base_align);
820 		return -EINVAL;
821 	}
822 	if (moffset & (surf.base_align - 1)) {
823 		dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
824 			 __func__, __LINE__, moffset, surf.base_align);
825 		return -EINVAL;
826 	}
827 	if (dim == SQ_TEX_DIM_3D) {
828 		toffset += surf.layer_size * depth;
829 	} else {
830 		toffset += surf.layer_size * mslice;
831 	}
832 	if (toffset > radeon_bo_size(texture)) {
833 		dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
834 			 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
835 			 __func__, __LINE__, surf.layer_size,
836 			(unsigned long)texdw[2] << 8, mslice,
837 			depth, radeon_bo_size(texture),
838 			surf.nbx, surf.nby);
839 		return -EINVAL;
840 	}
841 
842 	/* check mipmap size */
843 	for (i = 1; i <= llevel; i++) {
844 		unsigned w, h, d;
845 
846 		w = r600_mip_minify(width, i);
847 		h = r600_mip_minify(height, i);
848 		d = r600_mip_minify(depth, i);
849 		surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
850 		surf.nby = r600_fmt_get_nblocksy(surf.format, h);
851 
852 		switch (surf.mode) {
853 		case ARRAY_2D_TILED_THIN1:
854 			if (surf.nbx < surf.palign || surf.nby < surf.halign) {
855 				surf.mode = ARRAY_1D_TILED_THIN1;
856 			}
857 			/* recompute alignment */
858 			evergreen_surface_check(p, &surf, NULL);
859 			break;
860 		case ARRAY_LINEAR_GENERAL:
861 		case ARRAY_LINEAR_ALIGNED:
862 		case ARRAY_1D_TILED_THIN1:
863 			break;
864 		default:
865 			dev_warn(p->dev, "%s:%d invalid array mode %d\n",
866 				 __func__, __LINE__, surf.mode);
867 			return -EINVAL;
868 		}
869 		surf.nbx = ALIGN(surf.nbx, surf.palign);
870 		surf.nby = ALIGN(surf.nby, surf.halign);
871 
872 		r = evergreen_surface_check(p, &surf, "mipmap");
873 		if (r) {
874 			return r;
875 		}
876 
877 		if (dim == SQ_TEX_DIM_3D) {
878 			moffset += surf.layer_size * d;
879 		} else {
880 			moffset += surf.layer_size * mslice;
881 		}
882 		if (moffset > radeon_bo_size(mipmap)) {
883 			dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
884 					"offset %ld, coffset %ld, max layer %d, depth %d, "
885 					"bo size %ld) level0 (%d %d %d)\n",
886 					__func__, __LINE__, i, surf.layer_size,
887 					(unsigned long)texdw[3] << 8, moffset, mslice,
888 					d, radeon_bo_size(mipmap),
889 					width, height, depth);
890 			dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
891 				 __func__, __LINE__, surf.nbx, surf.nby,
892 				surf.mode, surf.bpe, surf.nsamples,
893 				surf.bankw, surf.bankh,
894 				surf.tsplit, surf.mtilea);
895 			return -EINVAL;
896 		}
897 	}
898 
899 	return 0;
900 }
901 
evergreen_cs_track_check(struct radeon_cs_parser * p)902 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
903 {
904 	struct evergreen_cs_track *track = p->track;
905 	unsigned tmp, i;
906 	int r;
907 	unsigned buffer_mask = 0;
908 
909 	/* check streamout */
910 	if (track->streamout_dirty && track->vgt_strmout_config) {
911 		for (i = 0; i < 4; i++) {
912 			if (track->vgt_strmout_config & (1 << i)) {
913 				buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
914 			}
915 		}
916 
917 		for (i = 0; i < 4; i++) {
918 			if (buffer_mask & (1 << i)) {
919 				if (track->vgt_strmout_bo[i]) {
920 					u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
921 							(u64)track->vgt_strmout_size[i];
922 					if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
923 						DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
924 							  i, offset,
925 							  radeon_bo_size(track->vgt_strmout_bo[i]));
926 						return -EINVAL;
927 					}
928 				} else {
929 					dev_warn(p->dev, "No buffer for streamout %d\n", i);
930 					return -EINVAL;
931 				}
932 			}
933 		}
934 		track->streamout_dirty = false;
935 	}
936 
937 	if (track->sx_misc_kill_all_prims)
938 		return 0;
939 
940 	/* check that we have a cb for each enabled target
941 	 */
942 	if (track->cb_dirty) {
943 		tmp = track->cb_target_mask;
944 		for (i = 0; i < 8; i++) {
945 			u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
946 
947 			if (format != V_028C70_COLOR_INVALID &&
948 			    (tmp >> (i * 4)) & 0xF) {
949 				/* at least one component is enabled */
950 				if (track->cb_color_bo[i] == NULL) {
951 					dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
952 						__func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
953 					return -EINVAL;
954 				}
955 				/* check cb */
956 				r = evergreen_cs_track_validate_cb(p, i);
957 				if (r) {
958 					return r;
959 				}
960 			}
961 		}
962 		track->cb_dirty = false;
963 	}
964 
965 	if (track->db_dirty) {
966 		/* Check stencil buffer */
967 		if (G_028800_STENCIL_ENABLE(track->db_depth_control)) {
968 			r = evergreen_cs_track_validate_stencil(p);
969 			if (r)
970 				return r;
971 		}
972 		/* Check depth buffer */
973 		if (G_028800_Z_ENABLE(track->db_depth_control)) {
974 			r = evergreen_cs_track_validate_depth(p);
975 			if (r)
976 				return r;
977 		}
978 		track->db_dirty = false;
979 	}
980 
981 	return 0;
982 }
983 
984 /**
985  * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
986  * @parser:	parser structure holding parsing context.
987  * @pkt:	where to store packet informations
988  *
989  * Assume that chunk_ib_index is properly set. Will return -EINVAL
990  * if packet is bigger than remaining ib size. or if packets is unknown.
991  **/
evergreen_cs_packet_parse(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx)992 int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
993 			      struct radeon_cs_packet *pkt,
994 			      unsigned idx)
995 {
996 	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
997 	uint32_t header;
998 
999 	if (idx >= ib_chunk->length_dw) {
1000 		DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1001 			  idx, ib_chunk->length_dw);
1002 		return -EINVAL;
1003 	}
1004 	header = radeon_get_ib_value(p, idx);
1005 	pkt->idx = idx;
1006 	pkt->type = CP_PACKET_GET_TYPE(header);
1007 	pkt->count = CP_PACKET_GET_COUNT(header);
1008 	pkt->one_reg_wr = 0;
1009 	switch (pkt->type) {
1010 	case PACKET_TYPE0:
1011 		pkt->reg = CP_PACKET0_GET_REG(header);
1012 		break;
1013 	case PACKET_TYPE3:
1014 		pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1015 		break;
1016 	case PACKET_TYPE2:
1017 		pkt->count = -1;
1018 		break;
1019 	default:
1020 		DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1021 		return -EINVAL;
1022 	}
1023 	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1024 		DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1025 			  pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1026 		return -EINVAL;
1027 	}
1028 	return 0;
1029 }
1030 
1031 /**
1032  * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1033  * @parser:		parser structure holding parsing context.
1034  * @data:		pointer to relocation data
1035  * @offset_start:	starting offset
1036  * @offset_mask:	offset mask (to align start offset on)
1037  * @reloc:		reloc informations
1038  *
1039  * Check next packet is relocation packet3, do bo validation and compute
1040  * GPU offset using the provided start.
1041  **/
evergreen_cs_packet_next_reloc(struct radeon_cs_parser * p,struct radeon_cs_reloc ** cs_reloc)1042 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
1043 					  struct radeon_cs_reloc **cs_reloc)
1044 {
1045 	struct radeon_cs_chunk *relocs_chunk;
1046 	struct radeon_cs_packet p3reloc;
1047 	unsigned idx;
1048 	int r;
1049 
1050 	if (p->chunk_relocs_idx == -1) {
1051 		DRM_ERROR("No relocation chunk !\n");
1052 		return -EINVAL;
1053 	}
1054 	*cs_reloc = NULL;
1055 	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1056 	r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1057 	if (r) {
1058 		return r;
1059 	}
1060 	p->idx += p3reloc.count + 2;
1061 	if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1062 		DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1063 			  p3reloc.idx);
1064 		return -EINVAL;
1065 	}
1066 	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1067 	if (idx >= relocs_chunk->length_dw) {
1068 		DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1069 			  idx, relocs_chunk->length_dw);
1070 		return -EINVAL;
1071 	}
1072 	/* FIXME: we assume reloc size is 4 dwords */
1073 	*cs_reloc = p->relocs_ptr[(idx / 4)];
1074 	return 0;
1075 }
1076 
1077 /**
1078  * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
1079  * @parser:		parser structure holding parsing context.
1080  *
1081  * Userspace sends a special sequence for VLINE waits.
1082  * PACKET0 - VLINE_START_END + value
1083  * PACKET3 - WAIT_REG_MEM poll vline status reg
1084  * RELOC (P3) - crtc_id in reloc.
1085  *
1086  * This function parses this and relocates the VLINE START END
1087  * and WAIT_REG_MEM packets to the correct crtc.
1088  * It also detects a switched off crtc and nulls out the
1089  * wait in that case.
1090  */
evergreen_cs_packet_parse_vline(struct radeon_cs_parser * p)1091 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1092 {
1093 	struct drm_mode_object *obj;
1094 	struct drm_crtc *crtc;
1095 	struct radeon_crtc *radeon_crtc;
1096 	struct radeon_cs_packet p3reloc, wait_reg_mem;
1097 	int crtc_id;
1098 	int r;
1099 	uint32_t header, h_idx, reg, wait_reg_mem_info;
1100 	volatile uint32_t *ib;
1101 
1102 	ib = p->ib->ptr;
1103 
1104 	/* parse the WAIT_REG_MEM */
1105 	r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
1106 	if (r)
1107 		return r;
1108 
1109 	/* check its a WAIT_REG_MEM */
1110 	if (wait_reg_mem.type != PACKET_TYPE3 ||
1111 	    wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1112 		DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1113 		return -EINVAL;
1114 	}
1115 
1116 	wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1117 	/* bit 4 is reg (0) or mem (1) */
1118 	if (wait_reg_mem_info & 0x10) {
1119 		DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1120 		return -EINVAL;
1121 	}
1122 	/* waiting for value to be equal */
1123 	if ((wait_reg_mem_info & 0x7) != 0x3) {
1124 		DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1125 		return -EINVAL;
1126 	}
1127 	if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
1128 		DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1129 		return -EINVAL;
1130 	}
1131 
1132 	if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
1133 		DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1134 		return -EINVAL;
1135 	}
1136 
1137 	/* jump over the NOP */
1138 	r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1139 	if (r)
1140 		return r;
1141 
1142 	h_idx = p->idx - 2;
1143 	p->idx += wait_reg_mem.count + 2;
1144 	p->idx += p3reloc.count + 2;
1145 
1146 	header = radeon_get_ib_value(p, h_idx);
1147 	crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1148 	reg = CP_PACKET0_GET_REG(header);
1149 	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1150 	if (!obj) {
1151 		DRM_ERROR("cannot find crtc %d\n", crtc_id);
1152 		return -EINVAL;
1153 	}
1154 	crtc = obj_to_crtc(obj);
1155 	radeon_crtc = to_radeon_crtc(crtc);
1156 	crtc_id = radeon_crtc->crtc_id;
1157 
1158 	if (!crtc->enabled) {
1159 		/* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1160 		ib[h_idx + 2] = PACKET2(0);
1161 		ib[h_idx + 3] = PACKET2(0);
1162 		ib[h_idx + 4] = PACKET2(0);
1163 		ib[h_idx + 5] = PACKET2(0);
1164 		ib[h_idx + 6] = PACKET2(0);
1165 		ib[h_idx + 7] = PACKET2(0);
1166 		ib[h_idx + 8] = PACKET2(0);
1167 	} else {
1168 		switch (reg) {
1169 		case EVERGREEN_VLINE_START_END:
1170 			header &= ~R600_CP_PACKET0_REG_MASK;
1171 			header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1172 			ib[h_idx] = header;
1173 			ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1174 			break;
1175 		default:
1176 			DRM_ERROR("unknown crtc reloc\n");
1177 			return -EINVAL;
1178 		}
1179 	}
1180 	return 0;
1181 }
1182 
evergreen_packet0_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)1183 static int evergreen_packet0_check(struct radeon_cs_parser *p,
1184 				   struct radeon_cs_packet *pkt,
1185 				   unsigned idx, unsigned reg)
1186 {
1187 	int r;
1188 
1189 	switch (reg) {
1190 	case EVERGREEN_VLINE_START_END:
1191 		r = evergreen_cs_packet_parse_vline(p);
1192 		if (r) {
1193 			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1194 					idx, reg);
1195 			return r;
1196 		}
1197 		break;
1198 	default:
1199 		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1200 		       reg, idx);
1201 		return -EINVAL;
1202 	}
1203 	return 0;
1204 }
1205 
evergreen_cs_parse_packet0(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1206 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1207 				      struct radeon_cs_packet *pkt)
1208 {
1209 	unsigned reg, i;
1210 	unsigned idx;
1211 	int r;
1212 
1213 	idx = pkt->idx + 1;
1214 	reg = pkt->reg;
1215 	for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1216 		r = evergreen_packet0_check(p, pkt, idx, reg);
1217 		if (r) {
1218 			return r;
1219 		}
1220 	}
1221 	return 0;
1222 }
1223 
1224 /**
1225  * evergreen_cs_check_reg() - check if register is authorized or not
1226  * @parser: parser structure holding parsing context
1227  * @reg: register we are testing
1228  * @idx: index into the cs buffer
1229  *
1230  * This function will test against evergreen_reg_safe_bm and return 0
1231  * if register is safe. If register is not flag as safe this function
1232  * will test it against a list of register needind special handling.
1233  */
evergreen_cs_check_reg(struct radeon_cs_parser * p,u32 reg,u32 idx)1234 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1235 {
1236 	struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1237 	struct radeon_cs_reloc *reloc;
1238 	u32 last_reg;
1239 	u32 m, i, tmp, *ib;
1240 	int r;
1241 
1242 	if (p->rdev->family >= CHIP_CAYMAN)
1243 		last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1244 	else
1245 		last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1246 
1247 	i = (reg >> 7);
1248 	if (i >= last_reg) {
1249 		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1250 		return -EINVAL;
1251 	}
1252 	m = 1 << ((reg >> 2) & 31);
1253 	if (p->rdev->family >= CHIP_CAYMAN) {
1254 		if (!(cayman_reg_safe_bm[i] & m))
1255 			return 0;
1256 	} else {
1257 		if (!(evergreen_reg_safe_bm[i] & m))
1258 			return 0;
1259 	}
1260 	ib = p->ib->ptr;
1261 	switch (reg) {
1262 	/* force following reg to 0 in an attempt to disable out buffer
1263 	 * which will need us to better understand how it works to perform
1264 	 * security check on it (Jerome)
1265 	 */
1266 	case SQ_ESGS_RING_SIZE:
1267 	case SQ_GSVS_RING_SIZE:
1268 	case SQ_ESTMP_RING_SIZE:
1269 	case SQ_GSTMP_RING_SIZE:
1270 	case SQ_HSTMP_RING_SIZE:
1271 	case SQ_LSTMP_RING_SIZE:
1272 	case SQ_PSTMP_RING_SIZE:
1273 	case SQ_VSTMP_RING_SIZE:
1274 	case SQ_ESGS_RING_ITEMSIZE:
1275 	case SQ_ESTMP_RING_ITEMSIZE:
1276 	case SQ_GSTMP_RING_ITEMSIZE:
1277 	case SQ_GSVS_RING_ITEMSIZE:
1278 	case SQ_GS_VERT_ITEMSIZE:
1279 	case SQ_GS_VERT_ITEMSIZE_1:
1280 	case SQ_GS_VERT_ITEMSIZE_2:
1281 	case SQ_GS_VERT_ITEMSIZE_3:
1282 	case SQ_GSVS_RING_OFFSET_1:
1283 	case SQ_GSVS_RING_OFFSET_2:
1284 	case SQ_GSVS_RING_OFFSET_3:
1285 	case SQ_HSTMP_RING_ITEMSIZE:
1286 	case SQ_LSTMP_RING_ITEMSIZE:
1287 	case SQ_PSTMP_RING_ITEMSIZE:
1288 	case SQ_VSTMP_RING_ITEMSIZE:
1289 	case VGT_TF_RING_SIZE:
1290 		/* get value to populate the IB don't remove */
1291 		/*tmp =radeon_get_ib_value(p, idx);
1292 		  ib[idx] = 0;*/
1293 		break;
1294 	case SQ_ESGS_RING_BASE:
1295 	case SQ_GSVS_RING_BASE:
1296 	case SQ_ESTMP_RING_BASE:
1297 	case SQ_GSTMP_RING_BASE:
1298 	case SQ_HSTMP_RING_BASE:
1299 	case SQ_LSTMP_RING_BASE:
1300 	case SQ_PSTMP_RING_BASE:
1301 	case SQ_VSTMP_RING_BASE:
1302 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1303 		if (r) {
1304 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1305 					"0x%04X\n", reg);
1306 			return -EINVAL;
1307 		}
1308 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1309 		break;
1310 	case DB_DEPTH_CONTROL:
1311 		track->db_depth_control = radeon_get_ib_value(p, idx);
1312 		track->db_dirty = true;
1313 		break;
1314 	case CAYMAN_DB_EQAA:
1315 		if (p->rdev->family < CHIP_CAYMAN) {
1316 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1317 				 "0x%04X\n", reg);
1318 			return -EINVAL;
1319 		}
1320 		break;
1321 	case CAYMAN_DB_DEPTH_INFO:
1322 		if (p->rdev->family < CHIP_CAYMAN) {
1323 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1324 				 "0x%04X\n", reg);
1325 			return -EINVAL;
1326 		}
1327 		break;
1328 	case DB_Z_INFO:
1329 		track->db_z_info = radeon_get_ib_value(p, idx);
1330 		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1331 			r = evergreen_cs_packet_next_reloc(p, &reloc);
1332 			if (r) {
1333 				dev_warn(p->dev, "bad SET_CONTEXT_REG "
1334 						"0x%04X\n", reg);
1335 				return -EINVAL;
1336 			}
1337 			ib[idx] &= ~Z_ARRAY_MODE(0xf);
1338 			track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1339 			ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1340 			track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1341 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1342 				unsigned bankw, bankh, mtaspect, tile_split;
1343 
1344 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1345 							&bankw, &bankh, &mtaspect,
1346 							&tile_split);
1347 				ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1348 				ib[idx] |= DB_TILE_SPLIT(tile_split) |
1349 						DB_BANK_WIDTH(bankw) |
1350 						DB_BANK_HEIGHT(bankh) |
1351 						DB_MACRO_TILE_ASPECT(mtaspect);
1352 			}
1353 		}
1354 		track->db_dirty = true;
1355 		break;
1356 	case DB_STENCIL_INFO:
1357 		track->db_s_info = radeon_get_ib_value(p, idx);
1358 		track->db_dirty = true;
1359 		break;
1360 	case DB_DEPTH_VIEW:
1361 		track->db_depth_view = radeon_get_ib_value(p, idx);
1362 		track->db_dirty = true;
1363 		break;
1364 	case DB_DEPTH_SIZE:
1365 		track->db_depth_size = radeon_get_ib_value(p, idx);
1366 		track->db_dirty = true;
1367 		break;
1368 	case R_02805C_DB_DEPTH_SLICE:
1369 		track->db_depth_slice = radeon_get_ib_value(p, idx);
1370 		track->db_dirty = true;
1371 		break;
1372 	case DB_Z_READ_BASE:
1373 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1374 		if (r) {
1375 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1376 					"0x%04X\n", reg);
1377 			return -EINVAL;
1378 		}
1379 		track->db_z_read_offset = radeon_get_ib_value(p, idx);
1380 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1381 		track->db_z_read_bo = reloc->robj;
1382 		track->db_dirty = true;
1383 		break;
1384 	case DB_Z_WRITE_BASE:
1385 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1386 		if (r) {
1387 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1388 					"0x%04X\n", reg);
1389 			return -EINVAL;
1390 		}
1391 		track->db_z_write_offset = radeon_get_ib_value(p, idx);
1392 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1393 		track->db_z_write_bo = reloc->robj;
1394 		track->db_dirty = true;
1395 		break;
1396 	case DB_STENCIL_READ_BASE:
1397 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1398 		if (r) {
1399 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1400 					"0x%04X\n", reg);
1401 			return -EINVAL;
1402 		}
1403 		track->db_s_read_offset = radeon_get_ib_value(p, idx);
1404 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1405 		track->db_s_read_bo = reloc->robj;
1406 		track->db_dirty = true;
1407 		break;
1408 	case DB_STENCIL_WRITE_BASE:
1409 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1410 		if (r) {
1411 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1412 					"0x%04X\n", reg);
1413 			return -EINVAL;
1414 		}
1415 		track->db_s_write_offset = radeon_get_ib_value(p, idx);
1416 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1417 		track->db_s_write_bo = reloc->robj;
1418 		track->db_dirty = true;
1419 		break;
1420 	case VGT_STRMOUT_CONFIG:
1421 		track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1422 		track->streamout_dirty = true;
1423 		break;
1424 	case VGT_STRMOUT_BUFFER_CONFIG:
1425 		track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1426 		track->streamout_dirty = true;
1427 		break;
1428 	case VGT_STRMOUT_BUFFER_BASE_0:
1429 	case VGT_STRMOUT_BUFFER_BASE_1:
1430 	case VGT_STRMOUT_BUFFER_BASE_2:
1431 	case VGT_STRMOUT_BUFFER_BASE_3:
1432 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1433 		if (r) {
1434 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1435 					"0x%04X\n", reg);
1436 			return -EINVAL;
1437 		}
1438 		tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1439 		track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1440 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1441 		track->vgt_strmout_bo[tmp] = reloc->robj;
1442 		track->streamout_dirty = true;
1443 		break;
1444 	case VGT_STRMOUT_BUFFER_SIZE_0:
1445 	case VGT_STRMOUT_BUFFER_SIZE_1:
1446 	case VGT_STRMOUT_BUFFER_SIZE_2:
1447 	case VGT_STRMOUT_BUFFER_SIZE_3:
1448 		tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1449 		/* size in register is DWs, convert to bytes */
1450 		track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1451 		track->streamout_dirty = true;
1452 		break;
1453 	case CP_COHER_BASE:
1454 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1455 		if (r) {
1456 			dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1457 					"0x%04X\n", reg);
1458 			return -EINVAL;
1459 		}
1460 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1461 	case CB_TARGET_MASK:
1462 		track->cb_target_mask = radeon_get_ib_value(p, idx);
1463 		track->cb_dirty = true;
1464 		break;
1465 	case CB_SHADER_MASK:
1466 		track->cb_shader_mask = radeon_get_ib_value(p, idx);
1467 		track->cb_dirty = true;
1468 		break;
1469 	case PA_SC_AA_CONFIG:
1470 		if (p->rdev->family >= CHIP_CAYMAN) {
1471 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1472 				 "0x%04X\n", reg);
1473 			return -EINVAL;
1474 		}
1475 		tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1476 		track->nsamples = 1 << tmp;
1477 		break;
1478 	case CAYMAN_PA_SC_AA_CONFIG:
1479 		if (p->rdev->family < CHIP_CAYMAN) {
1480 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1481 				 "0x%04X\n", reg);
1482 			return -EINVAL;
1483 		}
1484 		tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1485 		track->nsamples = 1 << tmp;
1486 		break;
1487 	case CB_COLOR0_VIEW:
1488 	case CB_COLOR1_VIEW:
1489 	case CB_COLOR2_VIEW:
1490 	case CB_COLOR3_VIEW:
1491 	case CB_COLOR4_VIEW:
1492 	case CB_COLOR5_VIEW:
1493 	case CB_COLOR6_VIEW:
1494 	case CB_COLOR7_VIEW:
1495 		tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1496 		track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1497 		track->cb_dirty = true;
1498 		break;
1499 	case CB_COLOR8_VIEW:
1500 	case CB_COLOR9_VIEW:
1501 	case CB_COLOR10_VIEW:
1502 	case CB_COLOR11_VIEW:
1503 		tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1504 		track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1505 		track->cb_dirty = true;
1506 		break;
1507 	case CB_COLOR0_INFO:
1508 	case CB_COLOR1_INFO:
1509 	case CB_COLOR2_INFO:
1510 	case CB_COLOR3_INFO:
1511 	case CB_COLOR4_INFO:
1512 	case CB_COLOR5_INFO:
1513 	case CB_COLOR6_INFO:
1514 	case CB_COLOR7_INFO:
1515 		tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1516 		track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1517 		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1518 			r = evergreen_cs_packet_next_reloc(p, &reloc);
1519 			if (r) {
1520 				dev_warn(p->dev, "bad SET_CONTEXT_REG "
1521 						"0x%04X\n", reg);
1522 				return -EINVAL;
1523 			}
1524 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1525 			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1526 		}
1527 		track->cb_dirty = true;
1528 		break;
1529 	case CB_COLOR8_INFO:
1530 	case CB_COLOR9_INFO:
1531 	case CB_COLOR10_INFO:
1532 	case CB_COLOR11_INFO:
1533 		tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1534 		track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1535 		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1536 			r = evergreen_cs_packet_next_reloc(p, &reloc);
1537 			if (r) {
1538 				dev_warn(p->dev, "bad SET_CONTEXT_REG "
1539 						"0x%04X\n", reg);
1540 				return -EINVAL;
1541 			}
1542 			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1543 			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1544 		}
1545 		track->cb_dirty = true;
1546 		break;
1547 	case CB_COLOR0_PITCH:
1548 	case CB_COLOR1_PITCH:
1549 	case CB_COLOR2_PITCH:
1550 	case CB_COLOR3_PITCH:
1551 	case CB_COLOR4_PITCH:
1552 	case CB_COLOR5_PITCH:
1553 	case CB_COLOR6_PITCH:
1554 	case CB_COLOR7_PITCH:
1555 		tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1556 		track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1557 		track->cb_dirty = true;
1558 		break;
1559 	case CB_COLOR8_PITCH:
1560 	case CB_COLOR9_PITCH:
1561 	case CB_COLOR10_PITCH:
1562 	case CB_COLOR11_PITCH:
1563 		tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1564 		track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1565 		track->cb_dirty = true;
1566 		break;
1567 	case CB_COLOR0_SLICE:
1568 	case CB_COLOR1_SLICE:
1569 	case CB_COLOR2_SLICE:
1570 	case CB_COLOR3_SLICE:
1571 	case CB_COLOR4_SLICE:
1572 	case CB_COLOR5_SLICE:
1573 	case CB_COLOR6_SLICE:
1574 	case CB_COLOR7_SLICE:
1575 		tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1576 		track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1577 		track->cb_color_slice_idx[tmp] = idx;
1578 		track->cb_dirty = true;
1579 		break;
1580 	case CB_COLOR8_SLICE:
1581 	case CB_COLOR9_SLICE:
1582 	case CB_COLOR10_SLICE:
1583 	case CB_COLOR11_SLICE:
1584 		tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1585 		track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1586 		track->cb_color_slice_idx[tmp] = idx;
1587 		track->cb_dirty = true;
1588 		break;
1589 	case CB_COLOR0_ATTRIB:
1590 	case CB_COLOR1_ATTRIB:
1591 	case CB_COLOR2_ATTRIB:
1592 	case CB_COLOR3_ATTRIB:
1593 	case CB_COLOR4_ATTRIB:
1594 	case CB_COLOR5_ATTRIB:
1595 	case CB_COLOR6_ATTRIB:
1596 	case CB_COLOR7_ATTRIB:
1597 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1598 		if (r) {
1599 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1600 					"0x%04X\n", reg);
1601 			return -EINVAL;
1602 		}
1603 		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1604 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1605 				unsigned bankw, bankh, mtaspect, tile_split;
1606 
1607 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1608 							&bankw, &bankh, &mtaspect,
1609 							&tile_split);
1610 				ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1611 				ib[idx] |= CB_TILE_SPLIT(tile_split) |
1612 					   CB_BANK_WIDTH(bankw) |
1613 					   CB_BANK_HEIGHT(bankh) |
1614 					   CB_MACRO_TILE_ASPECT(mtaspect);
1615 			}
1616 		}
1617 		tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1618 		track->cb_color_attrib[tmp] = ib[idx];
1619 		track->cb_dirty = true;
1620 		break;
1621 	case CB_COLOR8_ATTRIB:
1622 	case CB_COLOR9_ATTRIB:
1623 	case CB_COLOR10_ATTRIB:
1624 	case CB_COLOR11_ATTRIB:
1625 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1626 		if (r) {
1627 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1628 					"0x%04X\n", reg);
1629 			return -EINVAL;
1630 		}
1631 		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1632 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1633 				unsigned bankw, bankh, mtaspect, tile_split;
1634 
1635 				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1636 							&bankw, &bankh, &mtaspect,
1637 							&tile_split);
1638 				ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1639 				ib[idx] |= CB_TILE_SPLIT(tile_split) |
1640 					   CB_BANK_WIDTH(bankw) |
1641 					   CB_BANK_HEIGHT(bankh) |
1642 					   CB_MACRO_TILE_ASPECT(mtaspect);
1643 			}
1644 		}
1645 		tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1646 		track->cb_color_attrib[tmp] = ib[idx];
1647 		track->cb_dirty = true;
1648 		break;
1649 	case CB_COLOR0_FMASK:
1650 	case CB_COLOR1_FMASK:
1651 	case CB_COLOR2_FMASK:
1652 	case CB_COLOR3_FMASK:
1653 	case CB_COLOR4_FMASK:
1654 	case CB_COLOR5_FMASK:
1655 	case CB_COLOR6_FMASK:
1656 	case CB_COLOR7_FMASK:
1657 		tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1658 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1659 		if (r) {
1660 			dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1661 			return -EINVAL;
1662 		}
1663 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1664 		track->cb_color_fmask_bo[tmp] = reloc->robj;
1665 		break;
1666 	case CB_COLOR0_CMASK:
1667 	case CB_COLOR1_CMASK:
1668 	case CB_COLOR2_CMASK:
1669 	case CB_COLOR3_CMASK:
1670 	case CB_COLOR4_CMASK:
1671 	case CB_COLOR5_CMASK:
1672 	case CB_COLOR6_CMASK:
1673 	case CB_COLOR7_CMASK:
1674 		tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1675 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1676 		if (r) {
1677 			dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1678 			return -EINVAL;
1679 		}
1680 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1681 		track->cb_color_cmask_bo[tmp] = reloc->robj;
1682 		break;
1683 	case CB_COLOR0_FMASK_SLICE:
1684 	case CB_COLOR1_FMASK_SLICE:
1685 	case CB_COLOR2_FMASK_SLICE:
1686 	case CB_COLOR3_FMASK_SLICE:
1687 	case CB_COLOR4_FMASK_SLICE:
1688 	case CB_COLOR5_FMASK_SLICE:
1689 	case CB_COLOR6_FMASK_SLICE:
1690 	case CB_COLOR7_FMASK_SLICE:
1691 		tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1692 		track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1693 		break;
1694 	case CB_COLOR0_CMASK_SLICE:
1695 	case CB_COLOR1_CMASK_SLICE:
1696 	case CB_COLOR2_CMASK_SLICE:
1697 	case CB_COLOR3_CMASK_SLICE:
1698 	case CB_COLOR4_CMASK_SLICE:
1699 	case CB_COLOR5_CMASK_SLICE:
1700 	case CB_COLOR6_CMASK_SLICE:
1701 	case CB_COLOR7_CMASK_SLICE:
1702 		tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1703 		track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1704 		break;
1705 	case CB_COLOR0_BASE:
1706 	case CB_COLOR1_BASE:
1707 	case CB_COLOR2_BASE:
1708 	case CB_COLOR3_BASE:
1709 	case CB_COLOR4_BASE:
1710 	case CB_COLOR5_BASE:
1711 	case CB_COLOR6_BASE:
1712 	case CB_COLOR7_BASE:
1713 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1714 		if (r) {
1715 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1716 					"0x%04X\n", reg);
1717 			return -EINVAL;
1718 		}
1719 		tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1720 		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1721 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1722 		track->cb_color_bo[tmp] = reloc->robj;
1723 		track->cb_dirty = true;
1724 		break;
1725 	case CB_COLOR8_BASE:
1726 	case CB_COLOR9_BASE:
1727 	case CB_COLOR10_BASE:
1728 	case CB_COLOR11_BASE:
1729 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1730 		if (r) {
1731 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1732 					"0x%04X\n", reg);
1733 			return -EINVAL;
1734 		}
1735 		tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1736 		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1737 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1738 		track->cb_color_bo[tmp] = reloc->robj;
1739 		track->cb_dirty = true;
1740 		break;
1741 	case DB_HTILE_DATA_BASE:
1742 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1743 		if (r) {
1744 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1745 					"0x%04X\n", reg);
1746 			return -EINVAL;
1747 		}
1748 		track->htile_offset = radeon_get_ib_value(p, idx);
1749 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1750 		track->htile_bo = reloc->robj;
1751 		track->db_dirty = true;
1752 		break;
1753 	case DB_HTILE_SURFACE:
1754 		/* 8x8 only */
1755 		track->htile_surface = radeon_get_ib_value(p, idx);
1756 		track->db_dirty = true;
1757 		break;
1758 	case CB_IMMED0_BASE:
1759 	case CB_IMMED1_BASE:
1760 	case CB_IMMED2_BASE:
1761 	case CB_IMMED3_BASE:
1762 	case CB_IMMED4_BASE:
1763 	case CB_IMMED5_BASE:
1764 	case CB_IMMED6_BASE:
1765 	case CB_IMMED7_BASE:
1766 	case CB_IMMED8_BASE:
1767 	case CB_IMMED9_BASE:
1768 	case CB_IMMED10_BASE:
1769 	case CB_IMMED11_BASE:
1770 	case SQ_PGM_START_FS:
1771 	case SQ_PGM_START_ES:
1772 	case SQ_PGM_START_VS:
1773 	case SQ_PGM_START_GS:
1774 	case SQ_PGM_START_PS:
1775 	case SQ_PGM_START_HS:
1776 	case SQ_PGM_START_LS:
1777 	case SQ_CONST_MEM_BASE:
1778 	case SQ_ALU_CONST_CACHE_GS_0:
1779 	case SQ_ALU_CONST_CACHE_GS_1:
1780 	case SQ_ALU_CONST_CACHE_GS_2:
1781 	case SQ_ALU_CONST_CACHE_GS_3:
1782 	case SQ_ALU_CONST_CACHE_GS_4:
1783 	case SQ_ALU_CONST_CACHE_GS_5:
1784 	case SQ_ALU_CONST_CACHE_GS_6:
1785 	case SQ_ALU_CONST_CACHE_GS_7:
1786 	case SQ_ALU_CONST_CACHE_GS_8:
1787 	case SQ_ALU_CONST_CACHE_GS_9:
1788 	case SQ_ALU_CONST_CACHE_GS_10:
1789 	case SQ_ALU_CONST_CACHE_GS_11:
1790 	case SQ_ALU_CONST_CACHE_GS_12:
1791 	case SQ_ALU_CONST_CACHE_GS_13:
1792 	case SQ_ALU_CONST_CACHE_GS_14:
1793 	case SQ_ALU_CONST_CACHE_GS_15:
1794 	case SQ_ALU_CONST_CACHE_PS_0:
1795 	case SQ_ALU_CONST_CACHE_PS_1:
1796 	case SQ_ALU_CONST_CACHE_PS_2:
1797 	case SQ_ALU_CONST_CACHE_PS_3:
1798 	case SQ_ALU_CONST_CACHE_PS_4:
1799 	case SQ_ALU_CONST_CACHE_PS_5:
1800 	case SQ_ALU_CONST_CACHE_PS_6:
1801 	case SQ_ALU_CONST_CACHE_PS_7:
1802 	case SQ_ALU_CONST_CACHE_PS_8:
1803 	case SQ_ALU_CONST_CACHE_PS_9:
1804 	case SQ_ALU_CONST_CACHE_PS_10:
1805 	case SQ_ALU_CONST_CACHE_PS_11:
1806 	case SQ_ALU_CONST_CACHE_PS_12:
1807 	case SQ_ALU_CONST_CACHE_PS_13:
1808 	case SQ_ALU_CONST_CACHE_PS_14:
1809 	case SQ_ALU_CONST_CACHE_PS_15:
1810 	case SQ_ALU_CONST_CACHE_VS_0:
1811 	case SQ_ALU_CONST_CACHE_VS_1:
1812 	case SQ_ALU_CONST_CACHE_VS_2:
1813 	case SQ_ALU_CONST_CACHE_VS_3:
1814 	case SQ_ALU_CONST_CACHE_VS_4:
1815 	case SQ_ALU_CONST_CACHE_VS_5:
1816 	case SQ_ALU_CONST_CACHE_VS_6:
1817 	case SQ_ALU_CONST_CACHE_VS_7:
1818 	case SQ_ALU_CONST_CACHE_VS_8:
1819 	case SQ_ALU_CONST_CACHE_VS_9:
1820 	case SQ_ALU_CONST_CACHE_VS_10:
1821 	case SQ_ALU_CONST_CACHE_VS_11:
1822 	case SQ_ALU_CONST_CACHE_VS_12:
1823 	case SQ_ALU_CONST_CACHE_VS_13:
1824 	case SQ_ALU_CONST_CACHE_VS_14:
1825 	case SQ_ALU_CONST_CACHE_VS_15:
1826 	case SQ_ALU_CONST_CACHE_HS_0:
1827 	case SQ_ALU_CONST_CACHE_HS_1:
1828 	case SQ_ALU_CONST_CACHE_HS_2:
1829 	case SQ_ALU_CONST_CACHE_HS_3:
1830 	case SQ_ALU_CONST_CACHE_HS_4:
1831 	case SQ_ALU_CONST_CACHE_HS_5:
1832 	case SQ_ALU_CONST_CACHE_HS_6:
1833 	case SQ_ALU_CONST_CACHE_HS_7:
1834 	case SQ_ALU_CONST_CACHE_HS_8:
1835 	case SQ_ALU_CONST_CACHE_HS_9:
1836 	case SQ_ALU_CONST_CACHE_HS_10:
1837 	case SQ_ALU_CONST_CACHE_HS_11:
1838 	case SQ_ALU_CONST_CACHE_HS_12:
1839 	case SQ_ALU_CONST_CACHE_HS_13:
1840 	case SQ_ALU_CONST_CACHE_HS_14:
1841 	case SQ_ALU_CONST_CACHE_HS_15:
1842 	case SQ_ALU_CONST_CACHE_LS_0:
1843 	case SQ_ALU_CONST_CACHE_LS_1:
1844 	case SQ_ALU_CONST_CACHE_LS_2:
1845 	case SQ_ALU_CONST_CACHE_LS_3:
1846 	case SQ_ALU_CONST_CACHE_LS_4:
1847 	case SQ_ALU_CONST_CACHE_LS_5:
1848 	case SQ_ALU_CONST_CACHE_LS_6:
1849 	case SQ_ALU_CONST_CACHE_LS_7:
1850 	case SQ_ALU_CONST_CACHE_LS_8:
1851 	case SQ_ALU_CONST_CACHE_LS_9:
1852 	case SQ_ALU_CONST_CACHE_LS_10:
1853 	case SQ_ALU_CONST_CACHE_LS_11:
1854 	case SQ_ALU_CONST_CACHE_LS_12:
1855 	case SQ_ALU_CONST_CACHE_LS_13:
1856 	case SQ_ALU_CONST_CACHE_LS_14:
1857 	case SQ_ALU_CONST_CACHE_LS_15:
1858 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1859 		if (r) {
1860 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1861 					"0x%04X\n", reg);
1862 			return -EINVAL;
1863 		}
1864 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1865 		break;
1866 	case SX_MEMORY_EXPORT_BASE:
1867 		if (p->rdev->family >= CHIP_CAYMAN) {
1868 			dev_warn(p->dev, "bad SET_CONFIG_REG "
1869 				 "0x%04X\n", reg);
1870 			return -EINVAL;
1871 		}
1872 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1873 		if (r) {
1874 			dev_warn(p->dev, "bad SET_CONFIG_REG "
1875 					"0x%04X\n", reg);
1876 			return -EINVAL;
1877 		}
1878 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1879 		break;
1880 	case CAYMAN_SX_SCATTER_EXPORT_BASE:
1881 		if (p->rdev->family < CHIP_CAYMAN) {
1882 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1883 				 "0x%04X\n", reg);
1884 			return -EINVAL;
1885 		}
1886 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1887 		if (r) {
1888 			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1889 					"0x%04X\n", reg);
1890 			return -EINVAL;
1891 		}
1892 		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1893 		break;
1894 	case SX_MISC:
1895 		track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1896 		break;
1897 	default:
1898 		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1899 		return -EINVAL;
1900 	}
1901 	return 0;
1902 }
1903 
evergreen_is_safe_reg(struct radeon_cs_parser * p,u32 reg,u32 idx)1904 static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1905 {
1906 	u32 last_reg, m, i;
1907 
1908 	if (p->rdev->family >= CHIP_CAYMAN)
1909 		last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1910 	else
1911 		last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1912 
1913 	i = (reg >> 7);
1914 	if (i >= last_reg) {
1915 		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1916 		return false;
1917 	}
1918 	m = 1 << ((reg >> 2) & 31);
1919 	if (p->rdev->family >= CHIP_CAYMAN) {
1920 		if (!(cayman_reg_safe_bm[i] & m))
1921 			return true;
1922 	} else {
1923 		if (!(evergreen_reg_safe_bm[i] & m))
1924 			return true;
1925 	}
1926 	dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1927 	return false;
1928 }
1929 
evergreen_packet3_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1930 static int evergreen_packet3_check(struct radeon_cs_parser *p,
1931 				   struct radeon_cs_packet *pkt)
1932 {
1933 	struct radeon_cs_reloc *reloc;
1934 	struct evergreen_cs_track *track;
1935 	volatile u32 *ib;
1936 	unsigned idx;
1937 	unsigned i;
1938 	unsigned start_reg, end_reg, reg;
1939 	int r;
1940 	u32 idx_value;
1941 
1942 	track = (struct evergreen_cs_track *)p->track;
1943 	ib = p->ib->ptr;
1944 	idx = pkt->idx + 1;
1945 	idx_value = radeon_get_ib_value(p, idx);
1946 
1947 	switch (pkt->opcode) {
1948 	case PACKET3_SET_PREDICATION:
1949 	{
1950 		int pred_op;
1951 		int tmp;
1952 		uint64_t offset;
1953 
1954 		if (pkt->count != 1) {
1955 			DRM_ERROR("bad SET PREDICATION\n");
1956 			return -EINVAL;
1957 		}
1958 
1959 		tmp = radeon_get_ib_value(p, idx + 1);
1960 		pred_op = (tmp >> 16) & 0x7;
1961 
1962 		/* for the clear predicate operation */
1963 		if (pred_op == 0)
1964 			return 0;
1965 
1966 		if (pred_op > 2) {
1967 			DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1968 			return -EINVAL;
1969 		}
1970 
1971 		r = evergreen_cs_packet_next_reloc(p, &reloc);
1972 		if (r) {
1973 			DRM_ERROR("bad SET PREDICATION\n");
1974 			return -EINVAL;
1975 		}
1976 
1977 		offset = reloc->lobj.gpu_offset +
1978 		         (idx_value & 0xfffffff0) +
1979 		         ((u64)(tmp & 0xff) << 32);
1980 
1981 		ib[idx + 0] = offset;
1982 		ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1983 	}
1984 	break;
1985 	case PACKET3_CONTEXT_CONTROL:
1986 		if (pkt->count != 1) {
1987 			DRM_ERROR("bad CONTEXT_CONTROL\n");
1988 			return -EINVAL;
1989 		}
1990 		break;
1991 	case PACKET3_INDEX_TYPE:
1992 	case PACKET3_NUM_INSTANCES:
1993 	case PACKET3_CLEAR_STATE:
1994 		if (pkt->count) {
1995 			DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1996 			return -EINVAL;
1997 		}
1998 		break;
1999 	case CAYMAN_PACKET3_DEALLOC_STATE:
2000 		if (p->rdev->family < CHIP_CAYMAN) {
2001 			DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
2002 			return -EINVAL;
2003 		}
2004 		if (pkt->count) {
2005 			DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2006 			return -EINVAL;
2007 		}
2008 		break;
2009 	case PACKET3_INDEX_BASE:
2010 	{
2011 		uint64_t offset;
2012 
2013 		if (pkt->count != 1) {
2014 			DRM_ERROR("bad INDEX_BASE\n");
2015 			return -EINVAL;
2016 		}
2017 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2018 		if (r) {
2019 			DRM_ERROR("bad INDEX_BASE\n");
2020 			return -EINVAL;
2021 		}
2022 
2023 		offset = reloc->lobj.gpu_offset +
2024 		         idx_value +
2025 		         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2026 
2027 		ib[idx+0] = offset;
2028 		ib[idx+1] = upper_32_bits(offset) & 0xff;
2029 
2030 		r = evergreen_cs_track_check(p);
2031 		if (r) {
2032 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2033 			return r;
2034 		}
2035 		break;
2036 	}
2037 	case PACKET3_DRAW_INDEX:
2038 	{
2039 		uint64_t offset;
2040 		if (pkt->count != 3) {
2041 			DRM_ERROR("bad DRAW_INDEX\n");
2042 			return -EINVAL;
2043 		}
2044 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2045 		if (r) {
2046 			DRM_ERROR("bad DRAW_INDEX\n");
2047 			return -EINVAL;
2048 		}
2049 
2050 		offset = reloc->lobj.gpu_offset +
2051 		         idx_value +
2052 		         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2053 
2054 		ib[idx+0] = offset;
2055 		ib[idx+1] = upper_32_bits(offset) & 0xff;
2056 
2057 		r = evergreen_cs_track_check(p);
2058 		if (r) {
2059 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2060 			return r;
2061 		}
2062 		break;
2063 	}
2064 	case PACKET3_DRAW_INDEX_2:
2065 	{
2066 		uint64_t offset;
2067 
2068 		if (pkt->count != 4) {
2069 			DRM_ERROR("bad DRAW_INDEX_2\n");
2070 			return -EINVAL;
2071 		}
2072 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2073 		if (r) {
2074 			DRM_ERROR("bad DRAW_INDEX_2\n");
2075 			return -EINVAL;
2076 		}
2077 
2078 		offset = reloc->lobj.gpu_offset +
2079 		         radeon_get_ib_value(p, idx+1) +
2080 		         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2081 
2082 		ib[idx+1] = offset;
2083 		ib[idx+2] = upper_32_bits(offset) & 0xff;
2084 
2085 		r = evergreen_cs_track_check(p);
2086 		if (r) {
2087 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2088 			return r;
2089 		}
2090 		break;
2091 	}
2092 	case PACKET3_DRAW_INDEX_AUTO:
2093 		if (pkt->count != 1) {
2094 			DRM_ERROR("bad DRAW_INDEX_AUTO\n");
2095 			return -EINVAL;
2096 		}
2097 		r = evergreen_cs_track_check(p);
2098 		if (r) {
2099 			dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2100 			return r;
2101 		}
2102 		break;
2103 	case PACKET3_DRAW_INDEX_MULTI_AUTO:
2104 		if (pkt->count != 2) {
2105 			DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
2106 			return -EINVAL;
2107 		}
2108 		r = evergreen_cs_track_check(p);
2109 		if (r) {
2110 			dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2111 			return r;
2112 		}
2113 		break;
2114 	case PACKET3_DRAW_INDEX_IMMD:
2115 		if (pkt->count < 2) {
2116 			DRM_ERROR("bad DRAW_INDEX_IMMD\n");
2117 			return -EINVAL;
2118 		}
2119 		r = evergreen_cs_track_check(p);
2120 		if (r) {
2121 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2122 			return r;
2123 		}
2124 		break;
2125 	case PACKET3_DRAW_INDEX_OFFSET:
2126 		if (pkt->count != 2) {
2127 			DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
2128 			return -EINVAL;
2129 		}
2130 		r = evergreen_cs_track_check(p);
2131 		if (r) {
2132 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2133 			return r;
2134 		}
2135 		break;
2136 	case PACKET3_DRAW_INDEX_OFFSET_2:
2137 		if (pkt->count != 3) {
2138 			DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2139 			return -EINVAL;
2140 		}
2141 		r = evergreen_cs_track_check(p);
2142 		if (r) {
2143 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2144 			return r;
2145 		}
2146 		break;
2147 	case PACKET3_DISPATCH_DIRECT:
2148 		if (pkt->count != 3) {
2149 			DRM_ERROR("bad DISPATCH_DIRECT\n");
2150 			return -EINVAL;
2151 		}
2152 		r = evergreen_cs_track_check(p);
2153 		if (r) {
2154 			dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2155 			return r;
2156 		}
2157 		break;
2158 	case PACKET3_DISPATCH_INDIRECT:
2159 		if (pkt->count != 1) {
2160 			DRM_ERROR("bad DISPATCH_INDIRECT\n");
2161 			return -EINVAL;
2162 		}
2163 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2164 		if (r) {
2165 			DRM_ERROR("bad DISPATCH_INDIRECT\n");
2166 			return -EINVAL;
2167 		}
2168 		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2169 		r = evergreen_cs_track_check(p);
2170 		if (r) {
2171 			dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2172 			return r;
2173 		}
2174 		break;
2175 	case PACKET3_WAIT_REG_MEM:
2176 		if (pkt->count != 5) {
2177 			DRM_ERROR("bad WAIT_REG_MEM\n");
2178 			return -EINVAL;
2179 		}
2180 		/* bit 4 is reg (0) or mem (1) */
2181 		if (idx_value & 0x10) {
2182 			uint64_t offset;
2183 
2184 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2185 			if (r) {
2186 				DRM_ERROR("bad WAIT_REG_MEM\n");
2187 				return -EINVAL;
2188 			}
2189 
2190 			offset = reloc->lobj.gpu_offset +
2191 			         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2192 			         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2193 
2194 			ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2195 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2196 		}
2197 		break;
2198 	case PACKET3_SURFACE_SYNC:
2199 		if (pkt->count != 3) {
2200 			DRM_ERROR("bad SURFACE_SYNC\n");
2201 			return -EINVAL;
2202 		}
2203 		/* 0xffffffff/0x0 is flush all cache flag */
2204 		if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2205 		    radeon_get_ib_value(p, idx + 2) != 0) {
2206 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2207 			if (r) {
2208 				DRM_ERROR("bad SURFACE_SYNC\n");
2209 				return -EINVAL;
2210 			}
2211 			ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2212 		}
2213 		break;
2214 	case PACKET3_EVENT_WRITE:
2215 		if (pkt->count != 2 && pkt->count != 0) {
2216 			DRM_ERROR("bad EVENT_WRITE\n");
2217 			return -EINVAL;
2218 		}
2219 		if (pkt->count) {
2220 			uint64_t offset;
2221 
2222 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2223 			if (r) {
2224 				DRM_ERROR("bad EVENT_WRITE\n");
2225 				return -EINVAL;
2226 			}
2227 			offset = reloc->lobj.gpu_offset +
2228 			         (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2229 			         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2230 
2231 			ib[idx+1] = offset & 0xfffffff8;
2232 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2233 		}
2234 		break;
2235 	case PACKET3_EVENT_WRITE_EOP:
2236 	{
2237 		uint64_t offset;
2238 
2239 		if (pkt->count != 4) {
2240 			DRM_ERROR("bad EVENT_WRITE_EOP\n");
2241 			return -EINVAL;
2242 		}
2243 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2244 		if (r) {
2245 			DRM_ERROR("bad EVENT_WRITE_EOP\n");
2246 			return -EINVAL;
2247 		}
2248 
2249 		offset = reloc->lobj.gpu_offset +
2250 		         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2251 		         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2252 
2253 		ib[idx+1] = offset & 0xfffffffc;
2254 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2255 		break;
2256 	}
2257 	case PACKET3_EVENT_WRITE_EOS:
2258 	{
2259 		uint64_t offset;
2260 
2261 		if (pkt->count != 3) {
2262 			DRM_ERROR("bad EVENT_WRITE_EOS\n");
2263 			return -EINVAL;
2264 		}
2265 		r = evergreen_cs_packet_next_reloc(p, &reloc);
2266 		if (r) {
2267 			DRM_ERROR("bad EVENT_WRITE_EOS\n");
2268 			return -EINVAL;
2269 		}
2270 
2271 		offset = reloc->lobj.gpu_offset +
2272 		         (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2273 		         ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2274 
2275 		ib[idx+1] = offset & 0xfffffffc;
2276 		ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2277 		break;
2278 	}
2279 	case PACKET3_SET_CONFIG_REG:
2280 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2281 		end_reg = 4 * pkt->count + start_reg - 4;
2282 		if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2283 		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2284 		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2285 			DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2286 			return -EINVAL;
2287 		}
2288 		for (i = 0; i < pkt->count; i++) {
2289 			reg = start_reg + (4 * i);
2290 			r = evergreen_cs_check_reg(p, reg, idx+1+i);
2291 			if (r)
2292 				return r;
2293 		}
2294 		break;
2295 	case PACKET3_SET_CONTEXT_REG:
2296 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2297 		end_reg = 4 * pkt->count + start_reg - 4;
2298 		if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2299 		    (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2300 		    (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2301 			DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2302 			return -EINVAL;
2303 		}
2304 		for (i = 0; i < pkt->count; i++) {
2305 			reg = start_reg + (4 * i);
2306 			r = evergreen_cs_check_reg(p, reg, idx+1+i);
2307 			if (r)
2308 				return r;
2309 		}
2310 		break;
2311 	case PACKET3_SET_RESOURCE:
2312 		if (pkt->count % 8) {
2313 			DRM_ERROR("bad SET_RESOURCE\n");
2314 			return -EINVAL;
2315 		}
2316 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2317 		end_reg = 4 * pkt->count + start_reg - 4;
2318 		if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2319 		    (start_reg >= PACKET3_SET_RESOURCE_END) ||
2320 		    (end_reg >= PACKET3_SET_RESOURCE_END)) {
2321 			DRM_ERROR("bad SET_RESOURCE\n");
2322 			return -EINVAL;
2323 		}
2324 		for (i = 0; i < (pkt->count / 8); i++) {
2325 			struct radeon_bo *texture, *mipmap;
2326 			u32 toffset, moffset;
2327 			u32 size, offset;
2328 
2329 			switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2330 			case SQ_TEX_VTX_VALID_TEXTURE:
2331 				/* tex base */
2332 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2333 				if (r) {
2334 					DRM_ERROR("bad SET_RESOURCE (tex)\n");
2335 					return -EINVAL;
2336 				}
2337 				if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2338 					ib[idx+1+(i*8)+1] |=
2339 						TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2340 					if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2341 						unsigned bankw, bankh, mtaspect, tile_split;
2342 
2343 						evergreen_tiling_fields(reloc->lobj.tiling_flags,
2344 									&bankw, &bankh, &mtaspect,
2345 									&tile_split);
2346 						ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2347 						ib[idx+1+(i*8)+7] |=
2348 							TEX_BANK_WIDTH(bankw) |
2349 							TEX_BANK_HEIGHT(bankh) |
2350 							MACRO_TILE_ASPECT(mtaspect) |
2351 							TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2352 					}
2353 				}
2354 				texture = reloc->robj;
2355 				toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2356 				/* tex mip base */
2357 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2358 				if (r) {
2359 					DRM_ERROR("bad SET_RESOURCE (tex)\n");
2360 					return -EINVAL;
2361 				}
2362 				moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2363 				mipmap = reloc->robj;
2364 				r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
2365 				if (r)
2366 					return r;
2367 				ib[idx+1+(i*8)+2] += toffset;
2368 				ib[idx+1+(i*8)+3] += moffset;
2369 				break;
2370 			case SQ_TEX_VTX_VALID_BUFFER:
2371 			{
2372 				uint64_t offset64;
2373 				/* vtx base */
2374 				r = evergreen_cs_packet_next_reloc(p, &reloc);
2375 				if (r) {
2376 					DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2377 					return -EINVAL;
2378 				}
2379 				offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2380 				size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2381 				if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2382 					/* force size to size of the buffer */
2383 					dev_warn(p->dev, "vbo resource seems too big for the bo\n");
2384 					ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2385 				}
2386 
2387 				offset64 = reloc->lobj.gpu_offset + offset;
2388 				ib[idx+1+(i*8)+0] = offset64;
2389 				ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2390 						    (upper_32_bits(offset64) & 0xff);
2391 				break;
2392 			}
2393 			case SQ_TEX_VTX_INVALID_TEXTURE:
2394 			case SQ_TEX_VTX_INVALID_BUFFER:
2395 			default:
2396 				DRM_ERROR("bad SET_RESOURCE\n");
2397 				return -EINVAL;
2398 			}
2399 		}
2400 		break;
2401 	case PACKET3_SET_ALU_CONST:
2402 		/* XXX fix me ALU const buffers only */
2403 		break;
2404 	case PACKET3_SET_BOOL_CONST:
2405 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2406 		end_reg = 4 * pkt->count + start_reg - 4;
2407 		if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2408 		    (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2409 		    (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2410 			DRM_ERROR("bad SET_BOOL_CONST\n");
2411 			return -EINVAL;
2412 		}
2413 		break;
2414 	case PACKET3_SET_LOOP_CONST:
2415 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2416 		end_reg = 4 * pkt->count + start_reg - 4;
2417 		if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2418 		    (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2419 		    (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2420 			DRM_ERROR("bad SET_LOOP_CONST\n");
2421 			return -EINVAL;
2422 		}
2423 		break;
2424 	case PACKET3_SET_CTL_CONST:
2425 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2426 		end_reg = 4 * pkt->count + start_reg - 4;
2427 		if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2428 		    (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2429 		    (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2430 			DRM_ERROR("bad SET_CTL_CONST\n");
2431 			return -EINVAL;
2432 		}
2433 		break;
2434 	case PACKET3_SET_SAMPLER:
2435 		if (pkt->count % 3) {
2436 			DRM_ERROR("bad SET_SAMPLER\n");
2437 			return -EINVAL;
2438 		}
2439 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2440 		end_reg = 4 * pkt->count + start_reg - 4;
2441 		if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2442 		    (start_reg >= PACKET3_SET_SAMPLER_END) ||
2443 		    (end_reg >= PACKET3_SET_SAMPLER_END)) {
2444 			DRM_ERROR("bad SET_SAMPLER\n");
2445 			return -EINVAL;
2446 		}
2447 		break;
2448 	case PACKET3_STRMOUT_BUFFER_UPDATE:
2449 		if (pkt->count != 4) {
2450 			DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2451 			return -EINVAL;
2452 		}
2453 		/* Updating memory at DST_ADDRESS. */
2454 		if (idx_value & 0x1) {
2455 			u64 offset;
2456 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2457 			if (r) {
2458 				DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2459 				return -EINVAL;
2460 			}
2461 			offset = radeon_get_ib_value(p, idx+1);
2462 			offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2463 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2464 				DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2465 					  offset + 4, radeon_bo_size(reloc->robj));
2466 				return -EINVAL;
2467 			}
2468 			offset += reloc->lobj.gpu_offset;
2469 			ib[idx+1] = offset;
2470 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2471 		}
2472 		/* Reading data from SRC_ADDRESS. */
2473 		if (((idx_value >> 1) & 0x3) == 2) {
2474 			u64 offset;
2475 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2476 			if (r) {
2477 				DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2478 				return -EINVAL;
2479 			}
2480 			offset = radeon_get_ib_value(p, idx+3);
2481 			offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2482 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2483 				DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2484 					  offset + 4, radeon_bo_size(reloc->robj));
2485 				return -EINVAL;
2486 			}
2487 			offset += reloc->lobj.gpu_offset;
2488 			ib[idx+3] = offset;
2489 			ib[idx+4] = upper_32_bits(offset) & 0xff;
2490 		}
2491 		break;
2492 	case PACKET3_COPY_DW:
2493 		if (pkt->count != 4) {
2494 			DRM_ERROR("bad COPY_DW (invalid count)\n");
2495 			return -EINVAL;
2496 		}
2497 		if (idx_value & 0x1) {
2498 			u64 offset;
2499 			/* SRC is memory. */
2500 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2501 			if (r) {
2502 				DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2503 				return -EINVAL;
2504 			}
2505 			offset = radeon_get_ib_value(p, idx+1);
2506 			offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2507 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2508 				DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2509 					  offset + 4, radeon_bo_size(reloc->robj));
2510 				return -EINVAL;
2511 			}
2512 			offset += reloc->lobj.gpu_offset;
2513 			ib[idx+1] = offset;
2514 			ib[idx+2] = upper_32_bits(offset) & 0xff;
2515 		} else {
2516 			/* SRC is a reg. */
2517 			reg = radeon_get_ib_value(p, idx+1) << 2;
2518 			if (!evergreen_is_safe_reg(p, reg, idx+1))
2519 				return -EINVAL;
2520 		}
2521 		if (idx_value & 0x2) {
2522 			u64 offset;
2523 			/* DST is memory. */
2524 			r = evergreen_cs_packet_next_reloc(p, &reloc);
2525 			if (r) {
2526 				DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2527 				return -EINVAL;
2528 			}
2529 			offset = radeon_get_ib_value(p, idx+3);
2530 			offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2531 			if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2532 				DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2533 					  offset + 4, radeon_bo_size(reloc->robj));
2534 				return -EINVAL;
2535 			}
2536 			offset += reloc->lobj.gpu_offset;
2537 			ib[idx+3] = offset;
2538 			ib[idx+4] = upper_32_bits(offset) & 0xff;
2539 		} else {
2540 			/* DST is a reg. */
2541 			reg = radeon_get_ib_value(p, idx+3) << 2;
2542 			if (!evergreen_is_safe_reg(p, reg, idx+3))
2543 				return -EINVAL;
2544 		}
2545 		break;
2546 	case PACKET3_NOP:
2547 		break;
2548 	default:
2549 		DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2550 		return -EINVAL;
2551 	}
2552 	return 0;
2553 }
2554 
evergreen_cs_parse(struct radeon_cs_parser * p)2555 int evergreen_cs_parse(struct radeon_cs_parser *p)
2556 {
2557 	struct radeon_cs_packet pkt;
2558 	struct evergreen_cs_track *track;
2559 	u32 tmp;
2560 	int r;
2561 
2562 	if (p->track == NULL) {
2563 		/* initialize tracker, we are in kms */
2564 		track = kzalloc(sizeof(*track), GFP_KERNEL);
2565 		if (track == NULL)
2566 			return -ENOMEM;
2567 		evergreen_cs_track_init(track);
2568 		if (p->rdev->family >= CHIP_CAYMAN)
2569 			tmp = p->rdev->config.cayman.tile_config;
2570 		else
2571 			tmp = p->rdev->config.evergreen.tile_config;
2572 
2573 		switch (tmp & 0xf) {
2574 		case 0:
2575 			track->npipes = 1;
2576 			break;
2577 		case 1:
2578 		default:
2579 			track->npipes = 2;
2580 			break;
2581 		case 2:
2582 			track->npipes = 4;
2583 			break;
2584 		case 3:
2585 			track->npipes = 8;
2586 			break;
2587 		}
2588 
2589 		switch ((tmp & 0xf0) >> 4) {
2590 		case 0:
2591 			track->nbanks = 4;
2592 			break;
2593 		case 1:
2594 		default:
2595 			track->nbanks = 8;
2596 			break;
2597 		case 2:
2598 			track->nbanks = 16;
2599 			break;
2600 		}
2601 
2602 		switch ((tmp & 0xf00) >> 8) {
2603 		case 0:
2604 			track->group_size = 256;
2605 			break;
2606 		case 1:
2607 		default:
2608 			track->group_size = 512;
2609 			break;
2610 		}
2611 
2612 		switch ((tmp & 0xf000) >> 12) {
2613 		case 0:
2614 			track->row_size = 1;
2615 			break;
2616 		case 1:
2617 		default:
2618 			track->row_size = 2;
2619 			break;
2620 		case 2:
2621 			track->row_size = 4;
2622 			break;
2623 		}
2624 
2625 		p->track = track;
2626 	}
2627 	do {
2628 		r = evergreen_cs_packet_parse(p, &pkt, p->idx);
2629 		if (r) {
2630 			kfree(p->track);
2631 			p->track = NULL;
2632 			return r;
2633 		}
2634 		p->idx += pkt.count + 2;
2635 		switch (pkt.type) {
2636 		case PACKET_TYPE0:
2637 			r = evergreen_cs_parse_packet0(p, &pkt);
2638 			break;
2639 		case PACKET_TYPE2:
2640 			break;
2641 		case PACKET_TYPE3:
2642 			r = evergreen_packet3_check(p, &pkt);
2643 			break;
2644 		default:
2645 			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2646 			kfree(p->track);
2647 			p->track = NULL;
2648 			return -EINVAL;
2649 		}
2650 		if (r) {
2651 			kfree(p->track);
2652 			p->track = NULL;
2653 			return r;
2654 		}
2655 	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2656 #if 0
2657 	for (r = 0; r < p->ib->length_dw; r++) {
2658 		printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
2659 		mdelay(1);
2660 	}
2661 #endif
2662 	kfree(p->track);
2663 	p->track = NULL;
2664 	return 0;
2665 }
2666 
2667 /* vm parser */
evergreen_vm_reg_valid(u32 reg)2668 static bool evergreen_vm_reg_valid(u32 reg)
2669 {
2670 	/* context regs are fine */
2671 	if (reg >= 0x28000)
2672 		return true;
2673 
2674 	/* check config regs */
2675 	switch (reg) {
2676 	case WAIT_UNTIL:
2677 	case GRBM_GFX_INDEX:
2678 	case CP_STRMOUT_CNTL:
2679 	case CP_COHER_CNTL:
2680 	case CP_COHER_SIZE:
2681 	case VGT_VTX_VECT_EJECT_REG:
2682 	case VGT_CACHE_INVALIDATION:
2683 	case VGT_GS_VERTEX_REUSE:
2684 	case VGT_PRIMITIVE_TYPE:
2685 	case VGT_INDEX_TYPE:
2686 	case VGT_NUM_INDICES:
2687 	case VGT_NUM_INSTANCES:
2688 	case VGT_COMPUTE_DIM_X:
2689 	case VGT_COMPUTE_DIM_Y:
2690 	case VGT_COMPUTE_DIM_Z:
2691 	case VGT_COMPUTE_START_X:
2692 	case VGT_COMPUTE_START_Y:
2693 	case VGT_COMPUTE_START_Z:
2694 	case VGT_COMPUTE_INDEX:
2695 	case VGT_COMPUTE_THREAD_GROUP_SIZE:
2696 	case VGT_HS_OFFCHIP_PARAM:
2697 	case PA_CL_ENHANCE:
2698 	case PA_SU_LINE_STIPPLE_VALUE:
2699 	case PA_SC_LINE_STIPPLE_STATE:
2700 	case PA_SC_ENHANCE:
2701 	case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
2702 	case SQ_DYN_GPR_SIMD_LOCK_EN:
2703 	case SQ_CONFIG:
2704 	case SQ_GPR_RESOURCE_MGMT_1:
2705 	case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
2706 	case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
2707 	case SQ_CONST_MEM_BASE:
2708 	case SQ_STATIC_THREAD_MGMT_1:
2709 	case SQ_STATIC_THREAD_MGMT_2:
2710 	case SQ_STATIC_THREAD_MGMT_3:
2711 	case SPI_CONFIG_CNTL:
2712 	case SPI_CONFIG_CNTL_1:
2713 	case TA_CNTL_AUX:
2714 	case DB_DEBUG:
2715 	case DB_DEBUG2:
2716 	case DB_DEBUG3:
2717 	case DB_DEBUG4:
2718 	case DB_WATERMARKS:
2719 	case TD_PS_BORDER_COLOR_INDEX:
2720 	case TD_PS_BORDER_COLOR_RED:
2721 	case TD_PS_BORDER_COLOR_GREEN:
2722 	case TD_PS_BORDER_COLOR_BLUE:
2723 	case TD_PS_BORDER_COLOR_ALPHA:
2724 	case TD_VS_BORDER_COLOR_INDEX:
2725 	case TD_VS_BORDER_COLOR_RED:
2726 	case TD_VS_BORDER_COLOR_GREEN:
2727 	case TD_VS_BORDER_COLOR_BLUE:
2728 	case TD_VS_BORDER_COLOR_ALPHA:
2729 	case TD_GS_BORDER_COLOR_INDEX:
2730 	case TD_GS_BORDER_COLOR_RED:
2731 	case TD_GS_BORDER_COLOR_GREEN:
2732 	case TD_GS_BORDER_COLOR_BLUE:
2733 	case TD_GS_BORDER_COLOR_ALPHA:
2734 	case TD_HS_BORDER_COLOR_INDEX:
2735 	case TD_HS_BORDER_COLOR_RED:
2736 	case TD_HS_BORDER_COLOR_GREEN:
2737 	case TD_HS_BORDER_COLOR_BLUE:
2738 	case TD_HS_BORDER_COLOR_ALPHA:
2739 	case TD_LS_BORDER_COLOR_INDEX:
2740 	case TD_LS_BORDER_COLOR_RED:
2741 	case TD_LS_BORDER_COLOR_GREEN:
2742 	case TD_LS_BORDER_COLOR_BLUE:
2743 	case TD_LS_BORDER_COLOR_ALPHA:
2744 	case TD_CS_BORDER_COLOR_INDEX:
2745 	case TD_CS_BORDER_COLOR_RED:
2746 	case TD_CS_BORDER_COLOR_GREEN:
2747 	case TD_CS_BORDER_COLOR_BLUE:
2748 	case TD_CS_BORDER_COLOR_ALPHA:
2749 	case SQ_ESGS_RING_SIZE:
2750 	case SQ_GSVS_RING_SIZE:
2751 	case SQ_ESTMP_RING_SIZE:
2752 	case SQ_GSTMP_RING_SIZE:
2753 	case SQ_HSTMP_RING_SIZE:
2754 	case SQ_LSTMP_RING_SIZE:
2755 	case SQ_PSTMP_RING_SIZE:
2756 	case SQ_VSTMP_RING_SIZE:
2757 	case SQ_ESGS_RING_ITEMSIZE:
2758 	case SQ_ESTMP_RING_ITEMSIZE:
2759 	case SQ_GSTMP_RING_ITEMSIZE:
2760 	case SQ_GSVS_RING_ITEMSIZE:
2761 	case SQ_GS_VERT_ITEMSIZE:
2762 	case SQ_GS_VERT_ITEMSIZE_1:
2763 	case SQ_GS_VERT_ITEMSIZE_2:
2764 	case SQ_GS_VERT_ITEMSIZE_3:
2765 	case SQ_GSVS_RING_OFFSET_1:
2766 	case SQ_GSVS_RING_OFFSET_2:
2767 	case SQ_GSVS_RING_OFFSET_3:
2768 	case SQ_HSTMP_RING_ITEMSIZE:
2769 	case SQ_LSTMP_RING_ITEMSIZE:
2770 	case SQ_PSTMP_RING_ITEMSIZE:
2771 	case SQ_VSTMP_RING_ITEMSIZE:
2772 	case VGT_TF_RING_SIZE:
2773 	case SQ_ESGS_RING_BASE:
2774 	case SQ_GSVS_RING_BASE:
2775 	case SQ_ESTMP_RING_BASE:
2776 	case SQ_GSTMP_RING_BASE:
2777 	case SQ_HSTMP_RING_BASE:
2778 	case SQ_LSTMP_RING_BASE:
2779 	case SQ_PSTMP_RING_BASE:
2780 	case SQ_VSTMP_RING_BASE:
2781 	case CAYMAN_VGT_OFFCHIP_LDS_BASE:
2782 	case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2783 		return true;
2784 	default:
2785 		DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2786 		return false;
2787 	}
2788 }
2789 
evergreen_vm_packet3_check(struct radeon_device * rdev,u32 * ib,struct radeon_cs_packet * pkt)2790 static int evergreen_vm_packet3_check(struct radeon_device *rdev,
2791 				      u32 *ib, struct radeon_cs_packet *pkt)
2792 {
2793 	u32 idx = pkt->idx + 1;
2794 	u32 idx_value = ib[idx];
2795 	u32 start_reg, end_reg, reg, i;
2796 
2797 	switch (pkt->opcode) {
2798 	case PACKET3_NOP:
2799 	case PACKET3_SET_BASE:
2800 	case PACKET3_CLEAR_STATE:
2801 	case PACKET3_INDEX_BUFFER_SIZE:
2802 	case PACKET3_DISPATCH_DIRECT:
2803 	case PACKET3_DISPATCH_INDIRECT:
2804 	case PACKET3_MODE_CONTROL:
2805 	case PACKET3_SET_PREDICATION:
2806 	case PACKET3_COND_EXEC:
2807 	case PACKET3_PRED_EXEC:
2808 	case PACKET3_DRAW_INDIRECT:
2809 	case PACKET3_DRAW_INDEX_INDIRECT:
2810 	case PACKET3_INDEX_BASE:
2811 	case PACKET3_DRAW_INDEX_2:
2812 	case PACKET3_CONTEXT_CONTROL:
2813 	case PACKET3_DRAW_INDEX_OFFSET:
2814 	case PACKET3_INDEX_TYPE:
2815 	case PACKET3_DRAW_INDEX:
2816 	case PACKET3_DRAW_INDEX_AUTO:
2817 	case PACKET3_DRAW_INDEX_IMMD:
2818 	case PACKET3_NUM_INSTANCES:
2819 	case PACKET3_DRAW_INDEX_MULTI_AUTO:
2820 	case PACKET3_STRMOUT_BUFFER_UPDATE:
2821 	case PACKET3_DRAW_INDEX_OFFSET_2:
2822 	case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2823 	case PACKET3_MPEG_INDEX:
2824 	case PACKET3_WAIT_REG_MEM:
2825 	case PACKET3_MEM_WRITE:
2826 	case PACKET3_SURFACE_SYNC:
2827 	case PACKET3_EVENT_WRITE:
2828 	case PACKET3_EVENT_WRITE_EOP:
2829 	case PACKET3_EVENT_WRITE_EOS:
2830 	case PACKET3_SET_CONTEXT_REG:
2831 	case PACKET3_SET_BOOL_CONST:
2832 	case PACKET3_SET_LOOP_CONST:
2833 	case PACKET3_SET_RESOURCE:
2834 	case PACKET3_SET_SAMPLER:
2835 	case PACKET3_SET_CTL_CONST:
2836 	case PACKET3_SET_RESOURCE_OFFSET:
2837 	case PACKET3_SET_CONTEXT_REG_INDIRECT:
2838 	case PACKET3_SET_RESOURCE_INDIRECT:
2839 	case CAYMAN_PACKET3_DEALLOC_STATE:
2840 		break;
2841 	case PACKET3_COND_WRITE:
2842 		if (idx_value & 0x100) {
2843 			reg = ib[idx + 5] * 4;
2844 			if (!evergreen_vm_reg_valid(reg))
2845 				return -EINVAL;
2846 		}
2847 		break;
2848 	case PACKET3_COPY_DW:
2849 		if (idx_value & 0x2) {
2850 			reg = ib[idx + 3] * 4;
2851 			if (!evergreen_vm_reg_valid(reg))
2852 				return -EINVAL;
2853 		}
2854 		break;
2855 	case PACKET3_SET_CONFIG_REG:
2856 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2857 		end_reg = 4 * pkt->count + start_reg - 4;
2858 		if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2859 		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2860 		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2861 			DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2862 			return -EINVAL;
2863 		}
2864 		for (i = 0; i < pkt->count; i++) {
2865 			reg = start_reg + (4 * i);
2866 			if (!evergreen_vm_reg_valid(reg))
2867 				return -EINVAL;
2868 		}
2869 		break;
2870 	default:
2871 		return -EINVAL;
2872 	}
2873 	return 0;
2874 }
2875 
evergreen_ib_parse(struct radeon_device * rdev,struct radeon_ib * ib)2876 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2877 {
2878 	int ret = 0;
2879 	u32 idx = 0;
2880 	struct radeon_cs_packet pkt;
2881 
2882 	do {
2883 		pkt.idx = idx;
2884 		pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2885 		pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2886 		pkt.one_reg_wr = 0;
2887 		switch (pkt.type) {
2888 		case PACKET_TYPE0:
2889 			dev_err(rdev->dev, "Packet0 not allowed!\n");
2890 			ret = -EINVAL;
2891 			break;
2892 		case PACKET_TYPE2:
2893 			idx += 1;
2894 			break;
2895 		case PACKET_TYPE3:
2896 			pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2897 			ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
2898 			idx += pkt.count + 2;
2899 			break;
2900 		default:
2901 			dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2902 			ret = -EINVAL;
2903 			break;
2904 		}
2905 		if (ret)
2906 			break;
2907 	} while (idx < ib->length_dw);
2908 
2909 	return ret;
2910 }
2911