Lines Matching refs:radeon_get_ib_value
800 header = radeon_get_ib_value(p, idx); in r600_cs_packet_parse()
862 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in r600_cs_packet_next_reloc_mm()
908 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in r600_cs_packet_next_reloc_nomm()
981 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_packet_parse_vline()
992 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { in r600_cs_packet_parse_vline()
997 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { in r600_cs_packet_parse_vline()
1011 header = radeon_get_ib_value(p, h_idx); in r600_cs_packet_parse_vline()
1012 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in r600_cs_packet_parse_vline()
1140 tmp =radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1144 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1147 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1159 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1170 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1175 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1179 track->db_depth_size = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1184 track->vgt_strmout_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1188 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1202 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1214 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in r600_cs_check_reg()
1227 track->cb_target_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1231 track->cb_shader_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1234 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1254 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1264 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1277 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1289 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1369 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1383 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1396 track->htile_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1402 track->htile_surface = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1476 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in r600_cs_check_reg()
1579 word0 = radeon_get_ib_value(p, idx + 0); in r600_check_texture_resource()
1586 word1 = radeon_get_ib_value(p, idx + 1); in r600_check_texture_resource()
1653 word2 = radeon_get_ib_value(p, idx + 2) << 8; in r600_check_texture_resource()
1654 word3 = radeon_get_ib_value(p, idx + 3) << 8; in r600_check_texture_resource()
1656 word0 = radeon_get_ib_value(p, idx + 4); in r600_check_texture_resource()
1657 word1 = radeon_get_ib_value(p, idx + 5); in r600_check_texture_resource()
1683 word3 = radeon_get_ib_value(p, idx + 3) << 8; in r600_check_texture_resource()
1722 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1736 tmp = radeon_get_ib_value(p, idx + 1); in r600_packet3_check()
1797 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1848 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + in r600_packet3_check()
1849 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1861 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in r600_packet3_check()
1862 radeon_get_ib_value(p, idx + 2) != 0) { in r600_packet3_check()
1885 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in r600_packet3_check()
1886 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1907 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in r600_packet3_check()
1908 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1963 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { in r600_packet3_check()
1989 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), in r600_packet3_check()
1990 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), in r600_packet3_check()
2006 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); in r600_packet3_check()
2007 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; in r600_packet3_check()
2108 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2109 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2127 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2128 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2152 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2153 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2164 reg = radeon_get_ib_value(p, idx+1) << 2; in r600_packet3_check()
2176 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2177 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2188 reg = radeon_get_ib_value(p, idx+3) << 2; in r600_packet3_check()