| /linux-2.6.39/arch/x86/kernel/cpu/ |
| D | perf_event_intel.c | 158 [ C(L1D) ] = {
159 [ C(OP_READ) ] = {
160 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
161 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
163 [ C(OP_WRITE) ] = {
164 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
165 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
167 [ C(OP_PREFETCH) ] = {
168 [ C(RESULT_ACCESS) ] = 0x0,
169 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
[all …]
|
| D | perf_event_amd.c | 8 [ C(L1D) ] = {
9 [ C(OP_READ) ] = {
10 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
11 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
13 [ C(OP_WRITE) ] = {
14 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
15 [ C(RESULT_MISS) ] = 0,
17 [ C(OP_PREFETCH) ] = {
18 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
19 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
|
| /linux-2.6.39/arch/sh/kernel/cpu/sh4/ |
| D | perf_event.c | 87 #define C(x) PERF_COUNT_HW_CACHE_##x macro
94 [ C(L1D) ] = {
95 [ C(OP_READ) ] = {
96 [ C(RESULT_ACCESS) ] = 0x0001,
97 [ C(RESULT_MISS) ] = 0x0004,
99 [ C(OP_WRITE) ] = {
100 [ C(RESULT_ACCESS) ] = 0x0002,
101 [ C(RESULT_MISS) ] = 0x0005,
103 [ C(OP_PREFETCH) ] = {
104 [ C(RESULT_ACCESS) ] = 0,
[all …]
|
| /linux-2.6.39/arch/sh/kernel/cpu/sh4a/ |
| D | perf_event.c | 112 #define C(x) PERF_COUNT_HW_CACHE_##x macro
119 [ C(L1D) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0x0031,
122 [ C(RESULT_MISS) ] = 0x0032,
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = 0x0039,
126 [ C(RESULT_MISS) ] = 0x003a,
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = 0,
[all …]
|
| /linux-2.6.39/arch/arm/kernel/ |
| D | perf_event_v6.c | 80 [C(L1D)] = {
87 [C(OP_READ)] = {
88 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
89 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
91 [C(OP_WRITE)] = {
92 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
93 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
95 [C(OP_PREFETCH)] = {
96 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
97 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
[all …]
|
| D | perf_event_v7.c | 161 [C(L1D)] = {
168 [C(OP_READ)] = {
169 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
170 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
172 [C(OP_WRITE)] = {
173 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
174 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
176 [C(OP_PREFETCH)] = {
177 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
178 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
[all …]
|
| D | perf_event_xscale.c | 63 [C(L1D)] = {
64 [C(OP_READ)] = {
65 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
66 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
68 [C(OP_WRITE)] = {
69 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
70 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
72 [C(OP_PREFETCH)] = {
73 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
74 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
[all …]
|
| /linux-2.6.39/arch/mips/kernel/ |
| D | perf_event_mipsxx.c | 285 [C(L1D)] = {
292 [C(OP_READ)] = {
293 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
294 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
296 [C(OP_WRITE)] = {
297 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
298 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
300 [C(OP_PREFETCH)] = {
301 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
302 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
[all …]
|
| /linux-2.6.39/arch/sparc/kernel/ |
| D | perf_event.c | 128 #define C(x) PERF_COUNT_HW_CACHE_##x macro
164 [C(L1D)] = {
165 [C(OP_READ)] = {
166 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
167 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
169 [C(OP_WRITE)] = {
170 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
171 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
173 [C(OP_PREFETCH)] = {
174 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
|
| /linux-2.6.39/arch/powerpc/kernel/ |
| D | e500-pmu.c | 29 #define C(x) PERF_COUNT_HW_CACHE_##x macro
36 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
41 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
42 [C(OP_READ)] = { 27, 0 },
43 [C(OP_WRITE)] = { 28, 0 },
44 [C(OP_PREFETCH)] = { 29, 0 },
46 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
47 [C(OP_READ)] = { 2, 60 },
48 [C(OP_WRITE)] = { -1, -1 },
49 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
|
| D | mpc7450-pmu.c | 353 #define C(x) PERF_COUNT_HW_CACHE_##x macro
360 static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
361 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
362 [C(OP_READ)] = { 0, 0x225 },
363 [C(OP_WRITE)] = { 0, 0x227 },
364 [C(OP_PREFETCH)] = { 0, 0 },
366 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
367 [C(OP_READ)] = { 0x129, 0x115 },
368 [C(OP_WRITE)] = { -1, -1 },
369 [C(OP_PREFETCH)] = { 0x634, 0 },
[all …]
|
| D | power7-pmu.c | 307 #define C(x) PERF_COUNT_HW_CACHE_##x macro
314 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
315 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
316 [C(OP_READ)] = { 0xc880, 0x400f0 },
317 [C(OP_WRITE)] = { 0, 0x300f0 },
318 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
320 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
321 [C(OP_READ)] = { 0, 0x200fc },
322 [C(OP_WRITE)] = { -1, -1 },
323 [C(OP_PREFETCH)] = { 0x408a, 0 },
[all …]
|
| D | power6-pmu.c | 480 #define C(x) PERF_COUNT_HW_CACHE_##x macro
488 static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
489 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
490 [C(OP_READ)] = { 0x80082, 0x80080 },
491 [C(OP_WRITE)] = { 0x80086, 0x80088 },
492 [C(OP_PREFETCH)] = { 0x810a4, 0 },
494 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
495 [C(OP_READ)] = { 0, 0x100056 },
496 [C(OP_WRITE)] = { -1, -1 },
497 [C(OP_PREFETCH)] = { 0x4008c, 0 },
[all …]
|
| D | ppc970-pmu.c | 432 #define C(x) PERF_COUNT_HW_CACHE_##x macro
439 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
440 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
441 [C(OP_READ)] = { 0x8810, 0x3810 },
442 [C(OP_WRITE)] = { 0x7810, 0x813 },
443 [C(OP_PREFETCH)] = { 0x731, 0 },
445 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
446 [C(OP_READ)] = { 0, 0 },
447 [C(OP_WRITE)] = { -1, -1 },
448 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
|
| D | power4-pmu.c | 552 #define C(x) PERF_COUNT_HW_CACHE_##x macro
559 static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
560 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
561 [C(OP_READ)] = { 0x8c10, 0x3c10 },
562 [C(OP_WRITE)] = { 0x7c10, 0xc13 },
563 [C(OP_PREFETCH)] = { 0xc35, 0 },
565 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
566 [C(OP_READ)] = { 0, 0 },
567 [C(OP_WRITE)] = { -1, -1 },
568 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
|
| /linux-2.6.39/scripts/rt-tester/ |
| D | t5-l4-pi-boost-deboost-setsched.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedfifo: 1: 81
56 C: schedfifo: 2: 82
57 C: schedfifo: 3: 83
58 C: schedfifo: 4: 84
61 C: locknowait: 0: 0
65 C: locknowait: 1: 1
[all …]
|
| D | t5-l4-pi-boost-deboost.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedfifo: 1: 81
56 C: schedfifo: 2: 82
57 C: schedfifo: 3: 83
58 C: schedfifo: 4: 84
61 C: locknowait: 0: 0
65 C: locknowait: 1: 1
[all …]
|
| D | t4-l2-pi-deboost.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedother: 1: 0
56 C: schedfifo: 2: 82
57 C: schedfifo: 3: 83
60 C: locknowait: 0: 0
64 C: locknowait: 1: 1
68 C: lockintnowait: 3: 0
[all …]
|
| D | t2-l2-2rt-deadlock.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedfifo: 0: 80
55 C: schedfifo: 1: 80
58 C: locknowait: 0: 0
62 C: locknowait: 1: 1
66 C: lockintnowait: 0: 1
70 C: lockintnowait: 1: 0
74 C: signal: 1: 0
[all …]
|
| D | t3-l1-pi-steal.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedfifo: 1: 80
56 C: schedfifo: 2: 81
59 C: lock: 0: 0
63 C: lock: 1: 0
68 C: unlock: 0: 0
75 C: lock: 2: 0
[all …]
|
| D | t2-l1-2rt-sameprio.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedfifo: 0: 80
55 C: schedfifo: 1: 80
58 C: locknowait: 0: 0
59 C: locknowait: 1: 0
65 C: unlock: 0: 0
73 C: unlock: 1: 0
77 C: locknowait: 1: 0
[all …]
|
| D | t3-l1-pi-1rt.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedother: 1: 0
56 C: schedfifo: 2: 82
59 C: locknowait: 0: 0
63 C: locknowait: 1: 0
68 C: locknowait: 2: 0
73 C: unlock: 0: 0
[all …]
|
| D | t3-l1-pi-3rt.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedfifo: 0: 80
55 C: schedfifo: 1: 81
56 C: schedfifo: 2: 82
59 C: locknowait: 0: 0
63 C: locknowait: 1: 0
68 C: locknowait: 2: 0
73 C: unlock: 0: 0
[all …]
|
| D | t3-l2-pi.tst | 4 # Op: C(ommand)/T(est)/W(ait)
9 # C: lock: 0: 0
50 C: resetevent: 0: 0
54 C: schedother: 0: 0
55 C: schedother: 1: 0
56 C: schedfifo: 2: 82
59 C: locknowait: 0: 0
63 C: locknowait: 1: 0
68 C: locknowait: 2: 0
73 C: unlock: 0: 0
[all …]
|
| /linux-2.6.39/arch/frv/include/asm/ |
| D | irc-regs.h | 31 #define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; }) argument
33 #define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0) argument
35 #define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; }) argument
36 #define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0) argument
37 #define __clr_MASK(C) do { __reg(0xfeff9820) &= ~(1 << ((C)+16)); mb(); } while(0) argument
|