Lines Matching refs:C
8 [ C(L1D) ] = {
9 [ C(OP_READ) ] = {
10 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
11 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
13 [ C(OP_WRITE) ] = {
14 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
15 [ C(RESULT_MISS) ] = 0,
17 [ C(OP_PREFETCH) ] = {
18 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
19 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
22 [ C(L1I ) ] = {
23 [ C(OP_READ) ] = {
24 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
25 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
27 [ C(OP_WRITE) ] = {
28 [ C(RESULT_ACCESS) ] = -1,
29 [ C(RESULT_MISS) ] = -1,
31 [ C(OP_PREFETCH) ] = {
32 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
33 [ C(RESULT_MISS) ] = 0,
36 [ C(LL ) ] = {
37 [ C(OP_READ) ] = {
38 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
39 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
41 [ C(OP_WRITE) ] = {
42 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
43 [ C(RESULT_MISS) ] = 0,
45 [ C(OP_PREFETCH) ] = {
46 [ C(RESULT_ACCESS) ] = 0,
47 [ C(RESULT_MISS) ] = 0,
50 [ C(DTLB) ] = {
51 [ C(OP_READ) ] = {
52 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
53 [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
55 [ C(OP_WRITE) ] = {
56 [ C(RESULT_ACCESS) ] = 0,
57 [ C(RESULT_MISS) ] = 0,
59 [ C(OP_PREFETCH) ] = {
60 [ C(RESULT_ACCESS) ] = 0,
61 [ C(RESULT_MISS) ] = 0,
64 [ C(ITLB) ] = {
65 [ C(OP_READ) ] = {
66 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
67 [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
69 [ C(OP_WRITE) ] = {
70 [ C(RESULT_ACCESS) ] = -1,
71 [ C(RESULT_MISS) ] = -1,
73 [ C(OP_PREFETCH) ] = {
74 [ C(RESULT_ACCESS) ] = -1,
75 [ C(RESULT_MISS) ] = -1,
78 [ C(BPU ) ] = {
79 [ C(OP_READ) ] = {
80 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
81 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
83 [ C(OP_WRITE) ] = {
84 [ C(RESULT_ACCESS) ] = -1,
85 [ C(RESULT_MISS) ] = -1,
87 [ C(OP_PREFETCH) ] = {
88 [ C(RESULT_ACCESS) ] = -1,
89 [ C(RESULT_MISS) ] = -1,