Lines Matching refs:C
158 [ C(L1D) ] = {
159 [ C(OP_READ) ] = {
160 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
161 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
163 [ C(OP_WRITE) ] = {
164 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
165 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
167 [ C(OP_PREFETCH) ] = {
168 [ C(RESULT_ACCESS) ] = 0x0,
169 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
172 [ C(L1I ) ] = {
173 [ C(OP_READ) ] = {
174 [ C(RESULT_ACCESS) ] = 0x0,
175 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
177 [ C(OP_WRITE) ] = {
178 [ C(RESULT_ACCESS) ] = -1,
179 [ C(RESULT_MISS) ] = -1,
181 [ C(OP_PREFETCH) ] = {
182 [ C(RESULT_ACCESS) ] = 0x0,
183 [ C(RESULT_MISS) ] = 0x0,
186 [ C(LL ) ] = {
187 [ C(OP_READ) ] = {
189 [ C(RESULT_ACCESS) ] = 0x01b7,
191 [ C(RESULT_MISS) ] = 0x01b7,
193 [ C(OP_WRITE) ] = {
195 [ C(RESULT_ACCESS) ] = 0x01b7,
197 [ C(RESULT_MISS) ] = 0x01b7,
199 [ C(OP_PREFETCH) ] = {
201 [ C(RESULT_ACCESS) ] = 0x01b7,
203 [ C(RESULT_MISS) ] = 0x01b7,
206 [ C(DTLB) ] = {
207 [ C(OP_READ) ] = {
208 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
209 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
211 [ C(OP_WRITE) ] = {
212 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
213 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
215 [ C(OP_PREFETCH) ] = {
216 [ C(RESULT_ACCESS) ] = 0x0,
217 [ C(RESULT_MISS) ] = 0x0,
220 [ C(ITLB) ] = {
221 [ C(OP_READ) ] = {
222 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
223 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
225 [ C(OP_WRITE) ] = {
226 [ C(RESULT_ACCESS) ] = -1,
227 [ C(RESULT_MISS) ] = -1,
229 [ C(OP_PREFETCH) ] = {
230 [ C(RESULT_ACCESS) ] = -1,
231 [ C(RESULT_MISS) ] = -1,
234 [ C(BPU ) ] = {
235 [ C(OP_READ) ] = {
236 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
237 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
239 [ C(OP_WRITE) ] = {
240 [ C(RESULT_ACCESS) ] = -1,
241 [ C(RESULT_MISS) ] = -1,
243 [ C(OP_PREFETCH) ] = {
244 [ C(RESULT_ACCESS) ] = -1,
245 [ C(RESULT_MISS) ] = -1,
255 [ C(L1D) ] = {
256 [ C(OP_READ) ] = {
257 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
258 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
260 [ C(OP_WRITE) ] = {
261 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
262 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
264 [ C(OP_PREFETCH) ] = {
265 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
266 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
269 [ C(L1I ) ] = {
270 [ C(OP_READ) ] = {
271 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
272 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
274 [ C(OP_WRITE) ] = {
275 [ C(RESULT_ACCESS) ] = -1,
276 [ C(RESULT_MISS) ] = -1,
278 [ C(OP_PREFETCH) ] = {
279 [ C(RESULT_ACCESS) ] = 0x0,
280 [ C(RESULT_MISS) ] = 0x0,
283 [ C(LL ) ] = {
284 [ C(OP_READ) ] = {
286 [ C(RESULT_ACCESS) ] = 0x01b7,
288 [ C(RESULT_MISS) ] = 0x01b7,
294 [ C(OP_WRITE) ] = {
296 [ C(RESULT_ACCESS) ] = 0x01b7,
298 [ C(RESULT_MISS) ] = 0x01b7,
300 [ C(OP_PREFETCH) ] = {
302 [ C(RESULT_ACCESS) ] = 0x01b7,
304 [ C(RESULT_MISS) ] = 0x01b7,
307 [ C(DTLB) ] = {
308 [ C(OP_READ) ] = {
309 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
310 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
312 [ C(OP_WRITE) ] = {
313 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
314 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
316 [ C(OP_PREFETCH) ] = {
317 [ C(RESULT_ACCESS) ] = 0x0,
318 [ C(RESULT_MISS) ] = 0x0,
321 [ C(ITLB) ] = {
322 [ C(OP_READ) ] = {
323 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
324 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
326 [ C(OP_WRITE) ] = {
327 [ C(RESULT_ACCESS) ] = -1,
328 [ C(RESULT_MISS) ] = -1,
330 [ C(OP_PREFETCH) ] = {
331 [ C(RESULT_ACCESS) ] = -1,
332 [ C(RESULT_MISS) ] = -1,
335 [ C(BPU ) ] = {
336 [ C(OP_READ) ] = {
337 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
338 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
340 [ C(OP_WRITE) ] = {
341 [ C(RESULT_ACCESS) ] = -1,
342 [ C(RESULT_MISS) ] = -1,
344 [ C(OP_PREFETCH) ] = {
345 [ C(RESULT_ACCESS) ] = -1,
346 [ C(RESULT_MISS) ] = -1,
388 [ C(LL ) ] = {
389 [ C(OP_READ) ] = {
390 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
391 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
393 [ C(OP_WRITE) ] = {
394 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
395 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
399 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
409 [ C(L1D) ] = {
410 [ C(OP_READ) ] = {
411 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
412 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
414 [ C(OP_WRITE) ] = {
415 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
416 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
418 [ C(OP_PREFETCH) ] = {
419 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
420 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
423 [ C(L1I ) ] = {
424 [ C(OP_READ) ] = {
425 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
426 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
428 [ C(OP_WRITE) ] = {
429 [ C(RESULT_ACCESS) ] = -1,
430 [ C(RESULT_MISS) ] = -1,
432 [ C(OP_PREFETCH) ] = {
433 [ C(RESULT_ACCESS) ] = 0x0,
434 [ C(RESULT_MISS) ] = 0x0,
437 [ C(LL ) ] = {
438 [ C(OP_READ) ] = {
440 [ C(RESULT_ACCESS) ] = 0x01b7,
442 [ C(RESULT_MISS) ] = 0x01b7,
448 [ C(OP_WRITE) ] = {
450 [ C(RESULT_ACCESS) ] = 0x01b7,
452 [ C(RESULT_MISS) ] = 0x01b7,
454 [ C(OP_PREFETCH) ] = {
456 [ C(RESULT_ACCESS) ] = 0x01b7,
458 [ C(RESULT_MISS) ] = 0x01b7,
461 [ C(DTLB) ] = {
462 [ C(OP_READ) ] = {
463 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
464 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
466 [ C(OP_WRITE) ] = {
467 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
468 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
470 [ C(OP_PREFETCH) ] = {
471 [ C(RESULT_ACCESS) ] = 0x0,
472 [ C(RESULT_MISS) ] = 0x0,
475 [ C(ITLB) ] = {
476 [ C(OP_READ) ] = {
477 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
478 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
480 [ C(OP_WRITE) ] = {
481 [ C(RESULT_ACCESS) ] = -1,
482 [ C(RESULT_MISS) ] = -1,
484 [ C(OP_PREFETCH) ] = {
485 [ C(RESULT_ACCESS) ] = -1,
486 [ C(RESULT_MISS) ] = -1,
489 [ C(BPU ) ] = {
490 [ C(OP_READ) ] = {
491 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
492 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
494 [ C(OP_WRITE) ] = {
495 [ C(RESULT_ACCESS) ] = -1,
496 [ C(RESULT_MISS) ] = -1,
498 [ C(OP_PREFETCH) ] = {
499 [ C(RESULT_ACCESS) ] = -1,
500 [ C(RESULT_MISS) ] = -1,
510 [ C(L1D) ] = {
511 [ C(OP_READ) ] = {
512 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
513 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
515 [ C(OP_WRITE) ] = {
516 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
517 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
519 [ C(OP_PREFETCH) ] = {
520 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
521 [ C(RESULT_MISS) ] = 0,
524 [ C(L1I ) ] = {
525 [ C(OP_READ) ] = {
526 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
527 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
529 [ C(OP_WRITE) ] = {
530 [ C(RESULT_ACCESS) ] = -1,
531 [ C(RESULT_MISS) ] = -1,
533 [ C(OP_PREFETCH) ] = {
534 [ C(RESULT_ACCESS) ] = 0,
535 [ C(RESULT_MISS) ] = 0,
538 [ C(LL ) ] = {
539 [ C(OP_READ) ] = {
540 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
541 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
543 [ C(OP_WRITE) ] = {
544 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
545 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
547 [ C(OP_PREFETCH) ] = {
548 [ C(RESULT_ACCESS) ] = 0,
549 [ C(RESULT_MISS) ] = 0,
552 [ C(DTLB) ] = {
553 [ C(OP_READ) ] = {
554 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
555 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
557 [ C(OP_WRITE) ] = {
558 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
559 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
561 [ C(OP_PREFETCH) ] = {
562 [ C(RESULT_ACCESS) ] = 0,
563 [ C(RESULT_MISS) ] = 0,
566 [ C(ITLB) ] = {
567 [ C(OP_READ) ] = {
568 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
569 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
571 [ C(OP_WRITE) ] = {
572 [ C(RESULT_ACCESS) ] = -1,
573 [ C(RESULT_MISS) ] = -1,
575 [ C(OP_PREFETCH) ] = {
576 [ C(RESULT_ACCESS) ] = -1,
577 [ C(RESULT_MISS) ] = -1,
580 [ C(BPU ) ] = {
581 [ C(OP_READ) ] = {
582 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
583 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
585 [ C(OP_WRITE) ] = {
586 [ C(RESULT_ACCESS) ] = -1,
587 [ C(RESULT_MISS) ] = -1,
589 [ C(OP_PREFETCH) ] = {
590 [ C(RESULT_ACCESS) ] = -1,
591 [ C(RESULT_MISS) ] = -1,
601 [ C(L1D) ] = {
602 [ C(OP_READ) ] = {
603 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
604 [ C(RESULT_MISS) ] = 0,
606 [ C(OP_WRITE) ] = {
607 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
608 [ C(RESULT_MISS) ] = 0,
610 [ C(OP_PREFETCH) ] = {
611 [ C(RESULT_ACCESS) ] = 0x0,
612 [ C(RESULT_MISS) ] = 0,
615 [ C(L1I ) ] = {
616 [ C(OP_READ) ] = {
617 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
618 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
620 [ C(OP_WRITE) ] = {
621 [ C(RESULT_ACCESS) ] = -1,
622 [ C(RESULT_MISS) ] = -1,
624 [ C(OP_PREFETCH) ] = {
625 [ C(RESULT_ACCESS) ] = 0,
626 [ C(RESULT_MISS) ] = 0,
629 [ C(LL ) ] = {
630 [ C(OP_READ) ] = {
631 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
632 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
634 [ C(OP_WRITE) ] = {
635 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
636 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
638 [ C(OP_PREFETCH) ] = {
639 [ C(RESULT_ACCESS) ] = 0,
640 [ C(RESULT_MISS) ] = 0,
643 [ C(DTLB) ] = {
644 [ C(OP_READ) ] = {
645 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
646 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
648 [ C(OP_WRITE) ] = {
649 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
650 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
652 [ C(OP_PREFETCH) ] = {
653 [ C(RESULT_ACCESS) ] = 0,
654 [ C(RESULT_MISS) ] = 0,
657 [ C(ITLB) ] = {
658 [ C(OP_READ) ] = {
659 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
660 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
662 [ C(OP_WRITE) ] = {
663 [ C(RESULT_ACCESS) ] = -1,
664 [ C(RESULT_MISS) ] = -1,
666 [ C(OP_PREFETCH) ] = {
667 [ C(RESULT_ACCESS) ] = -1,
668 [ C(RESULT_MISS) ] = -1,
671 [ C(BPU ) ] = {
672 [ C(OP_READ) ] = {
673 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
674 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
676 [ C(OP_WRITE) ] = {
677 [ C(RESULT_ACCESS) ] = -1,
678 [ C(RESULT_MISS) ] = -1,
680 [ C(OP_PREFETCH) ] = {
681 [ C(RESULT_ACCESS) ] = -1,
682 [ C(RESULT_MISS) ] = -1,