Lines Matching refs:C
128 #define C(x) PERF_COUNT_HW_CACHE_##x macro
164 [C(L1D)] = {
165 [C(OP_READ)] = {
166 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
167 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
169 [C(OP_WRITE)] = {
170 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
171 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
173 [C(OP_PREFETCH)] = {
174 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
175 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
178 [C(L1I)] = {
179 [C(OP_READ)] = {
180 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
181 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
183 [ C(OP_WRITE) ] = {
184 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
185 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
187 [ C(OP_PREFETCH) ] = {
188 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
189 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
192 [C(LL)] = {
193 [C(OP_READ)] = {
194 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
195 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
197 [C(OP_WRITE)] = {
198 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
199 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
201 [C(OP_PREFETCH)] = {
202 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
203 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
206 [C(DTLB)] = {
207 [C(OP_READ)] = {
208 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
209 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
211 [ C(OP_WRITE) ] = {
212 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
213 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
215 [ C(OP_PREFETCH) ] = {
216 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
217 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
220 [C(ITLB)] = {
221 [C(OP_READ)] = {
222 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
223 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
225 [ C(OP_WRITE) ] = {
226 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
227 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
229 [ C(OP_PREFETCH) ] = {
230 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
231 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
234 [C(BPU)] = {
235 [C(OP_READ)] = {
236 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
237 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
239 [ C(OP_WRITE) ] = {
240 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
241 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
243 [ C(OP_PREFETCH) ] = {
244 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
245 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
279 [C(L1D)] = {
280 [C(OP_READ)] = {
281 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
282 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
284 [C(OP_WRITE)] = {
285 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
286 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
288 [C(OP_PREFETCH)] = {
289 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
290 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
293 [C(L1I)] = {
294 [C(OP_READ)] = {
295 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
296 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
298 [ C(OP_WRITE) ] = {
299 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
300 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
302 [ C(OP_PREFETCH) ] = {
303 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
304 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
307 [C(LL)] = {
308 [C(OP_READ)] = {
309 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
310 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
312 [C(OP_WRITE)] = {
313 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
314 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
316 [C(OP_PREFETCH)] = {
317 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
318 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
321 [C(DTLB)] = {
322 [C(OP_READ)] = {
323 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
324 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
326 [ C(OP_WRITE) ] = {
327 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
328 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
330 [ C(OP_PREFETCH) ] = {
331 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
332 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
335 [C(ITLB)] = {
336 [C(OP_READ)] = {
337 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
338 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
340 [ C(OP_WRITE) ] = {
341 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
342 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
344 [ C(OP_PREFETCH) ] = {
345 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
346 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
349 [C(BPU)] = {
350 [C(OP_READ)] = {
351 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
352 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
354 [ C(OP_WRITE) ] = {
355 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
356 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
358 [ C(OP_PREFETCH) ] = {
359 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
360 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
391 [C(L1D)] = {
392 [C(OP_READ)] = {
393 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
394 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
396 [C(OP_WRITE)] = {
397 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
398 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
400 [C(OP_PREFETCH)] = {
401 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
402 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
405 [C(L1I)] = {
406 [C(OP_READ)] = {
407 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
408 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
410 [ C(OP_WRITE) ] = {
411 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
412 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
414 [ C(OP_PREFETCH) ] = {
415 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
416 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
419 [C(LL)] = {
420 [C(OP_READ)] = {
421 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
422 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
424 [C(OP_WRITE)] = {
425 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
426 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
428 [C(OP_PREFETCH)] = {
429 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
430 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
433 [C(DTLB)] = {
434 [C(OP_READ)] = {
435 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
436 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
438 [ C(OP_WRITE) ] = {
439 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
440 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
442 [ C(OP_PREFETCH) ] = {
443 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
444 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
447 [C(ITLB)] = {
448 [C(OP_READ)] = {
449 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
450 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
452 [ C(OP_WRITE) ] = {
453 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
454 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
456 [ C(OP_PREFETCH) ] = {
457 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
458 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
461 [C(BPU)] = {
462 [C(OP_READ)] = {
463 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
464 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
466 [ C(OP_WRITE) ] = {
467 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
468 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
470 [ C(OP_PREFETCH) ] = {
471 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
472 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },