Searched refs:ddb_in32 (Results 1 – 15 of 15) sorted by relevance
33 t = ddb_in32(offset); in nile4_map_irq()47 t = ddb_in32(DDB_INTCTRL); in nile4_map_irq_all()51 t = ddb_in32(DDB_INTCTRL + 4); in nile4_map_irq_all()66 t = ddb_in32(offset); in nile4_enable_irq()80 t = ddb_in32(offset); in nile4_disable_irq()100 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_enable_irq_output()109 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_disable_irq_output()118 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_polarity()130 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_level_or_edge()154 reg = ddb_in32(DDB_PCIINIT0); in nile4_i8259_iack()[all …]
58 t = ddb_in32(DDB_PCICTRL + 4); in ddb_machine_restart()62 t = ddb_in32(DDB_CPUSTAT); in ddb_machine_restart()207 db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) == in ddb5476_board_init()211 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); in ddb5476_board_init()226 db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) == in ddb5476_board_init()231 db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) == in ddb5476_board_init()
77 swap->pdar_backup = ddb_in32(swap->pdar); in ddb_access_config_base()78 swap->pmr_backup = ddb_in32(swap->pmr); in ddb_access_config_base()
114 temp = ddb_in32(DDB_PCICTRL+4); in ddb_pci_reset_bus()
35 t = ddb_in32(offset); in nile4_map_irq()49 t = ddb_in32(DDB_INTCTRL); in nile4_map_irq_all()53 t = ddb_in32(DDB_INTCTRL + 4); in nile4_map_irq_all()73 t = ddb_in32(offset); in nile4_enable_irq()91 t = ddb_in32(offset); in nile4_disable_irq()111 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_enable_irq_output()120 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_disable_irq_output()129 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_polarity()141 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_level_or_edge()166 reg = ddb_in32(DDB_PCIINIT0); in nile4_i8259_iack()[all …]
74 swap->pdar_backup = ddb_in32(swap->pdar); in ddb_access_config_base()75 swap->pmr_backup = ddb_in32(swap->pmr); in ddb_access_config_base()
88 temp = ddb_in32(DDB_PCICTRL + 4); in ddb_pci_reset_bus()
68 reg_value = ddb_in32(pci); in set_pci_int_attr()152 reg = ddb_in32(DDB_PCIINIT10); in i8259_interrupt_ack()172 db_assert(ddb_in32(DDB_INT2STAT) == 0); in vrc5477_irq_dispatch()173 db_assert(ddb_in32(DDB_INT3STAT) == 0); in vrc5477_irq_dispatch()174 db_assert(ddb_in32(DDB_INT4STAT) == 0); in vrc5477_irq_dispatch()175 db_assert(ddb_in32(DDB_NMISTAT) == 0); in vrc5477_irq_dispatch()177 if (ddb_in32(DDB_INT1STAT) != 0) { in vrc5477_irq_dispatch()184 intStatus = ddb_in32(DDB_INT0STAT); in vrc5477_irq_dispatch()
63 t = ddb_in32(DDB_CPUSTAT); in ddb_machine_restart()105 t1 = ddb_in32(SP_TIMER_BASE+8); in detect_bus_frequency()111 t2 = ddb_in32(SP_TIMER_BASE+8); in detect_bus_frequency()225 db_assert(ddb_in32(DDB_SDRAM0) == in ddb5477_board_init()229 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); in ddb5477_board_init()254 db_assert(ddb_in32(DDB_VRC5477) == in ddb5477_board_init()258 db_assert(ddb_in32(DDB_BOOTCS) == in ddb5477_board_init()
131 reg_value = ddb_in32(reg_index); in ll_vrc5477_irq_route()148 reg_value = ddb_in32(reg_index); in ll_vrc5477_irq_enable()164 reg_value = ddb_in32(reg_index); in ll_vrc5477_irq_disable()
180 temp = ddb_in32(DDB_PCICTL0_H); in ddb_pci_reset_bus()186 temp = ddb_in32(DDB_PCICTL1_H); in ddb_pci_reset_bus()
83 swap->pdar_backup = ddb_in32(swap->pdar); in ddb_access_config_base()84 swap->pmr_backup = ddb_in32(swap->pmr); in ddb_access_config_base()
112 ddb_in32(pdar); in ddb_set_pdar()113 ddb_in32(pdar + 4); in ddb_set_pdar()
135 board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf)); in ddb5477_runtime_detection()
192 static inline u32 ddb_in32(u32 offset) in ddb_in32() function