1 /***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * arch/mips/ddb5xxx/ddb5477/setup.c
7 * Setup file for DDB5477.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/kdev_t.h>
18 #include <linux/types.h>
19 #include <linux/console.h>
20 #include <linux/sched.h>
21 #include <linux/pci.h>
22 #include <linux/ide.h>
23 #include <linux/fs.h> /* for ROOT_DEV */
24 #include <linux/ioport.h>
25 #include <linux/param.h> /* for HZ */
26
27 #include <asm/cpu.h>
28 #include <asm/bootinfo.h>
29 #include <asm/addrspace.h>
30 #include <asm/time.h>
31 #include <asm/bcache.h>
32 #include <asm/irq.h>
33 #include <asm/reboot.h>
34 #include <asm/gdb-stub.h>
35 #include <asm/traps.h>
36 #include <asm/debug.h>
37 #ifdef CONFIG_PC_KEYB
38 #include <asm/keyboard.h>
39 #endif
40
41 #include <asm/ddb5xxx/ddb5xxx.h>
42
43 #include "lcd44780.h"
44
45
46 #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
47
48 #define SP_TIMER_BASE DDB_SPT1CTRL_L
49 #define SP_TIMER_IRQ VRC5477_IRQ_SPT1
50
51 static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
52
ddb_machine_restart(char * command)53 static void ddb_machine_restart(char *command)
54 {
55 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
56
57 u32 t;
58
59 /* PCI cold reset */
60 ddb_pci_reset_bus();
61
62 /* CPU cold reset */
63 t = ddb_in32(DDB_CPUSTAT);
64 db_assert((t&1));
65 ddb_out32(DDB_CPUSTAT, t);
66
67 /* Call the PROM */
68 back_to_prom();
69 }
70
ddb_machine_halt(void)71 static void ddb_machine_halt(void)
72 {
73 printk("DDB Vrc-5477 halted.\n");
74 while (1);
75 }
76
ddb_machine_power_off(void)77 static void ddb_machine_power_off(void)
78 {
79 printk("DDB Vrc-5477 halted. Please turn off the power.\n");
80 while (1);
81 }
82
detect_bus_frequency(unsigned long rtc_base)83 static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
84 {
85 unsigned int freq;
86 unsigned char c;
87 unsigned int t1, t2;
88 unsigned i;
89
90 ddb_out32(SP_TIMER_BASE, 0xffffffff);
91 ddb_out32(SP_TIMER_BASE+4, 0x1);
92 ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
93
94 /* check if rtc is running */
95 c= *(volatile unsigned char*)rtc_base;
96 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
97 if (c == *(volatile unsigned char*)rtc_base) {
98 printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
99 return 83333000;
100 }
101
102 c= *(volatile unsigned char*)rtc_base;
103 while (c == *(volatile unsigned char*)rtc_base);
104 /* we are now at the turn of 1/100th second, if no error. */
105 t1 = ddb_in32(SP_TIMER_BASE+8);
106
107 for (i=0; i< 10; i++) {
108 c= *(volatile unsigned char*)rtc_base;
109 while (c == *(volatile unsigned char*)rtc_base);
110 /* we are now at the turn of another 1/100th second */
111 t2 = ddb_in32(SP_TIMER_BASE+8);
112 }
113
114 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
115
116 freq = (t1 - t2)*10;
117 printk("DDB bus frequency detection : %u \n", freq);
118 return freq;
119 }
120
121 extern void rtc_ds1386_init(unsigned long base);
ddb_time_init(void)122 static void __init ddb_time_init(void)
123 {
124 unsigned long rtc_base;
125 unsigned int i;
126
127 /* we have ds1396 RTC chip */
128 if (mips_machtype == MACH_NEC_ROCKHOPPER
129 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
130 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
131 } else {
132 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
133 }
134 rtc_ds1386_init(rtc_base);
135
136 /* do we need to do run-time detection of bus speed? */
137 if (bus_frequency == 0) {
138 bus_frequency = detect_bus_frequency(rtc_base);
139 }
140
141 /* mips_hpt_frequency is 1/2 of the cpu core freq */
142 i = (read_c0_config() >> 28 ) & 7;
143 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
144 i = 4;
145 mips_hpt_frequency = bus_frequency*(i+4)/4;
146 }
147
148 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
ddb_timer_setup(struct irqaction * irq)149 static void __init ddb_timer_setup(struct irqaction *irq)
150 {
151 #if defined(USE_CPU_COUNTER_TIMER)
152 unsigned int count;
153
154 /* we are using the cpu counter for timer interrupts */
155 setup_irq(CPU_IRQ_BASE + 7, irq);
156
157 #else
158
159 /* if we use Special purpose timer 1 */
160 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
161 ddb_out32(SP_TIMER_BASE+4, 0x1);
162 setup_irq(SP_TIMER_IRQ, irq);
163
164 #endif
165 }
166
167 static void ddb5477_board_init(void);
168 extern void ddb5477_irq_setup(void);
169
170 #if defined(CONFIG_BLK_DEV_INITRD)
171 extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
172 #endif
173
ddb_setup(void)174 void __init ddb_setup(void)
175 {
176 extern int panic_timeout;
177 #ifdef CONFIG_BLK_DEV_IDE
178 extern struct ide_ops std_ide_ops;
179 #endif
180
181 /* initialize board - we don't trust the loader */
182 ddb5477_board_init();
183
184 irq_setup = ddb5477_irq_setup;
185 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
186
187 board_time_init = ddb_time_init;
188 board_timer_setup = ddb_timer_setup;
189
190 _machine_restart = ddb_machine_restart;
191 _machine_halt = ddb_machine_halt;
192 _machine_power_off = ddb_machine_power_off;
193
194 /* setup resource limits */
195 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
196 iomem_resource.end = 0xffffffff;
197
198 /* Reboot on panic */
199 panic_timeout = 180;
200
201 #ifdef CONFIG_BLK_DEV_IDE
202 ide_ops = &std_ide_ops;
203 #endif
204
205
206 #ifdef CONFIG_FB
207 conswitchp = &dummy_con;
208 #endif
209
210 #if defined(CONFIG_BLK_DEV_INITRD)
211 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
212 initrd_start = (unsigned long)&__rd_start;
213 initrd_end = (unsigned long)&__rd_end;
214 #endif
215 }
216
ddb5477_board_init()217 static void __init ddb5477_board_init()
218 {
219 #ifdef CONFIG_PC_KEYB
220 extern struct kbd_ops std_kbd_ops;
221 #endif
222 /* ----------- setup PDARs ------------ */
223
224 /* SDRAM should have been set */
225 db_assert(ddb_in32(DDB_SDRAM0) ==
226 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
227
228 /* SDRAM1 should be turned off. What is this for anyway ? */
229 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
230
231 /* Setup local bus. */
232
233 /* Flash U12 PDAR and timing. */
234 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
235 ddb_out32(DDB_LCST0, 0x00090842);
236
237 /* We need to setup LCS1 and LCS2 differently based on the
238 board_version */
239 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
240 /* Flash U13 PDAR and timing. */
241 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
242 ddb_out32(DDB_LCST1, 0x00090842);
243
244 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
245 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
246 } else {
247 /* misc */
248 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
249 /* mezzanie (?) */
250 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
251 }
252
253 /* verify VRC5477 base addr */
254 db_assert(ddb_in32(DDB_VRC5477) ==
255 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
256
257 /* verify BOOT ROM addr */
258 db_assert(ddb_in32(DDB_BOOTCS) ==
259 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
260
261 /* setup PCI windows - window0 for MEM/config, window1 for IO */
262 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
263 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
264 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
265 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
266
267 /* ------------ reset PCI bus and BARs ----------------- */
268 ddb_pci_reset_bus();
269
270 ddb_out32(DDB_BARM010, 0x00000008);
271 ddb_out32(DDB_BARM011, 0x00000008);
272
273 ddb_out32(DDB_BARC0, 0xffffffff);
274 ddb_out32(DDB_BARM230, 0xffffffff);
275 ddb_out32(DDB_BAR00, 0xffffffff);
276 ddb_out32(DDB_BAR10, 0xffffffff);
277 ddb_out32(DDB_BAR20, 0xffffffff);
278 ddb_out32(DDB_BAR30, 0xffffffff);
279 ddb_out32(DDB_BAR40, 0xffffffff);
280 ddb_out32(DDB_BAR50, 0xffffffff);
281 ddb_out32(DDB_BARB0, 0xffffffff);
282
283 ddb_out32(DDB_BARC1, 0xffffffff);
284 ddb_out32(DDB_BARM231, 0xffffffff);
285 ddb_out32(DDB_BAR01, 0xffffffff);
286 ddb_out32(DDB_BAR11, 0xffffffff);
287 ddb_out32(DDB_BAR21, 0xffffffff);
288 ddb_out32(DDB_BAR31, 0xffffffff);
289 ddb_out32(DDB_BAR41, 0xffffffff);
290 ddb_out32(DDB_BAR51, 0xffffffff);
291 ddb_out32(DDB_BARB1, 0xffffffff);
292
293 /*
294 * We use pci master register 0 for memory space / config space
295 * And we use register 1 for IO space.
296 * Note that for memory space, we bump up the pci base address
297 * so that we have 1:1 mapping between PCI memory and cpu physical.
298 * For PCI IO space, it starts from 0 in PCI IO space but with
299 * DDB_xx_IO_BASE in CPU physical address space.
300 */
301 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
302 DDB_PCI_ACCESS_32);
303 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
304
305 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
306 DDB_PCI_ACCESS_32);
307 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
308 DDB_PCI_ACCESS_32);
309
310
311 /* PCI cross window should be set properly */
312 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
313 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
314 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
315 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
316
317 if (mips_machtype == MACH_NEC_ROCKHOPPER
318 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
319 /* Disable bus diagnostics. */
320 ddb_out32(DDB_PCICTL0_L, 0);
321 ddb_out32(DDB_PCICTL0_H, 0);
322 ddb_out32(DDB_PCICTL1_L, 0);
323 ddb_out32(DDB_PCICTL1_H, 0);
324 }
325
326 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
327 u16 vid;
328 struct pci_bus bus;
329 struct pci_dev dev_m1533;
330 extern struct pci_ops ddb5477_ext_pci_ops;
331
332 bus.parent = NULL; /* we scan the top level only */
333 bus.ops = &ddb5477_ext_pci_ops;
334 dev_m1533.bus = &bus;
335 dev_m1533.sysdata = NULL;
336 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
337 pci_read_config_word(&dev_m1533, 0, &vid);
338 if (vid == PCI_VENDOR_ID_AL) {
339 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
340 mips_machtype = MACH_NEC_ROCKHOPPERII;
341 }
342 }
343
344 /* enable USB input buffers */
345 ddb_out32(DDB_PIBMISC, 0x00000007);
346
347 /* For dual-function pins, make them all non-GPIO */
348 ddb_out32(DDB_GIUFUNSEL, 0x0);
349 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
350
351 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
352 #ifdef CONFIG_PC_KEYB
353 printk("kdb_ops is std\n");
354 kbd_ops = &std_kbd_ops;
355 #endif
356 }
357
358 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
359
360 /* enable IDE controller on Ali chip (south bridge) */
361 u8 temp8;
362 struct pci_bus bus;
363 struct pci_dev dev_m1533;
364 struct pci_dev dev_m5229;
365 extern struct pci_ops ddb5477_ext_pci_ops;
366
367 /* Setup M1535 registers */
368 bus.parent = NULL; /* we scan the top level only */
369 bus.ops = &ddb5477_ext_pci_ops;
370 dev_m1533.bus = &bus;
371 dev_m1533.sysdata = NULL;
372 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
373
374 /* setup IDE controller
375 * enable IDE controller (bit 6 - 1)
376 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
377 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
378 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
379 */
380 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
381
382 /*
383 * positive decode (bit6 -0)
384 * enable IDE controler interrupt (bit 4 -1)
385 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
386 */
387 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
388
389 /* Setup M5229 registers */
390 dev_m5229.bus = &bus;
391 dev_m5229.sysdata = NULL;
392 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
393
394 /*
395 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
396 * M5229 IDSEL is addr:15; see above setting
397 */
398 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
399 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
400
401 /*
402 * enable bus master (bit 2) and IO decoding (bit 0)
403 */
404 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
405 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
406
407 /*
408 * enable native, copied from arch/ppc/k2boot/head.S
409 * TODO - need volatile, need to be portable
410 */
411 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
412
413 /* Set Primary Channel Command Block Timing */
414 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
415
416 /*
417 * Enable primary channel 40-pin cable
418 * M5229 register 0x4a (bit 0)
419 */
420 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
421 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
422 }
423
424 if (mips_machtype == MACH_NEC_ROCKHOPPER
425 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
426 printk("lcd44780: initializing\n");
427 lcd44780_init();
428 lcd44780_puts("MontaVista Linux");
429 }
430 }
431