Lines Matching refs:ddb_in32
33 t = ddb_in32(offset); in nile4_map_irq()
47 t = ddb_in32(DDB_INTCTRL); in nile4_map_irq_all()
51 t = ddb_in32(DDB_INTCTRL + 4); in nile4_map_irq_all()
66 t = ddb_in32(offset); in nile4_enable_irq()
80 t = ddb_in32(offset); in nile4_disable_irq()
100 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_enable_irq_output()
109 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_disable_irq_output()
118 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_polarity()
130 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_level_or_edge()
154 reg = ddb_in32(DDB_PCIINIT0); in nile4_i8259_iack()
170 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), in nile4_dump_irq_status()
171 (void *) ddb_in32(DDB_CPUSTAT)); in nile4_dump_irq_status()
173 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), in nile4_dump_irq_status()
174 (void *) ddb_in32(DDB_INTCTRL)); in nile4_dump_irq_status()
177 (void *) ddb_in32(DDB_INTSTAT0 + 4), in nile4_dump_irq_status()
178 (void *) ddb_in32(DDB_INTSTAT0)); in nile4_dump_irq_status()
181 (void *) ddb_in32(DDB_INTSTAT1 + 4), in nile4_dump_irq_status()
182 (void *) ddb_in32(DDB_INTSTAT1)); in nile4_dump_irq_status()
184 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), in nile4_dump_irq_status()
185 (void *) ddb_in32(DDB_INTCLR)); in nile4_dump_irq_status()
187 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), in nile4_dump_irq_status()
188 (void *) ddb_in32(DDB_INTPPES)); in nile4_dump_irq_status()