Lines Matching refs:ddb_in32
35 t = ddb_in32(offset); in nile4_map_irq()
49 t = ddb_in32(DDB_INTCTRL); in nile4_map_irq_all()
53 t = ddb_in32(DDB_INTCTRL + 4); in nile4_map_irq_all()
73 t = ddb_in32(offset); in nile4_enable_irq()
91 t = ddb_in32(offset); in nile4_disable_irq()
111 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_enable_irq_output()
120 t = ddb_in32(DDB_INTSTAT1 + 4); in nile4_disable_irq_output()
129 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_polarity()
141 t = ddb_in32(DDB_INTPPES); in nile4_set_pci_irq_level_or_edge()
166 reg = ddb_in32(DDB_PCIINIT0); in nile4_i8259_iack()
267 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), in nile4_dump_irq_status()
268 (void *) ddb_in32(DDB_CPUSTAT)); in nile4_dump_irq_status()
270 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), in nile4_dump_irq_status()
271 (void *) ddb_in32(DDB_INTCTRL)); in nile4_dump_irq_status()
274 (void *) ddb_in32(DDB_INTSTAT0 + 4), in nile4_dump_irq_status()
275 (void *) ddb_in32(DDB_INTSTAT0)); in nile4_dump_irq_status()
278 (void *) ddb_in32(DDB_INTSTAT1 + 4), in nile4_dump_irq_status()
279 (void *) ddb_in32(DDB_INTSTAT1)); in nile4_dump_irq_status()
281 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), in nile4_dump_irq_status()
282 (void *) ddb_in32(DDB_INTCLR)); in nile4_dump_irq_status()
284 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), in nile4_dump_irq_status()
285 (void *) ddb_in32(DDB_INTPPES)); in nile4_dump_irq_status()