Searched refs:AT91_REG (Results 1 – 9 of 9) sorted by relevance
25 AT91_REG AIC_SMR[32]; // Source Mode Register26 AT91_REG AIC_SVR[32]; // Source Vector Register27 AT91_REG AIC_IVR; // IRQ Vector Register28 AT91_REG AIC_FVR; // FIQ Vector Register29 AT91_REG AIC_ISR; // Interrupt Status Register30 AT91_REG AIC_IPR; // Interrupt Pending Register31 AT91_REG AIC_IMR; // Interrupt Mask Register32 AT91_REG AIC_CISR; // Core Interrupt Status Register33 AT91_REG Reserved0[2]; //34 AT91_REG AIC_IECR; // Interrupt Enable Command Register[all …]
25 AT91_REG EMAC_CTL; // Network Control Register26 AT91_REG EMAC_CFG; // Network Configuration Register27 AT91_REG EMAC_SR; // Network Status Register28 AT91_REG EMAC_TAR; // Transmit Address Register29 AT91_REG EMAC_TCR; // Transmit Control Register30 AT91_REG EMAC_TSR; // Transmit Status Register31 AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer32 AT91_REG Reserved0[1]; //33 AT91_REG EMAC_RSR; // Receive Status Register34 AT91_REG EMAC_ISR; // Interrupt Status Register[all …]
25 AT91_REG UHP_HcRevision; // Revision26 AT91_REG UHP_HcControl; // Operating modes for the Host Controller27 AT91_REG UHP_HcCommandStatus; // Command & status Register28 AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register29 AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register30 AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register31 AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area32 AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor33 AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list34 AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register[all …]
25 AT91_REG SPI_CR; // Control Register26 AT91_REG SPI_MR; // Mode Register27 AT91_REG SPI_RDR; // Receive Data Register28 AT91_REG SPI_TDR; // Transmit Data Register29 AT91_REG SPI_SR; // Status Register30 AT91_REG SPI_IER; // Interrupt Enable Register31 AT91_REG SPI_IDR; // Interrupt Disable Register32 AT91_REG SPI_IMR; // Interrupt Mask Register33 AT91_REG Reserved0[4]; //34 AT91_REG SPI_CSR0; // Chip Select Register 0[all …]
25 AT91_REG TWI_CR; // Control Register26 AT91_REG TWI_MMR; // Master Mode Register27 AT91_REG TWI_SMR; // Slave Mode Register28 AT91_REG TWI_IADR; // Internal Address Register29 AT91_REG TWI_CWGR; // Clock Waveform Generator Register30 AT91_REG Reserved0[3]; //31 AT91_REG TWI_SR; // Status Register32 AT91_REG TWI_IER; // Interrupt Enable Register33 AT91_REG TWI_IDR; // Interrupt Disable Register34 AT91_REG TWI_IMR; // Interrupt Mask Register[all …]
25 AT91_REG US_CR; // Control Register26 AT91_REG US_MR; // Mode Register27 AT91_REG US_IER; // Interrupt Enable Register28 AT91_REG US_IDR; // Interrupt Disable Register29 AT91_REG US_IMR; // Interrupt Mask Register30 AT91_REG US_CSR; // Channel Status Register31 AT91_REG US_RHR; // Receiver Holding Register32 AT91_REG US_THR; // Transmitter Holding Register33 AT91_REG US_BRGR; // Baud Rate Generator Register34 AT91_REG US_RTOR; // Receiver Time-out Register[all …]
25 AT91_REG UDP_NUM; // Frame Number Register26 AT91_REG UDP_GLBSTATE; // Global State Register27 AT91_REG UDP_FADDR; // Function Address Register28 AT91_REG Reserved0[1]; //29 AT91_REG UDP_IER; // Interrupt Enable Register30 AT91_REG UDP_IDR; // Interrupt Disable Register31 AT91_REG UDP_IMR; // Interrupt Mask Register32 AT91_REG UDP_ISR; // Interrupt Status Register33 AT91_REG UDP_ICR; // Interrupt Clear Register34 AT91_REG Reserved1[1]; //[all …]
22 typedef volatile unsigned int AT91_REG; typedef
65 static AT91_REG at91rm9200_irq_smr[] __initdata = {