Lines Matching refs:AT91_REG
25 AT91_REG TWI_CR; // Control Register
26 AT91_REG TWI_MMR; // Master Mode Register
27 AT91_REG TWI_SMR; // Slave Mode Register
28 AT91_REG TWI_IADR; // Internal Address Register
29 AT91_REG TWI_CWGR; // Clock Waveform Generator Register
30 AT91_REG Reserved0[3]; //
31 AT91_REG TWI_SR; // Status Register
32 AT91_REG TWI_IER; // Interrupt Enable Register
33 AT91_REG TWI_IDR; // Interrupt Disable Register
34 AT91_REG TWI_IMR; // Interrupt Mask Register
35 AT91_REG TWI_RHR; // Receive Holding Register
36 AT91_REG TWI_THR; // Transmit Holding Register
37 AT91_REG Reserved1[50]; //
38 AT91_REG TWI_RPR; // Receive Pointer Register
39 AT91_REG TWI_RCR; // Receive Counter Register
40 AT91_REG TWI_TPR; // Transmit Pointer Register
41 AT91_REG TWI_TCR; // Transmit Counter Register
42 AT91_REG TWI_RNPR; // Receive Next Pointer Register
43 AT91_REG TWI_RNCR; // Receive Next Counter Register
44 AT91_REG TWI_TNPR; // Transmit Next Pointer Register
45 AT91_REG TWI_TNCR; // Transmit Next Counter Register
46 AT91_REG TWI_PTCR; // PDC Transfer Control Register
47 AT91_REG TWI_PTSR; // PDC Transfer Status Register