1 // ---------------------------------------------------------------------------- 2 // ATMEL Microcontroller Software Support - ROUSSET - 3 // ---------------------------------------------------------------------------- 4 // The software is delivered "AS IS" without warranty or condition of any 5 // kind, either express, implied or statutory. This includes without 6 // limitation any warranty or condition with respect to merchantability or 7 // fitness for any particular purpose, or against the infringements of 8 // intellectual property rights of others. 9 // ---------------------------------------------------------------------------- 10 // File Name : AT91RM9200.h 11 // Object : AT91RM9200 / EMAC definitions 12 // Generated : AT91 SW Application Group 01/17/2003 (13:41:21) 13 // 14 // ---------------------------------------------------------------------------- 15 16 #ifndef AT91RM9200_EMAC_H 17 #define AT91RM9200_EMAC_H 18 19 // ***************************************************************************** 20 // SOFTWARE API DEFINITION FOR Ethernet MAC 21 // ***************************************************************************** 22 #ifndef __ASSEMBLY__ 23 24 typedef struct _AT91S_EMAC { 25 AT91_REG EMAC_CTL; // Network Control Register 26 AT91_REG EMAC_CFG; // Network Configuration Register 27 AT91_REG EMAC_SR; // Network Status Register 28 AT91_REG EMAC_TAR; // Transmit Address Register 29 AT91_REG EMAC_TCR; // Transmit Control Register 30 AT91_REG EMAC_TSR; // Transmit Status Register 31 AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer 32 AT91_REG Reserved0[1]; // 33 AT91_REG EMAC_RSR; // Receive Status Register 34 AT91_REG EMAC_ISR; // Interrupt Status Register 35 AT91_REG EMAC_IER; // Interrupt Enable Register 36 AT91_REG EMAC_IDR; // Interrupt Disable Register 37 AT91_REG EMAC_IMR; // Interrupt Mask Register 38 AT91_REG EMAC_MAN; // PHY Maintenance Register 39 AT91_REG Reserved1[2]; // 40 AT91_REG EMAC_FRA; // Frames Transmitted OK Register 41 AT91_REG EMAC_SCOL; // Single Collision Frame Register 42 AT91_REG EMAC_MCOL; // Multiple Collision Frame Register 43 AT91_REG EMAC_OK; // Frames Received OK Register 44 AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register 45 AT91_REG EMAC_ALE; // Alignment Error Register 46 AT91_REG EMAC_DTE; // Deferred Transmission Frame Register 47 AT91_REG EMAC_LCOL; // Late Collision Register 48 AT91_REG EMAC_ECOL; // Excessive Collision Register 49 AT91_REG EMAC_CSE; // Carrier Sense Error Register 50 AT91_REG EMAC_TUE; // Transmit Underrun Error Register 51 AT91_REG EMAC_CDE; // Code Error Register 52 AT91_REG EMAC_ELR; // Excessive Length Error Register 53 AT91_REG EMAC_RJB; // Receive Jabber Register 54 AT91_REG EMAC_USF; // Undersize Frame Register 55 AT91_REG EMAC_SQEE; // SQE Test Error Register 56 AT91_REG EMAC_DRFC; // Discarded RX Frame Register 57 AT91_REG Reserved2[3]; // 58 AT91_REG EMAC_HSH; // Hash Address High[63:32] 59 AT91_REG EMAC_HSL; // Hash Address Low[31:0] 60 AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes 61 AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes 62 AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes 63 AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes 64 AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes 65 AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes 66 AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes 67 AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr 68 } AT91S_EMAC, *AT91PS_EMAC; 69 70 #endif 71 72 // -------- EMAC_CTL : (EMAC Offset: 0x0) -------- 73 #define AT91C_EMAC_LB ( 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. 74 #define AT91C_EMAC_LBL ( 0x1 << 1) // (EMAC) Loopback local. 75 #define AT91C_EMAC_RE ( 0x1 << 2) // (EMAC) Receive enable. 76 #define AT91C_EMAC_TE ( 0x1 << 3) // (EMAC) Transmit enable. 77 #define AT91C_EMAC_MPE ( 0x1 << 4) // (EMAC) Management port enable. 78 #define AT91C_EMAC_CSR ( 0x1 << 5) // (EMAC) Clear statistics registers. 79 #define AT91C_EMAC_ISR ( 0x1 << 6) // (EMAC) Increment statistics registers. 80 #define AT91C_EMAC_WES ( 0x1 << 7) // (EMAC) Write enable for statistics registers. 81 #define AT91C_EMAC_BP ( 0x1 << 8) // (EMAC) Back pressure. 82 // -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- 83 #define AT91C_EMAC_SPD ( 0x1 << 0) // (EMAC) Speed. 84 #define AT91C_EMAC_FD ( 0x1 << 1) // (EMAC) Full duplex. 85 #define AT91C_EMAC_BR ( 0x1 << 2) // (EMAC) Bit rate. 86 #define AT91C_EMAC_CAF ( 0x1 << 4) // (EMAC) Copy all frames. 87 #define AT91C_EMAC_NBC ( 0x1 << 5) // (EMAC) No broadcast. 88 #define AT91C_EMAC_MTI ( 0x1 << 6) // (EMAC) Multicast hash enable 89 #define AT91C_EMAC_UNI ( 0x1 << 7) // (EMAC) Unicast hash enable. 90 #define AT91C_EMAC_BIG ( 0x1 << 8) // (EMAC) Receive 1522 bytes. 91 #define AT91C_EMAC_EAE ( 0x1 << 9) // (EMAC) External address match enable. 92 #define AT91C_EMAC_CLK ( 0x3 << 10) // (EMAC) 93 #define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10) // (EMAC) HCLK divided by 8 94 #define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10) // (EMAC) HCLK divided by 16 95 #define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10) // (EMAC) HCLK divided by 32 96 #define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10) // (EMAC) HCLK divided by 64 97 #define AT91C_EMAC_RTY ( 0x1 << 12) // (EMAC) 98 #define AT91C_EMAC_RMII ( 0x1 << 13) // (EMAC) 99 // -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- 100 #define AT91C_EMAC_MDIO ( 0x1 << 1) // (EMAC) 101 #define AT91C_EMAC_IDLE ( 0x1 << 2) // (EMAC) 102 // -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- 103 #define AT91C_EMAC_LEN ( 0x7FF << 0) // (EMAC) 104 #define AT91C_EMAC_NCRC ( 0x1 << 15) // (EMAC) 105 // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- 106 #define AT91C_EMAC_OVR ( 0x1 << 0) // (EMAC) 107 #define AT91C_EMAC_COL ( 0x1 << 1) // (EMAC) 108 #define AT91C_EMAC_RLE ( 0x1 << 2) // (EMAC) 109 #define AT91C_EMAC_TXIDLE ( 0x1 << 3) // (EMAC) 110 #define AT91C_EMAC_BNQ ( 0x1 << 4) // (EMAC) 111 #define AT91C_EMAC_COMP ( 0x1 << 5) // (EMAC) 112 #define AT91C_EMAC_UND ( 0x1 << 6) // (EMAC) 113 // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 114 #define AT91C_EMAC_BNA ( 0x1 << 0) // (EMAC) 115 #define AT91C_EMAC_REC ( 0x1 << 1) // (EMAC) 116 // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 117 #define AT91C_EMAC_DONE ( 0x1 << 0) // (EMAC) 118 #define AT91C_EMAC_RCOM ( 0x1 << 1) // (EMAC) 119 #define AT91C_EMAC_RBNA ( 0x1 << 2) // (EMAC) 120 #define AT91C_EMAC_TOVR ( 0x1 << 3) // (EMAC) 121 #define AT91C_EMAC_TUND ( 0x1 << 4) // (EMAC) 122 #define AT91C_EMAC_RTRY ( 0x1 << 5) // (EMAC) 123 #define AT91C_EMAC_TBRE ( 0x1 << 6) // (EMAC) 124 #define AT91C_EMAC_TCOM ( 0x1 << 7) // (EMAC) 125 #define AT91C_EMAC_TIDLE ( 0x1 << 8) // (EMAC) 126 #define AT91C_EMAC_LINK ( 0x1 << 9) // (EMAC) 127 #define AT91C_EMAC_ROVR ( 0x1 << 10) // (EMAC) 128 #define AT91C_EMAC_HRESP ( 0x1 << 11) // (EMAC) 129 // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 130 // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 131 // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 132 // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 133 #define AT91C_EMAC_DATA ( 0xFFFF << 0) // (EMAC) 134 #define AT91C_EMAC_CODE ( 0x3 << 16) // (EMAC) 135 #define AT91C_EMAC_CODE_802_3 ( 0x2 << 16) // (EMAC) Write Operation 136 #define AT91C_EMAC_REGA ( 0x1F << 18) // (EMAC) 137 #define AT91C_EMAC_PHYA ( 0x1F << 23) // (EMAC) 138 #define AT91C_EMAC_RW ( 0x3 << 28) // (EMAC) 139 #define AT91C_EMAC_RW_R ( 0x2 << 28) // (EMAC) Read Operation 140 #define AT91C_EMAC_RW_W ( 0x1 << 28) // (EMAC) Write Operation 141 #define AT91C_EMAC_HIGH ( 0x1 << 30) // (EMAC) 142 #define AT91C_EMAC_LOW ( 0x1 << 31) // (EMAC) 143 144 #endif 145