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Searched refs:PIPE_A (Results 1 – 25 of 47) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c121 MMIO_D(PIPEDSL(PIPE_A)); in iterate_generic_mmio()
129 MMIO_D(PIPESTAT(PIPE_A)); in iterate_generic_mmio()
133 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A)); in iterate_generic_mmio()
137 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A)); in iterate_generic_mmio()
141 MMIO_D(CURCNTR(PIPE_A)); in iterate_generic_mmio()
144 MMIO_D(CURPOS(PIPE_A)); in iterate_generic_mmio()
147 MMIO_D(CURBASE(PIPE_A)); in iterate_generic_mmio()
150 MMIO_D(CUR_FBC_CTL(PIPE_A)); in iterate_generic_mmio()
160 MMIO_D(DSPCNTR(PIPE_A)); in iterate_generic_mmio()
161 MMIO_D(DSPADDR(PIPE_A)); in iterate_generic_mmio()
[all …]
Dintel_clock_gating.c322 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
518 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in bdw_init_clock_gating()
565 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in hsw_init_clock_gating()
Di915_irq.c902 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
1083 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1208 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
1209 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_display_device.c112 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_A] = CURSOR_A_OFFSET, \
123 [PIPE_A] = CURSOR_A_OFFSET, \
130 [PIPE_A] = CURSOR_A_OFFSET, \
137 [PIPE_A] = CURSOR_A_OFFSET, \
183 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
196 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
232 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
293 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
334 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
Dintel_pch_display.c24 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
32 return PIPE_A; in intel_crtc_pch_transcoder()
119 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
127 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
138 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
146 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
548 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
550 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
556 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
581 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
[all …]
Dintel_fdi.c165 case PIPE_A: in ilk_check_fdi_lanes()
316 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
768 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
775 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
776 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
781 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
808 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
812 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
813 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
819 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
[all …]
Dskl_watermark.c844 .active_pipes = BIT(PIPE_A),
846 [PIPE_A] = BIT(DBUF_S1),
856 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
858 [PIPE_A] = BIT(DBUF_S1),
869 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
871 [PIPE_A] = BIT(DBUF_S1),
883 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
885 [PIPE_A] = BIT(DBUF_S1),
907 .active_pipes = BIT(PIPE_A),
909 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
Dintel_display_limits.h17 PIPE_A = 0, enumerator
34 TRANSCODER_A = PIPE_A,
Dintel_cursor.c283 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); in i845_cursor_update_arm()
284 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); in i845_cursor_update_arm()
285 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); in i845_cursor_update_arm()
286 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
287 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); in i845_cursor_update_arm()
293 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
311 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state()
316 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
318 *pipe = PIPE_A; in i845_cursor_get_hw_state()
Dintel_display_reg_defs.h40 DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \
46 DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \
Dg4x_hdmi.c397 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
398 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
401 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
415 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
416 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
417 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
758 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
Di9xx_wm.c272 case PIPE_A: in vlv_get_fifo_size()
723 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
729 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
730 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
773 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
775 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
776 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
777 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
799 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
800 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dg4x_dp.c267 *pipe = PIPE_A; in cpt_dp_port_selected()
449 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
450 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
454 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
463 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
464 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
465 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
1364 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
Dintel_display_trace.h47 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
76 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
183 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
Dintel_display_power_well.c1034 if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1035 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1044 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1050 return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1189 if (pipe != PIPE_A) in vlv_display_power_well_init()
1411 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1476 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1502 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1631 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1662 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
Dintel_crt.c247 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
276 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
288 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
333 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1053 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1118 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_pipe_crc.c174 case PIPE_A: in vlv_pipe_crc_ctl_reg()
235 case PIPE_A: in vlv_undo_pipe_scramble_reset()
309 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
Dintel_dmc_regs.h22 #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
Dintel_fifo_underrun.c139 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
226 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dintel_dpll.c1214 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1232 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1722 if (pipe == PIPE_A) in vlv_prepare_pll()
1730 if (pipe == PIPE_A) in vlv_prepare_pll()
1933 if (pipe != PIPE_A) { in chv_enable_pll()
2007 if (pipe != PIPE_A) in vlv_disable_pll()
2024 if (pipe != PIPE_A) in chv_disable_pll()
Dintel_display_irq.c290 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
440 case PIPE_A: in i9xx_pipestat_irq_ack()
612 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
936 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1395 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
Dintel_pps.c38 case PIPE_A: in pps_name()
166 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
223 pipe = PIPE_A; in vlv_power_sequencer_pipe()
294 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1119 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
/linux-6.6.21/drivers/gpu/drm/i915/gvt/
Dhandlers.c693 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
2274 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2275 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2283 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2284 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2309 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); in init_generic_mmio_info()
2312 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2315 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2462 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2464 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
[all …]
Dreg.h71 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
81 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
Ddisplay.c50 pipe = PIPE_A; in get_edp_pipe()
79 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
627 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
633 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()

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