1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "i915_irq.h"
8 #include "i915_reg.h"
9 #include "intel_backlight_regs.h"
10 #include "intel_combo_phy.h"
11 #include "intel_combo_phy_regs.h"
12 #include "intel_crt.h"
13 #include "intel_de.h"
14 #include "intel_display_irq.h"
15 #include "intel_display_power_well.h"
16 #include "intel_display_types.h"
17 #include "intel_dkl_phy.h"
18 #include "intel_dkl_phy_regs.h"
19 #include "intel_dmc.h"
20 #include "intel_dp_aux_regs.h"
21 #include "intel_dpio_phy.h"
22 #include "intel_dpll.h"
23 #include "intel_hotplug.h"
24 #include "intel_pcode.h"
25 #include "intel_pps.h"
26 #include "intel_tc.h"
27 #include "intel_vga.h"
28 #include "skl_watermark.h"
29 #include "vlv_sideband.h"
30 #include "vlv_sideband_reg.h"
31 
32 struct i915_power_well_regs {
33 	i915_reg_t bios;
34 	i915_reg_t driver;
35 	i915_reg_t kvmr;
36 	i915_reg_t debug;
37 };
38 
39 struct i915_power_well_ops {
40 	const struct i915_power_well_regs *regs;
41 	/*
42 	 * Synchronize the well's hw state to match the current sw state, for
43 	 * example enable/disable it based on the current refcount. Called
44 	 * during driver init and resume time, possibly after first calling
45 	 * the enable/disable handlers.
46 	 */
47 	void (*sync_hw)(struct drm_i915_private *i915,
48 			struct i915_power_well *power_well);
49 	/*
50 	 * Enable the well and resources that depend on it (for example
51 	 * interrupts located on the well). Called after the 0->1 refcount
52 	 * transition.
53 	 */
54 	void (*enable)(struct drm_i915_private *i915,
55 		       struct i915_power_well *power_well);
56 	/*
57 	 * Disable the well and resources that depend on it. Called after
58 	 * the 1->0 refcount transition.
59 	 */
60 	void (*disable)(struct drm_i915_private *i915,
61 			struct i915_power_well *power_well);
62 	/* Returns the hw enabled state. */
63 	bool (*is_enabled)(struct drm_i915_private *i915,
64 			   struct i915_power_well *power_well);
65 };
66 
67 static const struct i915_power_well_instance *
i915_power_well_instance(const struct i915_power_well * power_well)68 i915_power_well_instance(const struct i915_power_well *power_well)
69 {
70 	return &power_well->desc->instances->list[power_well->instance_idx];
71 }
72 
73 struct i915_power_well *
lookup_power_well(struct drm_i915_private * i915,enum i915_power_well_id power_well_id)74 lookup_power_well(struct drm_i915_private *i915,
75 		  enum i915_power_well_id power_well_id)
76 {
77 	struct i915_power_well *power_well;
78 
79 	for_each_power_well(i915, power_well)
80 		if (i915_power_well_instance(power_well)->id == power_well_id)
81 			return power_well;
82 
83 	/*
84 	 * It's not feasible to add error checking code to the callers since
85 	 * this condition really shouldn't happen and it doesn't even make sense
86 	 * to abort things like display initialization sequences. Just return
87 	 * the first power well and hope the WARN gets reported so we can fix
88 	 * our driver.
89 	 */
90 	drm_WARN(&i915->drm, 1,
91 		 "Power well %d not defined for this platform\n",
92 		 power_well_id);
93 	return &i915->display.power.domains.power_wells[0];
94 }
95 
intel_power_well_enable(struct drm_i915_private * i915,struct i915_power_well * power_well)96 void intel_power_well_enable(struct drm_i915_private *i915,
97 			     struct i915_power_well *power_well)
98 {
99 	drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well));
100 	power_well->desc->ops->enable(i915, power_well);
101 	power_well->hw_enabled = true;
102 }
103 
intel_power_well_disable(struct drm_i915_private * i915,struct i915_power_well * power_well)104 void intel_power_well_disable(struct drm_i915_private *i915,
105 			      struct i915_power_well *power_well)
106 {
107 	drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well));
108 	power_well->hw_enabled = false;
109 	power_well->desc->ops->disable(i915, power_well);
110 }
111 
intel_power_well_sync_hw(struct drm_i915_private * i915,struct i915_power_well * power_well)112 void intel_power_well_sync_hw(struct drm_i915_private *i915,
113 			      struct i915_power_well *power_well)
114 {
115 	power_well->desc->ops->sync_hw(i915, power_well);
116 	power_well->hw_enabled =
117 		power_well->desc->ops->is_enabled(i915, power_well);
118 }
119 
intel_power_well_get(struct drm_i915_private * i915,struct i915_power_well * power_well)120 void intel_power_well_get(struct drm_i915_private *i915,
121 			  struct i915_power_well *power_well)
122 {
123 	if (!power_well->count++)
124 		intel_power_well_enable(i915, power_well);
125 }
126 
intel_power_well_put(struct drm_i915_private * i915,struct i915_power_well * power_well)127 void intel_power_well_put(struct drm_i915_private *i915,
128 			  struct i915_power_well *power_well)
129 {
130 	drm_WARN(&i915->drm, !power_well->count,
131 		 "Use count on power well %s is already zero",
132 		 i915_power_well_instance(power_well)->name);
133 
134 	if (!--power_well->count)
135 		intel_power_well_disable(i915, power_well);
136 }
137 
intel_power_well_is_enabled(struct drm_i915_private * i915,struct i915_power_well * power_well)138 bool intel_power_well_is_enabled(struct drm_i915_private *i915,
139 				 struct i915_power_well *power_well)
140 {
141 	return power_well->desc->ops->is_enabled(i915, power_well);
142 }
143 
intel_power_well_is_enabled_cached(struct i915_power_well * power_well)144 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well)
145 {
146 	return power_well->hw_enabled;
147 }
148 
intel_display_power_well_is_enabled(struct drm_i915_private * dev_priv,enum i915_power_well_id power_well_id)149 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
150 					 enum i915_power_well_id power_well_id)
151 {
152 	struct i915_power_well *power_well;
153 
154 	power_well = lookup_power_well(dev_priv, power_well_id);
155 
156 	return intel_power_well_is_enabled(dev_priv, power_well);
157 }
158 
intel_power_well_is_always_on(struct i915_power_well * power_well)159 bool intel_power_well_is_always_on(struct i915_power_well *power_well)
160 {
161 	return power_well->desc->always_on;
162 }
163 
intel_power_well_name(struct i915_power_well * power_well)164 const char *intel_power_well_name(struct i915_power_well *power_well)
165 {
166 	return i915_power_well_instance(power_well)->name;
167 }
168 
intel_power_well_domains(struct i915_power_well * power_well)169 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well)
170 {
171 	return &power_well->domains;
172 }
173 
intel_power_well_refcount(struct i915_power_well * power_well)174 int intel_power_well_refcount(struct i915_power_well *power_well)
175 {
176 	return power_well->count;
177 }
178 
179 /*
180  * Starting with Haswell, we have a "Power Down Well" that can be turned off
181  * when not needed anymore. We have 4 registers that can request the power well
182  * to be enabled, and it will only be disabled if none of the registers is
183  * requesting it to be enabled.
184  */
hsw_power_well_post_enable(struct drm_i915_private * dev_priv,u8 irq_pipe_mask,bool has_vga)185 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
186 				       u8 irq_pipe_mask, bool has_vga)
187 {
188 	if (has_vga)
189 		intel_vga_reset_io_mem(dev_priv);
190 
191 	if (irq_pipe_mask)
192 		gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
193 }
194 
hsw_power_well_pre_disable(struct drm_i915_private * dev_priv,u8 irq_pipe_mask)195 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
196 				       u8 irq_pipe_mask)
197 {
198 	if (irq_pipe_mask)
199 		gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
200 }
201 
202 #define ICL_AUX_PW_TO_CH(pw_idx)	\
203 	((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
204 
205 #define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\
206 	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
207 
icl_aux_pw_to_ch(const struct i915_power_well * power_well)208 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
209 {
210 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
211 
212 	return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
213 					     ICL_AUX_PW_TO_CH(pw_idx);
214 }
215 
216 static struct intel_digital_port *
aux_ch_to_digital_port(struct drm_i915_private * dev_priv,enum aux_ch aux_ch)217 aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
218 		       enum aux_ch aux_ch)
219 {
220 	struct intel_digital_port *dig_port = NULL;
221 	struct intel_encoder *encoder;
222 
223 	for_each_intel_encoder(&dev_priv->drm, encoder) {
224 		/* We'll check the MST primary port */
225 		if (encoder->type == INTEL_OUTPUT_DP_MST)
226 			continue;
227 
228 		dig_port = enc_to_dig_port(encoder);
229 		if (!dig_port)
230 			continue;
231 
232 		if (dig_port->aux_ch != aux_ch) {
233 			dig_port = NULL;
234 			continue;
235 		}
236 
237 		break;
238 	}
239 
240 	return dig_port;
241 }
242 
icl_aux_pw_to_phy(struct drm_i915_private * i915,const struct i915_power_well * power_well)243 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
244 				  const struct i915_power_well *power_well)
245 {
246 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
247 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
248 
249 	return intel_port_to_phy(i915, dig_port->base.port);
250 }
251 
hsw_wait_for_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,bool timeout_expected)252 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
253 					   struct i915_power_well *power_well,
254 					   bool timeout_expected)
255 {
256 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
257 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
258 	int timeout = power_well->desc->enable_timeout ? : 1;
259 
260 	/*
261 	 * For some power wells we're not supposed to watch the status bit for
262 	 * an ack, but rather just wait a fixed amount of time and then
263 	 * proceed.  This is only used on DG2.
264 	 */
265 	if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
266 		usleep_range(600, 1200);
267 		return;
268 	}
269 
270 	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
271 	if (intel_de_wait_for_set(dev_priv, regs->driver,
272 				  HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) {
273 		drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
274 			    intel_power_well_name(power_well));
275 
276 		drm_WARN_ON(&dev_priv->drm, !timeout_expected);
277 
278 	}
279 }
280 
hsw_power_well_requesters(struct drm_i915_private * dev_priv,const struct i915_power_well_regs * regs,int pw_idx)281 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
282 				     const struct i915_power_well_regs *regs,
283 				     int pw_idx)
284 {
285 	u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
286 	u32 ret;
287 
288 	ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
289 	ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
290 	if (regs->kvmr.reg)
291 		ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
292 	ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
293 
294 	return ret;
295 }
296 
hsw_wait_for_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)297 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
298 					    struct i915_power_well *power_well)
299 {
300 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
301 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
302 	bool disabled;
303 	u32 reqs;
304 
305 	/*
306 	 * Bspec doesn't require waiting for PWs to get disabled, but still do
307 	 * this for paranoia. The known cases where a PW will be forced on:
308 	 * - a KVMR request on any power well via the KVMR request register
309 	 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
310 	 *   DEBUG request registers
311 	 * Skip the wait in case any of the request bits are set and print a
312 	 * diagnostic message.
313 	 */
314 	wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
315 			       HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
316 		 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
317 	if (disabled)
318 		return;
319 
320 	drm_dbg_kms(&dev_priv->drm,
321 		    "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
322 		    intel_power_well_name(power_well),
323 		    !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
324 }
325 
gen9_wait_for_power_well_fuses(struct drm_i915_private * dev_priv,enum skl_power_gate pg)326 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
327 					   enum skl_power_gate pg)
328 {
329 	/* Timeout 5us for PG#0, for other PGs 1us */
330 	drm_WARN_ON(&dev_priv->drm,
331 		    intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
332 					  SKL_FUSE_PG_DIST_STATUS(pg), 1));
333 }
334 
hsw_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)335 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
336 				  struct i915_power_well *power_well)
337 {
338 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
339 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
340 
341 	if (power_well->desc->has_fuses) {
342 		enum skl_power_gate pg;
343 
344 		pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
345 						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
346 
347 		/* Wa_16013190616:adlp */
348 		if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
349 			intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
350 
351 		/*
352 		 * For PW1 we have to wait both for the PW0/PG0 fuse state
353 		 * before enabling the power well and PW1/PG1's own fuse
354 		 * state after the enabling. For all other power wells with
355 		 * fuses we only have to wait for that PW/PG's fuse state
356 		 * after the enabling.
357 		 */
358 		if (pg == SKL_PG1)
359 			gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
360 	}
361 
362 	intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
363 
364 	hsw_wait_for_power_well_enable(dev_priv, power_well, false);
365 
366 	if (power_well->desc->has_fuses) {
367 		enum skl_power_gate pg;
368 
369 		pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
370 						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
371 		gen9_wait_for_power_well_fuses(dev_priv, pg);
372 	}
373 
374 	hsw_power_well_post_enable(dev_priv,
375 				   power_well->desc->irq_pipe_mask,
376 				   power_well->desc->has_vga);
377 }
378 
hsw_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)379 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
380 				   struct i915_power_well *power_well)
381 {
382 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
383 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
384 
385 	hsw_power_well_pre_disable(dev_priv,
386 				   power_well->desc->irq_pipe_mask);
387 
388 	intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
389 	hsw_wait_for_power_well_disable(dev_priv, power_well);
390 }
391 
intel_port_is_edp(struct drm_i915_private * i915,enum port port)392 static bool intel_port_is_edp(struct drm_i915_private *i915, enum port port)
393 {
394 	struct intel_encoder *encoder;
395 
396 	for_each_intel_encoder(&i915->drm, encoder) {
397 		if (encoder->type == INTEL_OUTPUT_EDP &&
398 		    encoder->port == port)
399 			return true;
400 	}
401 
402 	return false;
403 }
404 
405 static void
icl_combo_phy_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)406 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
407 				    struct i915_power_well *power_well)
408 {
409 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
410 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
411 	enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
412 
413 	drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
414 
415 	intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx));
416 
417 	if (DISPLAY_VER(dev_priv) < 12)
418 		intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy),
419 			     0, ICL_LANE_ENABLE_AUX);
420 
421 	hsw_wait_for_power_well_enable(dev_priv, power_well, false);
422 
423 	/* Display WA #1178: icl */
424 	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
425 	    !intel_port_is_edp(dev_priv, (enum port)phy))
426 		intel_de_rmw(dev_priv, ICL_AUX_ANAOVRD1(pw_idx),
427 			     0, ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS);
428 }
429 
430 static void
icl_combo_phy_aux_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)431 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
432 				     struct i915_power_well *power_well)
433 {
434 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
435 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
436 	enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
437 
438 	drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
439 
440 	intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), ICL_LANE_ENABLE_AUX, 0);
441 
442 	intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
443 
444 	hsw_wait_for_power_well_disable(dev_priv, power_well);
445 }
446 
447 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
448 
icl_tc_port_assert_ref_held(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,struct intel_digital_port * dig_port)449 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
450 					struct i915_power_well *power_well,
451 					struct intel_digital_port *dig_port)
452 {
453 	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
454 		return;
455 
456 	if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
457 		return;
458 
459 	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
460 }
461 
462 #else
463 
icl_tc_port_assert_ref_held(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,struct intel_digital_port * dig_port)464 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
465 					struct i915_power_well *power_well,
466 					struct intel_digital_port *dig_port)
467 {
468 }
469 
470 #endif
471 
472 #define TGL_AUX_PW_TO_TC_PORT(pw_idx)	((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
473 
icl_tc_cold_exit(struct drm_i915_private * i915)474 static void icl_tc_cold_exit(struct drm_i915_private *i915)
475 {
476 	int ret, tries = 0;
477 
478 	while (1) {
479 		ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
480 					      250, 1);
481 		if (ret != -EAGAIN || ++tries == 3)
482 			break;
483 		msleep(1);
484 	}
485 
486 	/* Spec states that TC cold exit can take up to 1ms to complete */
487 	if (!ret)
488 		msleep(1);
489 
490 	/* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
491 	drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
492 		    "succeeded");
493 }
494 
495 static void
icl_tc_phy_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)496 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
497 				 struct i915_power_well *power_well)
498 {
499 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
500 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
501 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
502 	bool is_tbt = power_well->desc->is_tc_tbt;
503 	bool timeout_expected;
504 
505 	icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
506 
507 	intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch),
508 		     DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0);
509 
510 	intel_de_rmw(dev_priv, regs->driver,
511 		     0,
512 		     HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx));
513 
514 	/*
515 	 * An AUX timeout is expected if the TBT DP tunnel is down,
516 	 * or need to enable AUX on a legacy TypeC port as part of the TC-cold
517 	 * exit sequence.
518 	 */
519 	timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
520 	if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
521 		icl_tc_cold_exit(dev_priv);
522 
523 	hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
524 
525 	if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
526 		enum tc_port tc_port;
527 
528 		tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
529 
530 		if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
531 			     DKL_CMN_UC_DW27_UC_HEALTH, 1))
532 			drm_warn(&dev_priv->drm,
533 				 "Timeout waiting TC uC health\n");
534 	}
535 }
536 
537 static void
icl_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)538 icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
539 			  struct i915_power_well *power_well)
540 {
541 	enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
542 
543 	if (intel_phy_is_tc(dev_priv, phy))
544 		return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
545 	else if (IS_ICELAKE(dev_priv))
546 		return icl_combo_phy_aux_power_well_enable(dev_priv,
547 							   power_well);
548 	else
549 		return hsw_power_well_enable(dev_priv, power_well);
550 }
551 
552 static void
icl_aux_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)553 icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
554 			   struct i915_power_well *power_well)
555 {
556 	enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
557 
558 	if (intel_phy_is_tc(dev_priv, phy))
559 		return hsw_power_well_disable(dev_priv, power_well);
560 	else if (IS_ICELAKE(dev_priv))
561 		return icl_combo_phy_aux_power_well_disable(dev_priv,
562 							    power_well);
563 	else
564 		return hsw_power_well_disable(dev_priv, power_well);
565 }
566 
567 /*
568  * We should only use the power well if we explicitly asked the hardware to
569  * enable it, so check if it's enabled and also check if we've requested it to
570  * be enabled.
571  */
hsw_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)572 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
573 				   struct i915_power_well *power_well)
574 {
575 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
576 	enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
577 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
578 	u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
579 		   HSW_PWR_WELL_CTL_STATE(pw_idx);
580 	u32 val;
581 
582 	val = intel_de_read(dev_priv, regs->driver);
583 
584 	/*
585 	 * On GEN9 big core due to a DMC bug the driver's request bits for PW1
586 	 * and the MISC_IO PW will be not restored, so check instead for the
587 	 * BIOS's own request bits, which are forced-on for these power wells
588 	 * when exiting DC5/6.
589 	 */
590 	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
591 	    (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
592 		val |= intel_de_read(dev_priv, regs->bios);
593 
594 	return (val & mask) == mask;
595 }
596 
assert_can_enable_dc9(struct drm_i915_private * dev_priv)597 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
598 {
599 	drm_WARN_ONCE(&dev_priv->drm,
600 		      (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
601 		      "DC9 already programmed to be enabled.\n");
602 	drm_WARN_ONCE(&dev_priv->drm,
603 		      intel_de_read(dev_priv, DC_STATE_EN) &
604 		      DC_STATE_EN_UPTO_DC5,
605 		      "DC5 still not disabled to enable DC9.\n");
606 	drm_WARN_ONCE(&dev_priv->drm,
607 		      intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
608 		      HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
609 		      "Power well 2 on.\n");
610 	drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
611 		      "Interrupts not disabled yet.\n");
612 
613 	 /*
614 	  * TODO: check for the following to verify the conditions to enter DC9
615 	  * state are satisfied:
616 	  * 1] Check relevant display engine registers to verify if mode set
617 	  * disable sequence was followed.
618 	  * 2] Check if display uninitialize sequence is initialized.
619 	  */
620 }
621 
assert_can_disable_dc9(struct drm_i915_private * dev_priv)622 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
623 {
624 	drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
625 		      "Interrupts not disabled yet.\n");
626 	drm_WARN_ONCE(&dev_priv->drm,
627 		      intel_de_read(dev_priv, DC_STATE_EN) &
628 		      DC_STATE_EN_UPTO_DC5,
629 		      "DC5 still not disabled.\n");
630 
631 	 /*
632 	  * TODO: check for the following to verify DC9 state was indeed
633 	  * entered before programming to disable it:
634 	  * 1] Check relevant display engine registers to verify if mode
635 	  *  set disable sequence was followed.
636 	  * 2] Check if display uninitialize sequence is initialized.
637 	  */
638 }
639 
gen9_write_dc_state(struct drm_i915_private * dev_priv,u32 state)640 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
641 				u32 state)
642 {
643 	int rewrites = 0;
644 	int rereads = 0;
645 	u32 v;
646 
647 	intel_de_write(dev_priv, DC_STATE_EN, state);
648 
649 	/* It has been observed that disabling the dc6 state sometimes
650 	 * doesn't stick and dmc keeps returning old value. Make sure
651 	 * the write really sticks enough times and also force rewrite until
652 	 * we are confident that state is exactly what we want.
653 	 */
654 	do  {
655 		v = intel_de_read(dev_priv, DC_STATE_EN);
656 
657 		if (v != state) {
658 			intel_de_write(dev_priv, DC_STATE_EN, state);
659 			rewrites++;
660 			rereads = 0;
661 		} else if (rereads++ > 5) {
662 			break;
663 		}
664 
665 	} while (rewrites < 100);
666 
667 	if (v != state)
668 		drm_err(&dev_priv->drm,
669 			"Writing dc state to 0x%x failed, now 0x%x\n",
670 			state, v);
671 
672 	/* Most of the times we need one retry, avoid spam */
673 	if (rewrites > 1)
674 		drm_dbg_kms(&dev_priv->drm,
675 			    "Rewrote dc state to 0x%x %d times\n",
676 			    state, rewrites);
677 }
678 
gen9_dc_mask(struct drm_i915_private * dev_priv)679 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
680 {
681 	u32 mask;
682 
683 	mask = DC_STATE_EN_UPTO_DC5;
684 
685 	if (DISPLAY_VER(dev_priv) >= 12)
686 		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
687 					  | DC_STATE_EN_DC9;
688 	else if (DISPLAY_VER(dev_priv) == 11)
689 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
690 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
691 		mask |= DC_STATE_EN_DC9;
692 	else
693 		mask |= DC_STATE_EN_UPTO_DC6;
694 
695 	return mask;
696 }
697 
gen9_sanitize_dc_state(struct drm_i915_private * i915)698 void gen9_sanitize_dc_state(struct drm_i915_private *i915)
699 {
700 	struct i915_power_domains *power_domains = &i915->display.power.domains;
701 	u32 val;
702 
703 	if (!HAS_DISPLAY(i915))
704 		return;
705 
706 	val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915);
707 
708 	drm_dbg_kms(&i915->drm,
709 		    "Resetting DC state tracking from %02x to %02x\n",
710 		    power_domains->dc_state, val);
711 	power_domains->dc_state = val;
712 }
713 
714 /**
715  * gen9_set_dc_state - set target display C power state
716  * @dev_priv: i915 device instance
717  * @state: target DC power state
718  * - DC_STATE_DISABLE
719  * - DC_STATE_EN_UPTO_DC5
720  * - DC_STATE_EN_UPTO_DC6
721  * - DC_STATE_EN_DC9
722  *
723  * Signal to DMC firmware/HW the target DC power state passed in @state.
724  * DMC/HW can turn off individual display clocks and power rails when entering
725  * a deeper DC power state (higher in number) and turns these back when exiting
726  * that state to a shallower power state (lower in number). The HW will decide
727  * when to actually enter a given state on an on-demand basis, for instance
728  * depending on the active state of display pipes. The state of display
729  * registers backed by affected power rails are saved/restored as needed.
730  *
731  * Based on the above enabling a deeper DC power state is asynchronous wrt.
732  * enabling it. Disabling a deeper power state is synchronous: for instance
733  * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
734  * back on and register state is restored. This is guaranteed by the MMIO write
735  * to DC_STATE_EN blocking until the state is restored.
736  */
gen9_set_dc_state(struct drm_i915_private * dev_priv,u32 state)737 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
738 {
739 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
740 	u32 val;
741 	u32 mask;
742 
743 	if (!HAS_DISPLAY(dev_priv))
744 		return;
745 
746 	if (drm_WARN_ON_ONCE(&dev_priv->drm,
747 			     state & ~power_domains->allowed_dc_mask))
748 		state &= power_domains->allowed_dc_mask;
749 
750 	val = intel_de_read(dev_priv, DC_STATE_EN);
751 	mask = gen9_dc_mask(dev_priv);
752 	drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
753 		    val & mask, state);
754 
755 	/* Check if DMC is ignoring our DC state requests */
756 	if ((val & mask) != power_domains->dc_state)
757 		drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
758 			power_domains->dc_state, val & mask);
759 
760 	val &= ~mask;
761 	val |= state;
762 
763 	gen9_write_dc_state(dev_priv, val);
764 
765 	power_domains->dc_state = val & mask;
766 }
767 
tgl_enable_dc3co(struct drm_i915_private * dev_priv)768 static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
769 {
770 	drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
771 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
772 }
773 
tgl_disable_dc3co(struct drm_i915_private * dev_priv)774 static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
775 {
776 	drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
777 	intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
778 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
779 	/*
780 	 * Delay of 200us DC3CO Exit time B.Spec 49196
781 	 */
782 	usleep_range(200, 210);
783 }
784 
assert_can_enable_dc5(struct drm_i915_private * dev_priv)785 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
786 {
787 	enum i915_power_well_id high_pg;
788 
789 	/* Power wells at this level and above must be disabled for DC5 entry */
790 	if (DISPLAY_VER(dev_priv) == 12)
791 		high_pg = ICL_DISP_PW_3;
792 	else
793 		high_pg = SKL_DISP_PW_2;
794 
795 	drm_WARN_ONCE(&dev_priv->drm,
796 		      intel_display_power_well_is_enabled(dev_priv, high_pg),
797 		      "Power wells above platform's DC5 limit still enabled.\n");
798 
799 	drm_WARN_ONCE(&dev_priv->drm,
800 		      (intel_de_read(dev_priv, DC_STATE_EN) &
801 		       DC_STATE_EN_UPTO_DC5),
802 		      "DC5 already programmed to be enabled.\n");
803 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
804 
805 	assert_dmc_loaded(dev_priv);
806 }
807 
gen9_enable_dc5(struct drm_i915_private * dev_priv)808 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
809 {
810 	assert_can_enable_dc5(dev_priv);
811 
812 	drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
813 
814 	/* Wa Display #1183: skl,kbl,cfl */
815 	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
816 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
817 			     0, SKL_SELECT_ALTERNATE_DC_EXIT);
818 
819 	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
820 }
821 
assert_can_enable_dc6(struct drm_i915_private * dev_priv)822 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
823 {
824 	drm_WARN_ONCE(&dev_priv->drm,
825 		      (intel_de_read(dev_priv, UTIL_PIN_CTL) &
826 		       (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) ==
827 		      (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
828 		      "Utility pin enabled in PWM mode\n");
829 	drm_WARN_ONCE(&dev_priv->drm,
830 		      (intel_de_read(dev_priv, DC_STATE_EN) &
831 		       DC_STATE_EN_UPTO_DC6),
832 		      "DC6 already programmed to be enabled.\n");
833 
834 	assert_dmc_loaded(dev_priv);
835 }
836 
skl_enable_dc6(struct drm_i915_private * dev_priv)837 void skl_enable_dc6(struct drm_i915_private *dev_priv)
838 {
839 	assert_can_enable_dc6(dev_priv);
840 
841 	drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
842 
843 	/* Wa Display #1183: skl,kbl,cfl */
844 	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
845 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
846 			     0, SKL_SELECT_ALTERNATE_DC_EXIT);
847 
848 	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
849 }
850 
bxt_enable_dc9(struct drm_i915_private * dev_priv)851 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
852 {
853 	assert_can_enable_dc9(dev_priv);
854 
855 	drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
856 	/*
857 	 * Power sequencer reset is not needed on
858 	 * platforms with South Display Engine on PCH,
859 	 * because PPS registers are always on.
860 	 */
861 	if (!HAS_PCH_SPLIT(dev_priv))
862 		intel_pps_reset_all(dev_priv);
863 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
864 }
865 
bxt_disable_dc9(struct drm_i915_private * dev_priv)866 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
867 {
868 	assert_can_disable_dc9(dev_priv);
869 
870 	drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
871 
872 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
873 
874 	intel_pps_unlock_regs_wa(dev_priv);
875 }
876 
hsw_power_well_sync_hw(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)877 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
878 				   struct i915_power_well *power_well)
879 {
880 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
881 	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
882 	u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
883 	u32 bios_req = intel_de_read(dev_priv, regs->bios);
884 
885 	/* Take over the request bit if set by BIOS. */
886 	if (bios_req & mask) {
887 		u32 drv_req = intel_de_read(dev_priv, regs->driver);
888 
889 		if (!(drv_req & mask))
890 			intel_de_write(dev_priv, regs->driver, drv_req | mask);
891 		intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
892 	}
893 }
894 
bxt_dpio_cmn_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)895 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
896 					   struct i915_power_well *power_well)
897 {
898 	bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
899 }
900 
bxt_dpio_cmn_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)901 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
902 					    struct i915_power_well *power_well)
903 {
904 	bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
905 }
906 
bxt_dpio_cmn_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)907 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
908 					    struct i915_power_well *power_well)
909 {
910 	return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
911 }
912 
bxt_verify_ddi_phy_power_wells(struct drm_i915_private * dev_priv)913 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
914 {
915 	struct i915_power_well *power_well;
916 
917 	power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
918 	if (intel_power_well_refcount(power_well) > 0)
919 		bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
920 
921 	power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
922 	if (intel_power_well_refcount(power_well) > 0)
923 		bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
924 
925 	if (IS_GEMINILAKE(dev_priv)) {
926 		power_well = lookup_power_well(dev_priv,
927 					       GLK_DISP_PW_DPIO_CMN_C);
928 		if (intel_power_well_refcount(power_well) > 0)
929 			bxt_ddi_phy_verify_state(dev_priv,
930 						 i915_power_well_instance(power_well)->bxt.phy);
931 	}
932 }
933 
gen9_dc_off_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)934 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
935 					   struct i915_power_well *power_well)
936 {
937 	return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
938 		(intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
939 }
940 
gen9_assert_dbuf_enabled(struct drm_i915_private * dev_priv)941 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
942 {
943 	u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
944 	u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
945 
946 	drm_WARN(&dev_priv->drm,
947 		 hw_enabled_dbuf_slices != enabled_dbuf_slices,
948 		 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
949 		 hw_enabled_dbuf_slices,
950 		 enabled_dbuf_slices);
951 }
952 
gen9_disable_dc_states(struct drm_i915_private * dev_priv)953 void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
954 {
955 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
956 	struct intel_cdclk_config cdclk_config = {};
957 
958 	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
959 		tgl_disable_dc3co(dev_priv);
960 		return;
961 	}
962 
963 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
964 
965 	if (!HAS_DISPLAY(dev_priv))
966 		return;
967 
968 	intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
969 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
970 	drm_WARN_ON(&dev_priv->drm,
971 		    intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,
972 					      &cdclk_config));
973 
974 	gen9_assert_dbuf_enabled(dev_priv);
975 
976 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
977 		bxt_verify_ddi_phy_power_wells(dev_priv);
978 
979 	if (DISPLAY_VER(dev_priv) >= 11)
980 		/*
981 		 * DMC retains HW context only for port A, the other combo
982 		 * PHY's HW context for port B is lost after DC transitions,
983 		 * so we need to restore it manually.
984 		 */
985 		intel_combo_phy_init(dev_priv);
986 }
987 
gen9_dc_off_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)988 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
989 					  struct i915_power_well *power_well)
990 {
991 	gen9_disable_dc_states(dev_priv);
992 }
993 
gen9_dc_off_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)994 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
995 					   struct i915_power_well *power_well)
996 {
997 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
998 
999 	if (!intel_dmc_has_payload(dev_priv))
1000 		return;
1001 
1002 	switch (power_domains->target_dc_state) {
1003 	case DC_STATE_EN_DC3CO:
1004 		tgl_enable_dc3co(dev_priv);
1005 		break;
1006 	case DC_STATE_EN_UPTO_DC6:
1007 		skl_enable_dc6(dev_priv);
1008 		break;
1009 	case DC_STATE_EN_UPTO_DC5:
1010 		gen9_enable_dc5(dev_priv);
1011 		break;
1012 	}
1013 }
1014 
i9xx_power_well_sync_hw_noop(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1015 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
1016 					 struct i915_power_well *power_well)
1017 {
1018 }
1019 
i9xx_always_on_power_well_noop(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1020 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
1021 					   struct i915_power_well *power_well)
1022 {
1023 }
1024 
i9xx_always_on_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1025 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
1026 					     struct i915_power_well *power_well)
1027 {
1028 	return true;
1029 }
1030 
i830_pipes_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1031 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
1032 					 struct i915_power_well *power_well)
1033 {
1034 	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
1035 		i830_enable_pipe(dev_priv, PIPE_A);
1036 	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
1037 		i830_enable_pipe(dev_priv, PIPE_B);
1038 }
1039 
i830_pipes_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1040 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
1041 					  struct i915_power_well *power_well)
1042 {
1043 	i830_disable_pipe(dev_priv, PIPE_B);
1044 	i830_disable_pipe(dev_priv, PIPE_A);
1045 }
1046 
i830_pipes_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1047 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
1048 					  struct i915_power_well *power_well)
1049 {
1050 	return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
1051 		intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
1052 }
1053 
i830_pipes_power_well_sync_hw(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1054 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
1055 					  struct i915_power_well *power_well)
1056 {
1057 	if (intel_power_well_refcount(power_well) > 0)
1058 		i830_pipes_power_well_enable(dev_priv, power_well);
1059 	else
1060 		i830_pipes_power_well_disable(dev_priv, power_well);
1061 }
1062 
vlv_set_power_well(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,bool enable)1063 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
1064 			       struct i915_power_well *power_well, bool enable)
1065 {
1066 	int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1067 	u32 mask;
1068 	u32 state;
1069 	u32 ctrl;
1070 
1071 	mask = PUNIT_PWRGT_MASK(pw_idx);
1072 	state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
1073 			 PUNIT_PWRGT_PWR_GATE(pw_idx);
1074 
1075 	vlv_punit_get(dev_priv);
1076 
1077 #define COND \
1078 	((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1079 
1080 	if (COND)
1081 		goto out;
1082 
1083 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
1084 	ctrl &= ~mask;
1085 	ctrl |= state;
1086 	vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
1087 
1088 	if (wait_for(COND, 100))
1089 		drm_err(&dev_priv->drm,
1090 			"timeout setting power well state %08x (%08x)\n",
1091 			state,
1092 			vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1093 
1094 #undef COND
1095 
1096 out:
1097 	vlv_punit_put(dev_priv);
1098 }
1099 
vlv_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1100 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1101 				  struct i915_power_well *power_well)
1102 {
1103 	vlv_set_power_well(dev_priv, power_well, true);
1104 }
1105 
vlv_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1106 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1107 				   struct i915_power_well *power_well)
1108 {
1109 	vlv_set_power_well(dev_priv, power_well, false);
1110 }
1111 
vlv_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1112 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1113 				   struct i915_power_well *power_well)
1114 {
1115 	int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
1116 	bool enabled = false;
1117 	u32 mask;
1118 	u32 state;
1119 	u32 ctrl;
1120 
1121 	mask = PUNIT_PWRGT_MASK(pw_idx);
1122 	ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
1123 
1124 	vlv_punit_get(dev_priv);
1125 
1126 	state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1127 	/*
1128 	 * We only ever set the power-on and power-gate states, anything
1129 	 * else is unexpected.
1130 	 */
1131 	drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
1132 		    state != PUNIT_PWRGT_PWR_GATE(pw_idx));
1133 	if (state == ctrl)
1134 		enabled = true;
1135 
1136 	/*
1137 	 * A transient state at this point would mean some unexpected party
1138 	 * is poking at the power controls too.
1139 	 */
1140 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1141 	drm_WARN_ON(&dev_priv->drm, ctrl != state);
1142 
1143 	vlv_punit_put(dev_priv);
1144 
1145 	return enabled;
1146 }
1147 
vlv_init_display_clock_gating(struct drm_i915_private * dev_priv)1148 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1149 {
1150 	/*
1151 	 * On driver load, a pipe may be active and driving a DSI display.
1152 	 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1153 	 * (and never recovering) in this case. intel_dsi_post_disable() will
1154 	 * clear it when we turn off the display.
1155 	 */
1156 	intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
1157 		     ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);
1158 
1159 	/*
1160 	 * Disable trickle feed and enable pnd deadline calculation
1161 	 */
1162 	intel_de_write(dev_priv, MI_ARB_VLV,
1163 		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1164 	intel_de_write(dev_priv, CBR1_VLV, 0);
1165 
1166 	drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
1167 	intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
1168 		       DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
1169 					 1000));
1170 }
1171 
vlv_display_power_well_init(struct drm_i915_private * dev_priv)1172 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1173 {
1174 	struct intel_encoder *encoder;
1175 	enum pipe pipe;
1176 
1177 	/*
1178 	 * Enable the CRI clock source so we can get at the
1179 	 * display and the reference clock for VGA
1180 	 * hotplug / manual detection. Supposedly DSI also
1181 	 * needs the ref clock up and running.
1182 	 *
1183 	 * CHV DPLL B/C have some issues if VGA mode is enabled.
1184 	 */
1185 	for_each_pipe(dev_priv, pipe) {
1186 		u32 val = intel_de_read(dev_priv, DPLL(pipe));
1187 
1188 		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1189 		if (pipe != PIPE_A)
1190 			val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1191 
1192 		intel_de_write(dev_priv, DPLL(pipe), val);
1193 	}
1194 
1195 	vlv_init_display_clock_gating(dev_priv);
1196 
1197 	spin_lock_irq(&dev_priv->irq_lock);
1198 	valleyview_enable_display_irqs(dev_priv);
1199 	spin_unlock_irq(&dev_priv->irq_lock);
1200 
1201 	/*
1202 	 * During driver initialization/resume we can avoid restoring the
1203 	 * part of the HW/SW state that will be inited anyway explicitly.
1204 	 */
1205 	if (dev_priv->display.power.domains.initializing)
1206 		return;
1207 
1208 	intel_hpd_init(dev_priv);
1209 	intel_hpd_poll_disable(dev_priv);
1210 
1211 	/* Re-enable the ADPA, if we have one */
1212 	for_each_intel_encoder(&dev_priv->drm, encoder) {
1213 		if (encoder->type == INTEL_OUTPUT_ANALOG)
1214 			intel_crt_reset(&encoder->base);
1215 	}
1216 
1217 	intel_vga_redisable_power_on(dev_priv);
1218 
1219 	intel_pps_unlock_regs_wa(dev_priv);
1220 }
1221 
vlv_display_power_well_deinit(struct drm_i915_private * dev_priv)1222 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1223 {
1224 	spin_lock_irq(&dev_priv->irq_lock);
1225 	valleyview_disable_display_irqs(dev_priv);
1226 	spin_unlock_irq(&dev_priv->irq_lock);
1227 
1228 	/* make sure we're done processing display irqs */
1229 	intel_synchronize_irq(dev_priv);
1230 
1231 	intel_pps_reset_all(dev_priv);
1232 
1233 	/* Prevent us from re-enabling polling on accident in late suspend */
1234 	if (!dev_priv->drm.dev->power.is_suspended)
1235 		intel_hpd_poll_enable(dev_priv);
1236 }
1237 
vlv_display_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1238 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1239 					  struct i915_power_well *power_well)
1240 {
1241 	vlv_set_power_well(dev_priv, power_well, true);
1242 
1243 	vlv_display_power_well_init(dev_priv);
1244 }
1245 
vlv_display_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1246 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1247 					   struct i915_power_well *power_well)
1248 {
1249 	vlv_display_power_well_deinit(dev_priv);
1250 
1251 	vlv_set_power_well(dev_priv, power_well, false);
1252 }
1253 
vlv_dpio_cmn_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1254 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1255 					   struct i915_power_well *power_well)
1256 {
1257 	/* since ref/cri clock was enabled */
1258 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1259 
1260 	vlv_set_power_well(dev_priv, power_well, true);
1261 
1262 	/*
1263 	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1264 	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
1265 	 *   a.	GUnit 0x2110 bit[0] set to 1 (def 0)
1266 	 *   b.	The other bits such as sfr settings / modesel may all
1267 	 *	be set to 0.
1268 	 *
1269 	 * This should only be done on init and resume from S3 with
1270 	 * both PLLs disabled, or we risk losing DPIO and PLL
1271 	 * synchronization.
1272 	 */
1273 	intel_de_rmw(dev_priv, DPIO_CTL, 0, DPIO_CMNRST);
1274 }
1275 
vlv_dpio_cmn_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1276 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1277 					    struct i915_power_well *power_well)
1278 {
1279 	enum pipe pipe;
1280 
1281 	for_each_pipe(dev_priv, pipe)
1282 		assert_pll_disabled(dev_priv, pipe);
1283 
1284 	/* Assert common reset */
1285 	intel_de_rmw(dev_priv, DPIO_CTL, DPIO_CMNRST, 0);
1286 
1287 	vlv_set_power_well(dev_priv, power_well, false);
1288 }
1289 
1290 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1291 
assert_chv_phy_status(struct drm_i915_private * dev_priv)1292 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1293 {
1294 	struct i915_power_well *cmn_bc =
1295 		lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1296 	struct i915_power_well *cmn_d =
1297 		lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1298 	u32 phy_control = dev_priv->display.power.chv_phy_control;
1299 	u32 phy_status = 0;
1300 	u32 phy_status_mask = 0xffffffff;
1301 
1302 	/*
1303 	 * The BIOS can leave the PHY is some weird state
1304 	 * where it doesn't fully power down some parts.
1305 	 * Disable the asserts until the PHY has been fully
1306 	 * reset (ie. the power well has been disabled at
1307 	 * least once).
1308 	 */
1309 	if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
1310 		phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1311 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1312 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1313 				     PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1314 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1315 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1316 
1317 	if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
1318 		phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1319 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1320 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1321 
1322 	if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
1323 		phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1324 
1325 		/* this assumes override is only used to enable lanes */
1326 		if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1327 			phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1328 
1329 		if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1330 			phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1331 
1332 		/* CL1 is on whenever anything is on in either channel */
1333 		if (BITS_SET(phy_control,
1334 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1335 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1336 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1337 
1338 		/*
1339 		 * The DPLLB check accounts for the pipe B + port A usage
1340 		 * with CL2 powered up but all the lanes in the second channel
1341 		 * powered down.
1342 		 */
1343 		if (BITS_SET(phy_control,
1344 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1345 		    (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1346 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1347 
1348 		if (BITS_SET(phy_control,
1349 			     PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1350 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1351 		if (BITS_SET(phy_control,
1352 			     PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1353 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1354 
1355 		if (BITS_SET(phy_control,
1356 			     PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1357 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1358 		if (BITS_SET(phy_control,
1359 			     PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1360 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1361 	}
1362 
1363 	if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
1364 		phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1365 
1366 		/* this assumes override is only used to enable lanes */
1367 		if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1368 			phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1369 
1370 		if (BITS_SET(phy_control,
1371 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1372 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1373 
1374 		if (BITS_SET(phy_control,
1375 			     PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1376 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1377 		if (BITS_SET(phy_control,
1378 			     PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1379 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1380 	}
1381 
1382 	phy_status &= phy_status_mask;
1383 
1384 	/*
1385 	 * The PHY may be busy with some initial calibration and whatnot,
1386 	 * so the power state can take a while to actually change.
1387 	 */
1388 	if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
1389 				       phy_status_mask, phy_status, 10))
1390 		drm_err(&dev_priv->drm,
1391 			"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1392 			intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1393 			phy_status, dev_priv->display.power.chv_phy_control);
1394 }
1395 
1396 #undef BITS_SET
1397 
chv_dpio_cmn_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1398 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1399 					   struct i915_power_well *power_well)
1400 {
1401 	enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1402 	enum dpio_phy phy;
1403 	enum pipe pipe;
1404 	u32 tmp;
1405 
1406 	drm_WARN_ON_ONCE(&dev_priv->drm,
1407 			 id != VLV_DISP_PW_DPIO_CMN_BC &&
1408 			 id != CHV_DISP_PW_DPIO_CMN_D);
1409 
1410 	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1411 		pipe = PIPE_A;
1412 		phy = DPIO_PHY0;
1413 	} else {
1414 		pipe = PIPE_C;
1415 		phy = DPIO_PHY1;
1416 	}
1417 
1418 	/* since ref/cri clock was enabled */
1419 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1420 	vlv_set_power_well(dev_priv, power_well, true);
1421 
1422 	/* Poll for phypwrgood signal */
1423 	if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1424 				  PHY_POWERGOOD(phy), 1))
1425 		drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
1426 			phy);
1427 
1428 	vlv_dpio_get(dev_priv);
1429 
1430 	/* Enable dynamic power down */
1431 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1432 	tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1433 		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1434 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1435 
1436 	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1437 		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1438 		tmp |= DPIO_DYNPWRDOWNEN_CH1;
1439 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1440 	} else {
1441 		/*
1442 		 * Force the non-existing CL2 off. BXT does this
1443 		 * too, so maybe it saves some power even though
1444 		 * CL2 doesn't exist?
1445 		 */
1446 		tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1447 		tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1448 		vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1449 	}
1450 
1451 	vlv_dpio_put(dev_priv);
1452 
1453 	dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1454 	intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1455 		       dev_priv->display.power.chv_phy_control);
1456 
1457 	drm_dbg_kms(&dev_priv->drm,
1458 		    "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1459 		    phy, dev_priv->display.power.chv_phy_control);
1460 
1461 	assert_chv_phy_status(dev_priv);
1462 }
1463 
chv_dpio_cmn_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1464 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1465 					    struct i915_power_well *power_well)
1466 {
1467 	enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1468 	enum dpio_phy phy;
1469 
1470 	drm_WARN_ON_ONCE(&dev_priv->drm,
1471 			 id != VLV_DISP_PW_DPIO_CMN_BC &&
1472 			 id != CHV_DISP_PW_DPIO_CMN_D);
1473 
1474 	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
1475 		phy = DPIO_PHY0;
1476 		assert_pll_disabled(dev_priv, PIPE_A);
1477 		assert_pll_disabled(dev_priv, PIPE_B);
1478 	} else {
1479 		phy = DPIO_PHY1;
1480 		assert_pll_disabled(dev_priv, PIPE_C);
1481 	}
1482 
1483 	dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1484 	intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1485 		       dev_priv->display.power.chv_phy_control);
1486 
1487 	vlv_set_power_well(dev_priv, power_well, false);
1488 
1489 	drm_dbg_kms(&dev_priv->drm,
1490 		    "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1491 		    phy, dev_priv->display.power.chv_phy_control);
1492 
1493 	/* PHY is fully reset now, so we can enable the PHY state asserts */
1494 	dev_priv->display.power.chv_phy_assert[phy] = true;
1495 
1496 	assert_chv_phy_status(dev_priv);
1497 }
1498 
assert_chv_phy_powergate(struct drm_i915_private * dev_priv,enum dpio_phy phy,enum dpio_channel ch,bool override,unsigned int mask)1499 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1500 				     enum dpio_channel ch, bool override, unsigned int mask)
1501 {
1502 	enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1503 	u32 reg, val, expected, actual;
1504 
1505 	/*
1506 	 * The BIOS can leave the PHY is some weird state
1507 	 * where it doesn't fully power down some parts.
1508 	 * Disable the asserts until the PHY has been fully
1509 	 * reset (ie. the power well has been disabled at
1510 	 * least once).
1511 	 */
1512 	if (!dev_priv->display.power.chv_phy_assert[phy])
1513 		return;
1514 
1515 	if (ch == DPIO_CH0)
1516 		reg = _CHV_CMN_DW0_CH0;
1517 	else
1518 		reg = _CHV_CMN_DW6_CH1;
1519 
1520 	vlv_dpio_get(dev_priv);
1521 	val = vlv_dpio_read(dev_priv, pipe, reg);
1522 	vlv_dpio_put(dev_priv);
1523 
1524 	/*
1525 	 * This assumes !override is only used when the port is disabled.
1526 	 * All lanes should power down even without the override when
1527 	 * the port is disabled.
1528 	 */
1529 	if (!override || mask == 0xf) {
1530 		expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1531 		/*
1532 		 * If CH1 common lane is not active anymore
1533 		 * (eg. for pipe B DPLL) the entire channel will
1534 		 * shut down, which causes the common lane registers
1535 		 * to read as 0. That means we can't actually check
1536 		 * the lane power down status bits, but as the entire
1537 		 * register reads as 0 it's a good indication that the
1538 		 * channel is indeed entirely powered down.
1539 		 */
1540 		if (ch == DPIO_CH1 && val == 0)
1541 			expected = 0;
1542 	} else if (mask != 0x0) {
1543 		expected = DPIO_ANYDL_POWERDOWN;
1544 	} else {
1545 		expected = 0;
1546 	}
1547 
1548 	if (ch == DPIO_CH0)
1549 		actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1550 	else
1551 		actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1552 	actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1553 
1554 	drm_WARN(&dev_priv->drm, actual != expected,
1555 		 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1556 		 !!(actual & DPIO_ALLDL_POWERDOWN),
1557 		 !!(actual & DPIO_ANYDL_POWERDOWN),
1558 		 !!(expected & DPIO_ALLDL_POWERDOWN),
1559 		 !!(expected & DPIO_ANYDL_POWERDOWN),
1560 		 reg, val);
1561 }
1562 
chv_phy_powergate_ch(struct drm_i915_private * dev_priv,enum dpio_phy phy,enum dpio_channel ch,bool override)1563 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1564 			  enum dpio_channel ch, bool override)
1565 {
1566 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1567 	bool was_override;
1568 
1569 	mutex_lock(&power_domains->lock);
1570 
1571 	was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1572 
1573 	if (override == was_override)
1574 		goto out;
1575 
1576 	if (override)
1577 		dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1578 	else
1579 		dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1580 
1581 	intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1582 		       dev_priv->display.power.chv_phy_control);
1583 
1584 	drm_dbg_kms(&dev_priv->drm,
1585 		    "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1586 		    phy, ch, dev_priv->display.power.chv_phy_control);
1587 
1588 	assert_chv_phy_status(dev_priv);
1589 
1590 out:
1591 	mutex_unlock(&power_domains->lock);
1592 
1593 	return was_override;
1594 }
1595 
chv_phy_powergate_lanes(struct intel_encoder * encoder,bool override,unsigned int mask)1596 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1597 			     bool override, unsigned int mask)
1598 {
1599 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1600 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1601 	enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1602 	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
1603 
1604 	mutex_lock(&power_domains->lock);
1605 
1606 	dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1607 	dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1608 
1609 	if (override)
1610 		dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1611 	else
1612 		dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1613 
1614 	intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1615 		       dev_priv->display.power.chv_phy_control);
1616 
1617 	drm_dbg_kms(&dev_priv->drm,
1618 		    "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1619 		    phy, ch, mask, dev_priv->display.power.chv_phy_control);
1620 
1621 	assert_chv_phy_status(dev_priv);
1622 
1623 	assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1624 
1625 	mutex_unlock(&power_domains->lock);
1626 }
1627 
chv_pipe_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1628 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1629 					struct i915_power_well *power_well)
1630 {
1631 	enum pipe pipe = PIPE_A;
1632 	bool enabled;
1633 	u32 state, ctrl;
1634 
1635 	vlv_punit_get(dev_priv);
1636 
1637 	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
1638 	/*
1639 	 * We only ever set the power-on and power-gate states, anything
1640 	 * else is unexpected.
1641 	 */
1642 	drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
1643 		    state != DP_SSS_PWR_GATE(pipe));
1644 	enabled = state == DP_SSS_PWR_ON(pipe);
1645 
1646 	/*
1647 	 * A transient state at this point would mean some unexpected party
1648 	 * is poking at the power controls too.
1649 	 */
1650 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
1651 	drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
1652 
1653 	vlv_punit_put(dev_priv);
1654 
1655 	return enabled;
1656 }
1657 
chv_set_pipe_power_well(struct drm_i915_private * dev_priv,struct i915_power_well * power_well,bool enable)1658 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1659 				    struct i915_power_well *power_well,
1660 				    bool enable)
1661 {
1662 	enum pipe pipe = PIPE_A;
1663 	u32 state;
1664 	u32 ctrl;
1665 
1666 	state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1667 
1668 	vlv_punit_get(dev_priv);
1669 
1670 #define COND \
1671 	((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
1672 
1673 	if (COND)
1674 		goto out;
1675 
1676 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
1677 	ctrl &= ~DP_SSC_MASK(pipe);
1678 	ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1679 	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
1680 
1681 	if (wait_for(COND, 100))
1682 		drm_err(&dev_priv->drm,
1683 			"timeout setting power well state %08x (%08x)\n",
1684 			state,
1685 			vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
1686 
1687 #undef COND
1688 
1689 out:
1690 	vlv_punit_put(dev_priv);
1691 }
1692 
chv_pipe_power_well_sync_hw(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1693 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1694 					struct i915_power_well *power_well)
1695 {
1696 	intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1697 		       dev_priv->display.power.chv_phy_control);
1698 }
1699 
chv_pipe_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1700 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1701 				       struct i915_power_well *power_well)
1702 {
1703 	chv_set_pipe_power_well(dev_priv, power_well, true);
1704 
1705 	vlv_display_power_well_init(dev_priv);
1706 }
1707 
chv_pipe_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1708 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1709 					struct i915_power_well *power_well)
1710 {
1711 	vlv_display_power_well_deinit(dev_priv);
1712 
1713 	chv_set_pipe_power_well(dev_priv, power_well, false);
1714 }
1715 
1716 static void
tgl_tc_cold_request(struct drm_i915_private * i915,bool block)1717 tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
1718 {
1719 	u8 tries = 0;
1720 	int ret;
1721 
1722 	while (1) {
1723 		u32 low_val;
1724 		u32 high_val = 0;
1725 
1726 		if (block)
1727 			low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
1728 		else
1729 			low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
1730 
1731 		/*
1732 		 * Spec states that we should timeout the request after 200us
1733 		 * but the function below will timeout after 500us
1734 		 */
1735 		ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
1736 		if (ret == 0) {
1737 			if (block &&
1738 			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
1739 				ret = -EIO;
1740 			else
1741 				break;
1742 		}
1743 
1744 		if (++tries == 3)
1745 			break;
1746 
1747 		msleep(1);
1748 	}
1749 
1750 	if (ret)
1751 		drm_err(&i915->drm, "TC cold %sblock failed\n",
1752 			block ? "" : "un");
1753 	else
1754 		drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
1755 			    block ? "" : "un");
1756 }
1757 
1758 static void
tgl_tc_cold_off_power_well_enable(struct drm_i915_private * i915,struct i915_power_well * power_well)1759 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
1760 				  struct i915_power_well *power_well)
1761 {
1762 	tgl_tc_cold_request(i915, true);
1763 }
1764 
1765 static void
tgl_tc_cold_off_power_well_disable(struct drm_i915_private * i915,struct i915_power_well * power_well)1766 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
1767 				   struct i915_power_well *power_well)
1768 {
1769 	tgl_tc_cold_request(i915, false);
1770 }
1771 
1772 static void
tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private * i915,struct i915_power_well * power_well)1773 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
1774 				   struct i915_power_well *power_well)
1775 {
1776 	if (intel_power_well_refcount(power_well) > 0)
1777 		tgl_tc_cold_off_power_well_enable(i915, power_well);
1778 	else
1779 		tgl_tc_cold_off_power_well_disable(i915, power_well);
1780 }
1781 
1782 static bool
tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1783 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
1784 				      struct i915_power_well *power_well)
1785 {
1786 	/*
1787 	 * Not the correctly implementation but there is no way to just read it
1788 	 * from PCODE, so returning count to avoid state mismatch errors
1789 	 */
1790 	return intel_power_well_refcount(power_well);
1791 }
1792 
xelpdp_aux_power_well_enable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1793 static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
1794 					 struct i915_power_well *power_well)
1795 {
1796 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1797 
1798 	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
1799 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
1800 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
1801 
1802 	/*
1803 	 * The power status flag cannot be used to determine whether aux
1804 	 * power wells have finished powering up.  Instead we're
1805 	 * expected to just wait a fixed 600us after raising the request
1806 	 * bit.
1807 	 */
1808 	usleep_range(600, 1200);
1809 }
1810 
xelpdp_aux_power_well_disable(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1811 static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
1812 					  struct i915_power_well *power_well)
1813 {
1814 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1815 
1816 	intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
1817 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
1818 		     0);
1819 	usleep_range(10, 30);
1820 }
1821 
xelpdp_aux_power_well_enabled(struct drm_i915_private * dev_priv,struct i915_power_well * power_well)1822 static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
1823 					  struct i915_power_well *power_well)
1824 {
1825 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
1826 
1827 	return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
1828 		XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
1829 }
1830 
1831 const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1832 	.sync_hw = i9xx_power_well_sync_hw_noop,
1833 	.enable = i9xx_always_on_power_well_noop,
1834 	.disable = i9xx_always_on_power_well_noop,
1835 	.is_enabled = i9xx_always_on_power_well_enabled,
1836 };
1837 
1838 const struct i915_power_well_ops chv_pipe_power_well_ops = {
1839 	.sync_hw = chv_pipe_power_well_sync_hw,
1840 	.enable = chv_pipe_power_well_enable,
1841 	.disable = chv_pipe_power_well_disable,
1842 	.is_enabled = chv_pipe_power_well_enabled,
1843 };
1844 
1845 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1846 	.sync_hw = i9xx_power_well_sync_hw_noop,
1847 	.enable = chv_dpio_cmn_power_well_enable,
1848 	.disable = chv_dpio_cmn_power_well_disable,
1849 	.is_enabled = vlv_power_well_enabled,
1850 };
1851 
1852 const struct i915_power_well_ops i830_pipes_power_well_ops = {
1853 	.sync_hw = i830_pipes_power_well_sync_hw,
1854 	.enable = i830_pipes_power_well_enable,
1855 	.disable = i830_pipes_power_well_disable,
1856 	.is_enabled = i830_pipes_power_well_enabled,
1857 };
1858 
1859 static const struct i915_power_well_regs hsw_power_well_regs = {
1860 	.bios	= HSW_PWR_WELL_CTL1,
1861 	.driver	= HSW_PWR_WELL_CTL2,
1862 	.kvmr	= HSW_PWR_WELL_CTL3,
1863 	.debug	= HSW_PWR_WELL_CTL4,
1864 };
1865 
1866 const struct i915_power_well_ops hsw_power_well_ops = {
1867 	.regs = &hsw_power_well_regs,
1868 	.sync_hw = hsw_power_well_sync_hw,
1869 	.enable = hsw_power_well_enable,
1870 	.disable = hsw_power_well_disable,
1871 	.is_enabled = hsw_power_well_enabled,
1872 };
1873 
1874 const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1875 	.sync_hw = i9xx_power_well_sync_hw_noop,
1876 	.enable = gen9_dc_off_power_well_enable,
1877 	.disable = gen9_dc_off_power_well_disable,
1878 	.is_enabled = gen9_dc_off_power_well_enabled,
1879 };
1880 
1881 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1882 	.sync_hw = i9xx_power_well_sync_hw_noop,
1883 	.enable = bxt_dpio_cmn_power_well_enable,
1884 	.disable = bxt_dpio_cmn_power_well_disable,
1885 	.is_enabled = bxt_dpio_cmn_power_well_enabled,
1886 };
1887 
1888 const struct i915_power_well_ops vlv_display_power_well_ops = {
1889 	.sync_hw = i9xx_power_well_sync_hw_noop,
1890 	.enable = vlv_display_power_well_enable,
1891 	.disable = vlv_display_power_well_disable,
1892 	.is_enabled = vlv_power_well_enabled,
1893 };
1894 
1895 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1896 	.sync_hw = i9xx_power_well_sync_hw_noop,
1897 	.enable = vlv_dpio_cmn_power_well_enable,
1898 	.disable = vlv_dpio_cmn_power_well_disable,
1899 	.is_enabled = vlv_power_well_enabled,
1900 };
1901 
1902 const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1903 	.sync_hw = i9xx_power_well_sync_hw_noop,
1904 	.enable = vlv_power_well_enable,
1905 	.disable = vlv_power_well_disable,
1906 	.is_enabled = vlv_power_well_enabled,
1907 };
1908 
1909 static const struct i915_power_well_regs icl_aux_power_well_regs = {
1910 	.bios	= ICL_PWR_WELL_CTL_AUX1,
1911 	.driver	= ICL_PWR_WELL_CTL_AUX2,
1912 	.debug	= ICL_PWR_WELL_CTL_AUX4,
1913 };
1914 
1915 const struct i915_power_well_ops icl_aux_power_well_ops = {
1916 	.regs = &icl_aux_power_well_regs,
1917 	.sync_hw = hsw_power_well_sync_hw,
1918 	.enable = icl_aux_power_well_enable,
1919 	.disable = icl_aux_power_well_disable,
1920 	.is_enabled = hsw_power_well_enabled,
1921 };
1922 
1923 static const struct i915_power_well_regs icl_ddi_power_well_regs = {
1924 	.bios	= ICL_PWR_WELL_CTL_DDI1,
1925 	.driver	= ICL_PWR_WELL_CTL_DDI2,
1926 	.debug	= ICL_PWR_WELL_CTL_DDI4,
1927 };
1928 
1929 const struct i915_power_well_ops icl_ddi_power_well_ops = {
1930 	.regs = &icl_ddi_power_well_regs,
1931 	.sync_hw = hsw_power_well_sync_hw,
1932 	.enable = hsw_power_well_enable,
1933 	.disable = hsw_power_well_disable,
1934 	.is_enabled = hsw_power_well_enabled,
1935 };
1936 
1937 const struct i915_power_well_ops tgl_tc_cold_off_ops = {
1938 	.sync_hw = tgl_tc_cold_off_power_well_sync_hw,
1939 	.enable = tgl_tc_cold_off_power_well_enable,
1940 	.disable = tgl_tc_cold_off_power_well_disable,
1941 	.is_enabled = tgl_tc_cold_off_power_well_is_enabled,
1942 };
1943 
1944 const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
1945 	.sync_hw = i9xx_power_well_sync_hw_noop,
1946 	.enable = xelpdp_aux_power_well_enable,
1947 	.disable = xelpdp_aux_power_well_disable,
1948 	.is_enabled = xelpdp_aux_power_well_enabled,
1949 };
1950