Lines Matching refs:PIPE_A
24 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
32 return PIPE_A; in intel_crtc_pch_transcoder()
119 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
127 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
138 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
146 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
548 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
550 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
556 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
581 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
591 assert_pch_transcoder_disabled(dev_priv, PIPE_A); in lpt_pch_enable()
596 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); in lpt_pch_enable()
622 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); in lpt_pch_get_config()