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/linux-5.19.10/arch/arm64/boot/dts/renesas/
Dr8a774a1-beacon-rzg2m-kit.dts44 clocks = <&cpg CPG_MOD 724>,
45 <&cpg CPG_MOD 723>,
46 <&cpg CPG_MOD 722>,
56 clocks = <&cpg CPG_MOD 1005>,
57 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
58 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
59 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
60 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
61 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
62 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
[all …]
Dr8a774e1-beacon-rzg2h-kit.dts45 clocks = <&cpg CPG_MOD 724>,
46 <&cpg CPG_MOD 723>,
47 <&cpg CPG_MOD 721>,
57 clocks = <&cpg CPG_MOD 1005>,
58 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
59 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
60 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
61 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
62 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
63 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
[all …]
Dr8a774b1-beacon-rzg2n-kit.dts40 clocks = <&cpg CPG_MOD 724>,
41 <&cpg CPG_MOD 723>,
42 <&cpg CPG_MOD 721>,
52 clocks = <&cpg CPG_MOD 1005>,
53 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
54 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
55 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
56 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
57 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
58 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
[all …]
Dr9a07g043.dtsi9 #include <dt-bindings/clock/r9a07g043-cpg.h>
83 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
115 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
116 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
119 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
122 power-domains = <&cpg>;
136 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
137 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
140 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
143 power-domains = <&cpg>;
[all …]
Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
180 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
181 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
184 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
187 power-domains = <&cpg>;
201 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
202 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
205 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
[all …]
Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
180 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
181 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
184 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
187 power-domains = <&cpg>;
201 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
202 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
205 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
[all …]
Dhihope-rev4.dtsi99 clocks = <&cpg CPG_MOD 1005>,
100 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
101 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
102 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
103 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
104 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
105 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
106 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
107 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
108 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
149 clocks = <&cpg CPG_MOD 402>;
151 resets = <&cpg 402>;
165 clocks = <&cpg CPG_MOD 912>;
167 resets = <&cpg 912>;
180 clocks = <&cpg CPG_MOD 911>;
182 resets = <&cpg 911>;
195 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
93 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
105 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
175 clocks = <&cpg CPG_MOD 402>;
177 resets = <&cpg 402>;
191 clocks = <&cpg CPG_MOD 912>;
193 resets = <&cpg 912>;
206 clocks = <&cpg CPG_MOD 911>;
208 resets = <&cpg 911>;
221 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
98 clocks = <&cpg CPG_MOD 402>;
100 resets = <&cpg 402>;
114 clocks = <&cpg CPG_MOD 912>;
116 resets = <&cpg 912>;
129 clocks = <&cpg CPG_MOD 911>;
131 resets = <&cpg 911>;
144 clocks = <&cpg CPG_MOD 910>;
146 resets = <&cpg 910>;
159 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a774b1.dtsi10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
85 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
96 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
160 clocks = <&cpg CPG_MOD 402>;
162 resets = <&cpg 402>;
176 clocks = <&cpg CPG_MOD 912>;
178 resets = <&cpg 912>;
191 clocks = <&cpg CPG_MOD 911>;
193 resets = <&cpg 911>;
206 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
119 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
131 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
209 clocks = <&cpg CPG_MOD 402>;
211 resets = <&cpg 402>;
225 clocks = <&cpg CPG_MOD 912>;
227 resets = <&cpg 912>;
240 clocks = <&cpg CPG_MOD 911>;
242 resets = <&cpg 911>;
255 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
207 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
223 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
236 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
249 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
262 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
373 clocks = <&cpg CPG_MOD 402>;
[all …]
/linux-5.19.10/drivers/clk/renesas/
DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
Dclk-sh73a0.c75 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
86 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
91 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
120 void __iomem *dsi_reg = cpg->reg + in sh73a0_cpg_register_clock()
157 cpg->reg + reg, shift, width, 0, in sh73a0_cpg_register_clock()
158 table, &cpg->lock); in sh73a0_cpg_register_clock()
164 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
175 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
177 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
[all …]
/linux-5.19.10/arch/arm/boot/dts/
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
77 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
165 clocks = <&cpg CPG_MOD 402>;
167 resets = <&cpg 402>;
181 clocks = <&cpg CPG_MOD 912>;
183 resets = <&cpg 912>;
196 clocks = <&cpg CPG_MOD 911>;
198 resets = <&cpg 911>;
211 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
73 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7742.dtsi8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
56 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
154 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
164 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
174 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
248 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
150 clocks = <&cpg CPG_MOD 402>;
152 resets = <&cpg 402>;
166 clocks = <&cpg CPG_MOD 912>;
168 resets = <&cpg 912>;
181 clocks = <&cpg CPG_MOD 911>;
183 resets = <&cpg 911>;
196 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
132 clocks = <&cpg CPG_MOD 402>;
134 resets = <&cpg 402>;
148 clocks = <&cpg CPG_MOD 912>;
150 resets = <&cpg 912>;
163 clocks = <&cpg CPG_MOD 911>;
165 resets = <&cpg 911>;
178 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
58 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
115 clocks = <&cpg CPG_MOD 402>;
117 resets = <&cpg 402>;
131 clocks = <&cpg CPG_MOD 912>;
133 resets = <&cpg 912>;
146 clocks = <&cpg CPG_MOD 911>;
148 resets = <&cpg 911>;
161 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
58 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
144 clocks = <&cpg CPG_MOD 402>;
146 resets = <&cpg 402>;
160 clocks = <&cpg CPG_MOD 912>;
162 resets = <&cpg 912>;
175 clocks = <&cpg CPG_MOD 911>;
177 resets = <&cpg 911>;
190 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
122 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
144 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
166 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
178 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
190 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
202 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
278 clocks = <&cpg CPG_MOD 402>;
[all …]

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