Lines Matching refs:cpg
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
180 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
181 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
184 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
187 power-domains = <&cpg>;
201 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
202 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
205 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
208 power-domains = <&cpg>;
222 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
223 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
226 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
229 power-domains = <&cpg>;
243 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
244 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
247 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
250 power-domains = <&cpg>;
262 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
263 resets = <&cpg R9A07G044_RSPI0_RST>;
264 power-domains = <&cpg>;
278 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
279 resets = <&cpg R9A07G044_RSPI1_RST>;
280 power-domains = <&cpg>;
294 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
295 resets = <&cpg R9A07G044_RSPI2_RST>;
296 power-domains = <&cpg>;
314 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
316 power-domains = <&cpg>;
317 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
332 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
334 power-domains = <&cpg>;
335 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
350 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
352 power-domains = <&cpg>;
353 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
368 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
370 power-domains = <&cpg>;
371 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
386 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
388 power-domains = <&cpg>;
389 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
401 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
403 power-domains = <&cpg>;
404 resets = <&cpg R9A07G044_SCI0_RST>;
416 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
418 power-domains = <&cpg>;
419 resets = <&cpg R9A07G044_SCI1_RST>;
437 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
438 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
441 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
443 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
444 <&cpg R9A07G044_CANFD_RSTC_N>;
446 power-domains = <&cpg>;
472 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
474 resets = <&cpg R9A07G044_I2C0_MRST>;
475 power-domains = <&cpg>;
494 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
496 resets = <&cpg R9A07G044_I2C1_MRST>;
497 power-domains = <&cpg>;
516 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
518 resets = <&cpg R9A07G044_I2C2_MRST>;
519 power-domains = <&cpg>;
538 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
540 resets = <&cpg R9A07G044_I2C3_MRST>;
541 power-domains = <&cpg>;
549 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
550 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
552 resets = <&cpg R9A07G044_ADC_PRESETN>,
553 <&cpg R9A07G044_ADC_ADRST_N>;
555 power-domains = <&cpg>;
591 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
592 resets = <&cpg R9A07G044_TSU_PRESETN>;
593 power-domains = <&cpg>;
605 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
606 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
607 resets = <&cpg R9A07G044_SPI_RST>;
608 power-domains = <&cpg>;
614 cpg: clock-controller@11010000 { label
615 compatible = "renesas,r9a07g044-cpg";
642 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
643 power-domains = <&cpg>;
644 resets = <&cpg R9A07G044_GPIO_RSTN>,
645 <&cpg R9A07G044_GPIO_PORT_RESETN>,
646 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
676 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
677 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
678 power-domains = <&cpg>;
679 resets = <&cpg R9A07G044_DMAC_ARESETN>,
680 <&cpg R9A07G044_DMAC_RST_ASYNC>;
694 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
695 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
696 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
698 power-domains = <&cpg>;
699 resets = <&cpg R9A07G044_GPU_RESETN>,
700 <&cpg R9A07G044_GPU_AXI_RESETN>,
701 <&cpg R9A07G044_GPU_ACE_RESETN>;
722 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
723 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
724 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
725 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
727 resets = <&cpg R9A07G044_SDHI0_IXRST>;
728 power-domains = <&cpg>;
738 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
739 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
740 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
741 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
743 resets = <&cpg R9A07G044_SDHI1_IXRST>;
744 power-domains = <&cpg>;
757 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
758 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
759 <&cpg CPG_CORE R9A07G044_CLK_HP>;
761 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
762 power-domains = <&cpg>;
777 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
778 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
779 <&cpg CPG_CORE R9A07G044_CLK_HP>;
781 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
782 power-domains = <&cpg>;
792 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
793 resets = <&cpg R9A07G044_USB_PRESETN>;
794 power-domains = <&cpg>;
803 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
804 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
806 <&cpg R9A07G044_USB_U2H0_HRESETN>;
809 power-domains = <&cpg>;
817 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
818 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
820 <&cpg R9A07G044_USB_U2H1_HRESETN>;
823 power-domains = <&cpg>;
831 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
832 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
834 <&cpg R9A07G044_USB_U2H0_HRESETN>;
838 power-domains = <&cpg>;
846 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
847 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
849 <&cpg R9A07G044_USB_U2H1_HRESETN>;
853 power-domains = <&cpg>;
862 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
863 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
866 power-domains = <&cpg>;
875 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
876 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
879 power-domains = <&cpg>;
891 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
892 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
894 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
898 power-domains = <&cpg>;
906 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
907 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
912 resets = <&cpg R9A07G044_WDT0_PRESETN>;
913 power-domains = <&cpg>;
921 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
922 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
927 resets = <&cpg R9A07G044_WDT1_PRESETN>;
928 power-domains = <&cpg>;
936 clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
937 <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
942 resets = <&cpg R9A07G044_WDT2_PRESETN>;
943 power-domains = <&cpg>;
952 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
953 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
954 power-domains = <&cpg>;
963 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
964 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
965 power-domains = <&cpg>;
974 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
975 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
976 power-domains = <&cpg>;