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Searched refs:hwc (Results 1 – 25 of 103) sorted by relevance

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/linux-6.6.21/drivers/net/ethernet/microsoft/mana/
Dhw_channel.c7 static int mana_hwc_get_msg_index(struct hw_channel_context *hwc, u16 *msg_id) in mana_hwc_get_msg_index() argument
9 struct gdma_resource *r = &hwc->inflight_msg_res; in mana_hwc_get_msg_index()
13 down(&hwc->sema); in mana_hwc_get_msg_index()
17 index = find_first_zero_bit(hwc->inflight_msg_res.map, in mana_hwc_get_msg_index()
18 hwc->inflight_msg_res.size); in mana_hwc_get_msg_index()
20 bitmap_set(hwc->inflight_msg_res.map, index, 1); in mana_hwc_get_msg_index()
29 static void mana_hwc_put_msg_index(struct hw_channel_context *hwc, u16 msg_id) in mana_hwc_put_msg_index() argument
31 struct gdma_resource *r = &hwc->inflight_msg_res; in mana_hwc_put_msg_index()
35 bitmap_clear(hwc->inflight_msg_res.map, msg_id, 1); in mana_hwc_put_msg_index()
38 up(&hwc->sema); in mana_hwc_put_msg_index()
[all …]
/linux-6.6.21/drivers/net/ethernet/mellanox/mlx5/core/sf/
Dhw_table.c36 struct mlx5_sf_hwc_table hwc[MLX5_SF_HWC_MAX]; member
44 return &dev->priv.sf_hw_table->hwc[idx]; in mlx5_sf_controller_to_hwc()
49 struct mlx5_sf_hwc_table *hwc; in mlx5_sf_sw_to_hw_id() local
51 hwc = mlx5_sf_controller_to_hwc(dev, controller); in mlx5_sf_sw_to_hw_id()
52 return hwc->start_fn_id + sw_id; in mlx5_sf_sw_to_hw_id()
55 static u16 mlx5_sf_hw_to_sw_id(struct mlx5_sf_hwc_table *hwc, u16 hw_id) in mlx5_sf_hw_to_sw_id() argument
57 return hw_id - hwc->start_fn_id; in mlx5_sf_hw_to_sw_id()
65 for (i = 0; i < ARRAY_SIZE(table->hwc); i++) { in mlx5_sf_table_fn_to_hwc()
66 if (table->hwc[i].max_fn && in mlx5_sf_table_fn_to_hwc()
67 fn_id >= table->hwc[i].start_fn_id && in mlx5_sf_table_fn_to_hwc()
[all …]
/linux-6.6.21/drivers/iio/buffer/
Dindustrialio-hw-consumer.c53 struct iio_hw_consumer *hwc, struct iio_dev *indio_dev) in iio_hw_consumer_get_buffer() argument
57 list_for_each_entry(buf, &hwc->buffers, head) { in iio_hw_consumer_get_buffer()
72 list_add_tail(&buf->head, &hwc->buffers); in iio_hw_consumer_get_buffer()
86 struct iio_hw_consumer *hwc; in iio_hw_consumer_alloc() local
90 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); in iio_hw_consumer_alloc()
91 if (!hwc) in iio_hw_consumer_alloc()
94 INIT_LIST_HEAD(&hwc->buffers); in iio_hw_consumer_alloc()
96 hwc->channels = iio_channel_get_all(dev); in iio_hw_consumer_alloc()
97 if (IS_ERR(hwc->channels)) { in iio_hw_consumer_alloc()
98 ret = PTR_ERR(hwc->channels); in iio_hw_consumer_alloc()
[all …]
/linux-6.6.21/arch/alpha/kernel/
Dperf_event.c253 struct hw_perf_event *hwc, int idx) in alpha_perf_event_set_period() argument
255 long left = local64_read(&hwc->period_left); in alpha_perf_event_set_period()
256 long period = hwc->sample_period; in alpha_perf_event_set_period()
261 local64_set(&hwc->period_left, left); in alpha_perf_event_set_period()
262 hwc->last_period = period; in alpha_perf_event_set_period()
268 local64_set(&hwc->period_left, left); in alpha_perf_event_set_period()
269 hwc->last_period = period; in alpha_perf_event_set_period()
283 local64_set(&hwc->prev_count, (unsigned long)(-left)); in alpha_perf_event_set_period()
308 struct hw_perf_event *hwc, int idx, long ovf) in alpha_perf_event_update() argument
314 prev_raw_count = local64_read(&hwc->prev_count); in alpha_perf_event_update()
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/linux-6.6.21/drivers/perf/
Driscv_pmu.c151 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_ctr_get_width_mask() local
153 if (hwc->idx == -1) in riscv_pmu_ctr_get_width_mask()
157 cwidth = rvpmu->ctr_get_width(hwc->idx); in riscv_pmu_ctr_get_width_mask()
165 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_event_update() local
176 prev_raw_count = local64_read(&hwc->prev_count); in riscv_pmu_event_update()
178 oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count, in riscv_pmu_event_update()
184 local64_sub(delta, &hwc->period_left); in riscv_pmu_event_update()
191 struct hw_perf_event *hwc = &event->hw; in riscv_pmu_stop() local
194 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); in riscv_pmu_stop()
196 if (!(hwc->state & PERF_HES_STOPPED)) { in riscv_pmu_stop()
[all …]
Dthunderx2_pmu.c325 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_l3c() local
332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
334 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
341 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_dmc() local
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
350 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
357 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_ccpi2() local
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
364 hwc->event_base = (unsigned long)tx2_pmu->base; in init_cntr_base_ccpi2()
370 struct hw_perf_event *hwc = &event->hw; in uncore_start_event_l3c() local
[all …]
Darm_pmu.c203 struct hw_perf_event *hwc = &event->hw; in armpmu_event_set_period() local
204 s64 left = local64_read(&hwc->period_left); in armpmu_event_set_period()
205 s64 period = hwc->sample_period; in armpmu_event_set_period()
212 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
213 hwc->last_period = period; in armpmu_event_set_period()
219 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
220 hwc->last_period = period; in armpmu_event_set_period()
233 local64_set(&hwc->prev_count, (u64)-left); in armpmu_event_set_period()
245 struct hw_perf_event *hwc = &event->hw; in armpmu_event_update() local
250 prev_raw_count = local64_read(&hwc->prev_count); in armpmu_event_update()
[all …]
Dqcom_l2_pmu.c299 struct hw_perf_event *hwc = &event->hw; in l2_cache_event_update() local
301 u32 idx = hwc->idx; in l2_cache_event_update()
304 prev = local64_read(&hwc->prev_count); in l2_cache_event_update()
306 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); in l2_cache_event_update()
320 struct hw_perf_event *hwc) in l2_cache_cluster_set_period() argument
322 u32 idx = hwc->idx; in l2_cache_cluster_set_period()
335 local64_set(&hwc->prev_count, new); in l2_cache_cluster_set_period()
342 struct hw_perf_event *hwc = &event->hw; in l2_cache_get_event_idx() local
347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_get_event_idx()
364 group = L2_EVT_GROUP(hwc->config_base); in l2_cache_get_event_idx()
[all …]
Dmarvell_cn10k_ddr_pmu.c326 struct hw_perf_event *hwc = &event->hw; in cn10k_ddr_perf_event_init() local
350 hwc->idx = -1; in cn10k_ddr_perf_event_init()
409 struct hw_perf_event *hwc = &event->hw; in cn10k_ddr_perf_event_update() local
413 prev_count = local64_read(&hwc->prev_count); in cn10k_ddr_perf_event_update()
414 new_count = cn10k_ddr_perf_read_counter(pmu, hwc->idx); in cn10k_ddr_perf_event_update()
415 } while (local64_xchg(&hwc->prev_count, new_count) != prev_count); in cn10k_ddr_perf_event_update()
425 struct hw_perf_event *hwc = &event->hw; in cn10k_ddr_perf_event_start() local
426 int counter = hwc->idx; in cn10k_ddr_perf_event_start()
428 local64_set(&hwc->prev_count, 0); in cn10k_ddr_perf_event_start()
432 hwc->state = 0; in cn10k_ddr_perf_event_start()
[all …]
/linux-6.6.21/arch/s390/include/asm/
Dperf_event.h67 #define OVERFLOW_REG(hwc) ((hwc)->extra_reg.config) argument
68 #define SFB_ALLOC_REG(hwc) ((hwc)->extra_reg.alloc) argument
69 #define TEAR_REG(hwc) ((hwc)->last_tag) argument
70 #define SAMPL_RATE(hwc) ((hwc)->event_base) argument
71 #define SAMPL_FLAGS(hwc) ((hwc)->config_base) argument
72 #define SAMPL_DIAG_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_DIAG_MODE) argument
73 #define SAMPLE_FREQ_MODE(hwc) (SAMPL_FLAGS(hwc) & PERF_CPUM_SF_FREQ_MODE) argument
/linux-6.6.21/arch/loongarch/kernel/
Dperf_event.c253 static int loongarch_pmu_alloc_counter(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc) in loongarch_pmu_alloc_counter() argument
300 struct hw_perf_event *hwc, in loongarch_pmu_event_set_period() argument
304 u64 left = local64_read(&hwc->period_left); in loongarch_pmu_event_set_period()
305 u64 period = hwc->sample_period; in loongarch_pmu_event_set_period()
310 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
311 hwc->last_period = period; in loongarch_pmu_event_set_period()
316 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
317 hwc->last_period = period; in loongarch_pmu_event_set_period()
323 local64_set(&hwc->period_left, left); in loongarch_pmu_event_set_period()
326 local64_set(&hwc->prev_count, loongarch_pmu.overflow - left); in loongarch_pmu_event_set_period()
[all …]
/linux-6.6.21/arch/x86/events/amd/
Diommu.c208 struct hw_perf_event *hwc = &event->hw; in perf_iommu_event_init() local
226 hwc->conf = event->attr.config; in perf_iommu_event_init()
227 hwc->conf1 = event->attr.config1; in perf_iommu_event_init()
240 struct hw_perf_event *hwc = &ev->hw; in perf_iommu_enable_event() local
241 u8 bank = hwc->iommu_bank; in perf_iommu_enable_event()
242 u8 cntr = hwc->iommu_cntr; in perf_iommu_enable_event()
245 reg = GET_CSOURCE(hwc); in perf_iommu_enable_event()
248 reg = GET_DEVID_MASK(hwc); in perf_iommu_enable_event()
249 reg = GET_DEVID(hwc) | (reg << 32); in perf_iommu_enable_event()
254 reg = GET_PASID_MASK(hwc); in perf_iommu_enable_event()
[all …]
Duncore.c84 struct hw_perf_event *hwc = &event->hw; in amd_uncore_read() local
93 prev = local64_read(&hwc->prev_count); in amd_uncore_read()
94 rdpmcl(hwc->event_base_rdpmc, new); in amd_uncore_read()
95 local64_set(&hwc->prev_count, new); in amd_uncore_read()
103 struct hw_perf_event *hwc = &event->hw; in amd_uncore_start() local
106 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
108 hwc->state = 0; in amd_uncore_start()
109 wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); in amd_uncore_start()
115 struct hw_perf_event *hwc = &event->hw; in amd_uncore_stop() local
117 wrmsrl(hwc->config_base, hwc->config); in amd_uncore_stop()
[all …]
Dibs.c101 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period) in perf_event_set_period() argument
103 s64 left = local64_read(&hwc->period_left); in perf_event_set_period()
104 s64 period = hwc->sample_period; in perf_event_set_period()
112 local64_set(&hwc->period_left, left); in perf_event_set_period()
113 hwc->last_period = period; in perf_event_set_period()
119 local64_set(&hwc->period_left, left); in perf_event_set_period()
120 hwc->last_period = period; in perf_event_set_period()
146 struct hw_perf_event *hwc = &event->hw; in perf_event_try_update() local
158 prev_raw_count = local64_read(&hwc->prev_count); in perf_event_try_update()
159 if (!local64_try_cmpxchg(&hwc->prev_count, in perf_event_try_update()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pmu.c211 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_event_init() local
218 hwc->config = event->attr.config; in amdgpu_perf_event_init()
219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
227 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_start() local
233 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) in amdgpu_perf_start()
240 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in amdgpu_perf_start()
241 hwc->state = 0; in amdgpu_perf_start()
243 switch (hwc->config_base) { in amdgpu_perf_start()
248 hwc->config, 0 /* unused */, in amdgpu_perf_start()
253 hwc->idx = target_cntr; in amdgpu_perf_start()
[all …]
/linux-6.6.21/arch/xtensa/kernel/
Dperf_event.c146 struct hw_perf_event *hwc, int idx) in xtensa_perf_event_update() argument
152 prev_raw_count = local64_read(&hwc->prev_count); in xtensa_perf_event_update()
154 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in xtensa_perf_event_update()
160 local64_sub(delta, &hwc->period_left); in xtensa_perf_event_update()
164 struct hw_perf_event *hwc, int idx) in xtensa_perf_event_set_period() argument
172 s64 period = hwc->sample_period; in xtensa_perf_event_set_period()
174 left = local64_read(&hwc->period_left); in xtensa_perf_event_set_period()
177 local64_set(&hwc->period_left, left); in xtensa_perf_event_set_period()
178 hwc->last_period = period; in xtensa_perf_event_set_period()
182 local64_set(&hwc->period_left, left); in xtensa_perf_event_set_period()
[all …]
/linux-6.6.21/drivers/perf/hisilicon/
Dhisi_uncore_pmu.c186 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_event_init() local
225 hwc->idx = -1; in hisi_uncore_pmu_event_init()
226 hwc->config_base = event->attr.config; in hisi_uncore_pmu_event_init()
245 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_enable_event() local
247 hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx, in hisi_uncore_pmu_enable_event()
253 hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
254 hisi_pmu->ops->enable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
263 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_disable_event() local
265 hisi_pmu->ops->disable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
266 hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
[all …]
Dhisi_uncore_ddrc_pmu.c59 #define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7) argument
82 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v1_read_counter() argument
85 hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx)); in hisi_ddrc_pmu_v1_read_counter()
89 struct hw_perf_event *hwc, u64 val) in hisi_ddrc_pmu_v1_write_counter() argument
92 ddrc_pmu->base + hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx)); in hisi_ddrc_pmu_v1_write_counter()
96 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v2_read_counter() argument
99 hisi_ddrc_pmu_v2_get_counter_offset(hwc->idx)); in hisi_ddrc_pmu_v2_read_counter()
103 struct hw_perf_event *hwc, u64 val) in hisi_ddrc_pmu_v2_write_counter() argument
106 ddrc_pmu->base + hisi_ddrc_pmu_v2_get_counter_offset(hwc->idx)); in hisi_ddrc_pmu_v2_write_counter()
146 struct hw_perf_event *hwc) in hisi_ddrc_pmu_v1_enable_counter() argument
[all …]
Dhisi_pcie_pmu.c222 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_config_filter() local
259 hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg); in hisi_pcie_pmu_config_filter()
265 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_clear_filter() local
267 hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, HISI_PCIE_INIT_SET); in hisi_pcie_pmu_clear_filter()
354 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_event_init() local
363 hwc->event_base = HISI_PCIE_EXT_CNT; in hisi_pcie_pmu_event_init()
365 hwc->event_base = HISI_PCIE_CNT; in hisi_pcie_pmu_event_init()
426 struct hw_perf_event *hwc = &event->hw; in hisi_pcie_pmu_event_update() local
430 prev_cnt = local64_read(&hwc->prev_count); in hisi_pcie_pmu_event_update()
432 } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, in hisi_pcie_pmu_event_update()
[all …]
/linux-6.6.21/arch/arc/kernel/
Dperf_event.c281 struct hw_perf_event *hwc, int idx) in arc_perf_event_update() argument
283 u64 prev_raw_count = local64_read(&hwc->prev_count); in arc_perf_event_update()
291 local64_set(&hwc->prev_count, new_raw_count); in arc_perf_event_update()
293 local64_sub(delta, &hwc->period_left); in arc_perf_event_update()
331 struct hw_perf_event *hwc = &event->hw; in arc_pmu_event_init() local
335 hwc->sample_period = arc_pmu->max_period; in arc_pmu_event_init()
336 hwc->last_period = hwc->sample_period; in arc_pmu_event_init()
337 local64_set(&hwc->period_left, hwc->sample_period); in arc_pmu_event_init()
340 hwc->config = 0; in arc_pmu_event_init()
345 hwc->config |= ARC_REG_PCT_CONFIG_KERN; in arc_pmu_event_init()
[all …]
/linux-6.6.21/arch/arm/kernel/
Dperf_event_xscale.c175 struct hw_perf_event *hwc; in xscale1pmu_handle_irq() local
183 hwc = &event->hw; in xscale1pmu_handle_irq()
185 perf_sample_data_init(&data, 0, hwc->last_period); in xscale1pmu_handle_irq()
208 struct hw_perf_event *hwc = &event->hw; in xscale1pmu_enable_event() local
210 int idx = hwc->idx; in xscale1pmu_enable_event()
219 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
224 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
244 struct hw_perf_event *hwc = &event->hw; in xscale1pmu_disable_event() local
246 int idx = hwc->idx; in xscale1pmu_disable_event()
278 struct hw_perf_event *hwc = &event->hw; in xscale1pmu_get_event_idx() local
[all …]
/linux-6.6.21/arch/x86/events/intel/
Duncore_nhmex.c247 struct hw_perf_event *hwc = &event->hw; in nhmex_uncore_msr_enable_event() local
249 if (hwc->idx == UNCORE_PMC_IDX_FIXED) in nhmex_uncore_msr_enable_event()
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
352 struct hw_perf_event *hwc = &event->hw; in nhmex_bbox_hw_config() local
353 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_hw_config()
354 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; in nhmex_bbox_hw_config()
357 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >> in nhmex_bbox_hw_config()
359 ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >> in nhmex_bbox_hw_config()
[all …]
/linux-6.6.21/arch/sh/kernel/
Dperf_event.c103 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init() local
153 hwc->config |= config; in __hw_perf_event_init()
159 struct hw_perf_event *hwc, int idx) in sh_perf_event_update() argument
178 prev_raw_count = local64_read(&hwc->prev_count); in sh_perf_event_update()
181 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in sh_perf_event_update()
202 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop() local
203 int idx = hwc->idx; in sh_pmu_stop()
206 sh_pmu->disable(hwc, idx); in sh_pmu_stop()
220 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start() local
221 int idx = hwc->idx; in sh_pmu_start()
[all …]
/linux-6.6.21/arch/s390/kernel/
Dperf_cpum_sf.c384 static unsigned long sfb_max_limit(struct hw_perf_event *hwc) in sfb_max_limit() argument
386 return SAMPL_DIAG_MODE(hwc) ? CPUM_SF_MAX_SDB * CPUM_SF_SDB_DIAG_FACTOR in sfb_max_limit()
391 struct hw_perf_event *hwc) in sfb_pending_allocs() argument
394 return SFB_ALLOC_REG(hwc); in sfb_pending_allocs()
395 if (SFB_ALLOC_REG(hwc) > sfb->num_sdb) in sfb_pending_allocs()
396 return SFB_ALLOC_REG(hwc) - sfb->num_sdb; in sfb_pending_allocs()
401 struct hw_perf_event *hwc) in sfb_has_pending_allocs() argument
403 return sfb_pending_allocs(sfb, hwc) > 0; in sfb_has_pending_allocs()
406 static void sfb_account_allocs(unsigned long num, struct hw_perf_event *hwc) in sfb_account_allocs() argument
409 num = min_t(unsigned long, num, sfb_max_limit(hwc) - SFB_ALLOC_REG(hwc)); in sfb_account_allocs()
[all …]
/linux-6.6.21/arch/mips/kernel/
Dperf_event_mipsxx.c315 struct hw_perf_event *hwc) in mipsxx_pmu_alloc_counter() argument
325 cntr_mask = (hwc->event_base >> 10) & 0xffff; in mipsxx_pmu_alloc_counter()
327 cntr_mask = (hwc->event_base >> 8) & 0xffff; in mipsxx_pmu_alloc_counter()
410 struct hw_perf_event *hwc, in mipspmu_event_set_period() argument
413 u64 left = local64_read(&hwc->period_left); in mipspmu_event_set_period()
414 u64 period = hwc->sample_period; in mipspmu_event_set_period()
420 local64_set(&hwc->period_left, left); in mipspmu_event_set_period()
421 hwc->last_period = period; in mipspmu_event_set_period()
426 local64_set(&hwc->period_left, left); in mipspmu_event_set_period()
427 hwc->last_period = period; in mipspmu_event_set_period()
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