222 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_config_filter()  local
259 	hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg);  in hisi_pcie_pmu_config_filter()
265 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_clear_filter()  local
267 	hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, HISI_PCIE_INIT_SET);  in hisi_pcie_pmu_clear_filter()
354 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_event_init()  local
363 		hwc->event_base = HISI_PCIE_EXT_CNT;  in hisi_pcie_pmu_event_init()
365 		hwc->event_base = HISI_PCIE_CNT;  in hisi_pcie_pmu_event_init()
426 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_event_update()  local
430 		prev_cnt = local64_read(&hwc->prev_count);  in hisi_pcie_pmu_event_update()
432 	} while (local64_cmpxchg(&hwc->prev_count, prev_cnt,  in hisi_pcie_pmu_event_update()
447 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_set_period()  local
448 	int idx = hwc->idx;  in hisi_pcie_pmu_set_period()
450 	local64_set(&hwc->prev_count, HISI_PCIE_INIT_VAL);  in hisi_pcie_pmu_set_period()
455 static void hisi_pcie_pmu_enable_counter(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc)  in hisi_pcie_pmu_enable_counter()  argument
457 	u32 idx = hwc->idx;  in hisi_pcie_pmu_enable_counter()
465 static void hisi_pcie_pmu_disable_counter(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc)  in hisi_pcie_pmu_disable_counter()  argument
467 	u32 idx = hwc->idx;  in hisi_pcie_pmu_disable_counter()
475 static void hisi_pcie_pmu_enable_int(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc)  in hisi_pcie_pmu_enable_int()  argument
477 	u32 idx = hwc->idx;  in hisi_pcie_pmu_enable_int()
482 static void hisi_pcie_pmu_disable_int(struct hisi_pcie_pmu *pcie_pmu, struct hw_perf_event *hwc)  in hisi_pcie_pmu_disable_int()  argument
484 	u32 idx = hwc->idx;  in hisi_pcie_pmu_disable_int()
498 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_start()  local
499 	int idx = hwc->idx;  in hisi_pcie_pmu_start()
502 	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))  in hisi_pcie_pmu_start()
505 	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in hisi_pcie_pmu_start()
506 	hwc->state = 0;  in hisi_pcie_pmu_start()
509 	hisi_pcie_pmu_enable_counter(pcie_pmu, hwc);  in hisi_pcie_pmu_start()
510 	hisi_pcie_pmu_enable_int(pcie_pmu, hwc);  in hisi_pcie_pmu_start()
514 		prev_cnt = local64_read(&hwc->prev_count);  in hisi_pcie_pmu_start()
515 		hisi_pcie_pmu_writeq(pcie_pmu, hwc->event_base, idx, prev_cnt);  in hisi_pcie_pmu_start()
524 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_stop()  local
527 	hisi_pcie_pmu_disable_int(pcie_pmu, hwc);  in hisi_pcie_pmu_stop()
528 	hisi_pcie_pmu_disable_counter(pcie_pmu, hwc);  in hisi_pcie_pmu_stop()
530 	WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);  in hisi_pcie_pmu_stop()
531 	hwc->state |= PERF_HES_STOPPED;  in hisi_pcie_pmu_stop()
533 	if (hwc->state & PERF_HES_UPTODATE)  in hisi_pcie_pmu_stop()
536 	hwc->state |= PERF_HES_UPTODATE;  in hisi_pcie_pmu_stop()
542 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_add()  local
545 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in hisi_pcie_pmu_add()
554 		hwc->idx = idx;  in hisi_pcie_pmu_add()
562 	hwc->idx = idx;  in hisi_pcie_pmu_add()
577 	struct hw_perf_event *hwc = &event->hw;  in hisi_pcie_pmu_del()  local
580 	pcie_pmu->hw_events[hwc->idx] = NULL;  in hisi_pcie_pmu_del()