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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c287 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_hw_fini()
357 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
359 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
361 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v4_0_mc_resume()
364 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
366 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
369 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_mc_resume()
371 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); in vcn_v4_0_mc_resume()
374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
376 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v4_0_mc_resume()
[all …]
Dvcn_v2_5.c93 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v2_5_early_init()
173 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
175 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
177 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
179 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
181 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
339 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
406 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
408 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
410 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
[all …]
Dvcn_v3_0.c166 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); in vcn_v3_0_sw_init()
168 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); in vcn_v3_0_sw_init()
170 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); in vcn_v3_0_sw_init()
172 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); in vcn_v3_0_sw_init()
174 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); in vcn_v3_0_sw_init()
386 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
452 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
454 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
456 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
459 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
[all …]
Dvcn_v2_0.c273 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
495 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
502 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
504 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
525 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
527 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
548 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
551 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
576 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
578 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
[all …]
Dvcn_v1_0.c239 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
453 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
462 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
464 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
466 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
469 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
477 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
479 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
500 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
502 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
[all …]
Damdgpu_vcn.h137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
147 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
148 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
Djpeg_v4_0.c140 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, in jpeg_v4_0_hw_init()
/linux-6.1.9/fs/ntfs/
Drunlist.h29 VCN vcn; /* vcn = Starting virtual cluster number. */
65 extern LCN ntfs_rl_vcn_to_lcn(const runlist_element *rl, const VCN vcn);
70 const VCN vcn);
73 const runlist_element *rl, const VCN first_vcn,
74 const VCN last_vcn);
78 const VCN first_vcn, const VCN last_vcn, VCN *const stop_vcn);
84 const VCN start, const s64 length);
Dattrib.h49 extern int ntfs_map_runlist_nolock(ntfs_inode *ni, VCN vcn,
51 extern int ntfs_map_runlist(ntfs_inode *ni, VCN vcn);
53 extern LCN ntfs_attr_vcn_to_lcn_nolock(ntfs_inode *ni, const VCN vcn,
57 const VCN vcn, ntfs_attr_search_ctx *ctx);
61 const VCN lowest_vcn, const u8 *val, const u32 val_len,
Dlcnalloc.h30 const VCN start_vcn, const s64 count, const LCN start_lcn,
34 extern s64 __ntfs_cluster_free(ntfs_inode *ni, const VCN start_vcn,
93 static inline s64 ntfs_cluster_free(ntfs_inode *ni, const VCN start_vcn, in ntfs_cluster_free()
Drunlist.c527 VCN marker_vcn = 0; in ntfs_runlists_merge()
738 VCN vcn; /* Current vcn. */ in ntfs_mapping_pairs_decompress()
752 attr->data.non_resident.lowest_vcn) < (VCN)0) { in ntfs_mapping_pairs_decompress()
900 VCN max_cluster; in ntfs_mapping_pairs_decompress()
990 LCN ntfs_rl_vcn_to_lcn(const runlist_element *rl, const VCN vcn) in ntfs_rl_vcn_to_lcn()
1039 runlist_element *ntfs_rl_find_vcn_nolock(runlist_element *rl, const VCN vcn) in ntfs_rl_find_vcn_nolock()
1118 const runlist_element *rl, const VCN first_vcn, in ntfs_get_size_for_mapping_pairs()
1119 const VCN last_vcn) in ntfs_get_size_for_mapping_pairs()
1311 const VCN first_vcn, const VCN last_vcn, VCN *const stop_vcn) in ntfs_mapping_pairs_build()
1631 const VCN start, const s64 length) in ntfs_rl_punch_nolock()
[all …]
Dtypes.h29 typedef s64 VCN; typedef
Daops.c167 VCN vcn; in ntfs_read_block()
242 vcn = (VCN)iblock << blocksize_bits >> in ntfs_read_block()
244 vcn_ofs = ((VCN)iblock << blocksize_bits) & in ntfs_read_block()
533 VCN vcn; in ntfs_write_block()
701 vcn = (VCN)block << blocksize_bits; in ntfs_write_block()
1004 VCN vcn; in ntfs_write_mst_block()
1010 vcn = (VCN)block << bh_size_bits; in ntfs_write_mst_block()
Dattrib.c70 int ntfs_map_runlist_nolock(ntfs_inode *ni, VCN vcn, ntfs_attr_search_ctx *ctx) in ntfs_map_runlist_nolock()
72 VCN end_vcn; in ntfs_map_runlist_nolock()
100 VCN allocated_size_vcn; in ntfs_map_runlist_nolock()
284 int ntfs_map_runlist(ntfs_inode *ni, VCN vcn) in ntfs_map_runlist()
327 LCN ntfs_attr_vcn_to_lcn_nolock(ntfs_inode *ni, const VCN vcn, in ntfs_attr_vcn_to_lcn_nolock()
450 runlist_element *ntfs_attr_find_vcn_nolock(ntfs_inode *ni, const VCN vcn, in ntfs_attr_find_vcn_nolock()
869 const IGNORE_CASE_BOOL ic, const VCN lowest_vcn, in ntfs_external_attr_find()
1199 const VCN lowest_vcn, const u8 *val, const u32 val_len, in ntfs_attr_lookup()
1917 VCN vcn; in ntfs_attr_extend_allocation()
Dcompress.c478 VCN vcn; in ntfs_read_compressed_block()
481 VCN start_vcn = (((s64)index << PAGE_SHIFT) & ~cb_size_mask) >> in ntfs_read_compressed_block()
487 VCN end_vcn = ((((s64)(index + 1UL) << PAGE_SHIFT) + cb_size - 1) in ntfs_read_compressed_block()
Dlcnalloc.c132 runlist_element *ntfs_cluster_alloc(ntfs_volume *vol, const VCN start_vcn, in ntfs_cluster_alloc()
835 s64 __ntfs_cluster_free(ntfs_inode *ni, const VCN start_vcn, s64 count, in __ntfs_cluster_free()
916 VCN vcn; in __ntfs_cluster_free()
Dfile.c566 VCN vcn, highest_vcn = 0, cpos, cend, bh_cpos, bh_cend; in ntfs_prepare_pages_for_non_resident_write()
638 VCN cdelta; in ntfs_prepare_pages_for_non_resident_write()
1729 VCN last_vcn; in ntfs_perform_write()
1769 VCN vcn; in ntfs_perform_write()
Dindex.c108 VCN vcn, old_vcn; in ntfs_index_lookup()
Dmft.c525 VCN vcn; in ntfs_sync_mft_mirror()
531 vcn = ((VCN)mft_no << vol->mft_record_size_bits) + in ntfs_sync_mft_mirror()
718 VCN vcn; in write_mft_record_nolock()
724 vcn = ((VCN)ni->mft_no << vol->mft_record_size_bits) + in write_mft_record_nolock()
1712 VCN old_last_vcn; in ntfs_mft_data_extend_allocation_nolock()
Dlogfile.c714 VCN vcn, end_vcn; in ntfs_empty_logfile()
Ddir.c80 VCN vcn, old_vcn; in ntfs_lookup_inode_by_name()
634 VCN vcn, old_vcn;
/linux-6.1.9/Documentation/gpu/amdgpu/
Dapu-asic-info-table.csv1 Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version
3 …es / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
4 Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
5 Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.…
6 SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
7 Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
8 Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
Ddgpu-asic-info-table.csv1 Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
17 MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
18 MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
19 AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
20 AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0…
21 AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
22 AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
23 AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
24 AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
Damdgpu-glossary.rst99 VCN
Ddriver-core.rst74 VCN (Video Core Next)

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