287                                 RREG32_SOC15(VCN, i, regUVD_STATUS))) {  in vcn_v4_0_hw_fini()
357 		WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v4_0_mc_resume()
359 		WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v4_0_mc_resume()
361 		WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);  in vcn_v4_0_mc_resume()
364 		WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v4_0_mc_resume()
366 		WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v4_0_mc_resume()
369                 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);  in vcn_v4_0_mc_resume()
371 	WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);  in vcn_v4_0_mc_resume()
374 	WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,  in vcn_v4_0_mc_resume()
376 	WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,  in vcn_v4_0_mc_resume()
378 	WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);  in vcn_v4_0_mc_resume()
379 	WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);  in vcn_v4_0_mc_resume()
382 	WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,  in vcn_v4_0_mc_resume()
384 	WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,  in vcn_v4_0_mc_resume()
386 	WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);  in vcn_v4_0_mc_resume()
387 	WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);  in vcn_v4_0_mc_resume()
390 	WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,  in vcn_v4_0_mc_resume()
392 	WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,  in vcn_v4_0_mc_resume()
394 	WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);  in vcn_v4_0_mc_resume()
395 	WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,  in vcn_v4_0_mc_resume()
419 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v4_0_mc_resume_dpg_mode()
422 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v4_0_mc_resume_dpg_mode()
425 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
428 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
430 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
432 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
437 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v4_0_mc_resume_dpg_mode()
440 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v4_0_mc_resume_dpg_mode()
444 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),  in vcn_v4_0_mc_resume_dpg_mode()
450 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
453 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
458 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),  in vcn_v4_0_mc_resume_dpg_mode()
461 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),  in vcn_v4_0_mc_resume_dpg_mode()
464 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
467 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
469 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
471 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
474 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
478 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),  in vcn_v4_0_mc_resume_dpg_mode()
481 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),  in vcn_v4_0_mc_resume_dpg_mode()
484 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
486 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
490 			VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),  in vcn_v4_0_mc_resume_dpg_mode()
493 			VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),  in vcn_v4_0_mc_resume_dpg_mode()
496 			VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
498 			VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),  in vcn_v4_0_mc_resume_dpg_mode()
503 		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
534 		WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);  in vcn_v4_0_disable_static_power_gating()
535 		SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,  in vcn_v4_0_disable_static_power_gating()
556                 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);  in vcn_v4_0_disable_static_power_gating()
557                 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value,  0x3F3FFFFF);  in vcn_v4_0_disable_static_power_gating()
560         data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);  in vcn_v4_0_disable_static_power_gating()
566         WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);  in vcn_v4_0_disable_static_power_gating()
585 		data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);  in vcn_v4_0_enable_static_power_gating()
588 		WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);  in vcn_v4_0_enable_static_power_gating()
604 		WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);  in vcn_v4_0_enable_static_power_gating()
620 		SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);  in vcn_v4_0_enable_static_power_gating()
642 	data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);  in vcn_v4_0_disable_clock_gating()
646 	WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);  in vcn_v4_0_disable_clock_gating()
648 	data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);  in vcn_v4_0_disable_clock_gating()
670 	WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);  in vcn_v4_0_disable_clock_gating()
671 	SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0,  0xFFFFFFFF);  in vcn_v4_0_disable_clock_gating()
673 	data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);  in vcn_v4_0_disable_clock_gating()
694 	WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);  in vcn_v4_0_disable_clock_gating()
696 	data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);  in vcn_v4_0_disable_clock_gating()
721 	WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);  in vcn_v4_0_disable_clock_gating()
723 	data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);  in vcn_v4_0_disable_clock_gating()
734 	WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);  in vcn_v4_0_disable_clock_gating()
779 		VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
783 		VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
787 		VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
791 		VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
810 	data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);  in vcn_v4_0_enable_clock_gating()
814 	WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);  in vcn_v4_0_enable_clock_gating()
816 	data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);  in vcn_v4_0_enable_clock_gating()
837 	WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);  in vcn_v4_0_enable_clock_gating()
839 	data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);  in vcn_v4_0_enable_clock_gating()
850 	WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);  in vcn_v4_0_enable_clock_gating()
871 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,  in vcn_v4_0_start_dpg_mode()
874 	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);  in vcn_v4_0_start_dpg_mode()
877 	WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);  in vcn_v4_0_start_dpg_mode()
889 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
893 		VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v4_0_start_dpg_mode()
905 		VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
908 		VCN, inst_idx, regUVD_MPC_CNTL),  in vcn_v4_0_start_dpg_mode()
912 		VCN, inst_idx, regUVD_MPC_SET_MUXA0),  in vcn_v4_0_start_dpg_mode()
919 		VCN, inst_idx, regUVD_MPC_SET_MUXB0),  in vcn_v4_0_start_dpg_mode()
926 		VCN, inst_idx, regUVD_MPC_SET_MUX),  in vcn_v4_0_start_dpg_mode()
936 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
941 		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
945 		VCN, inst_idx, regUVD_MASTINT_EN),  in vcn_v4_0_start_dpg_mode()
956 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v4_0_start_dpg_mode()
957 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v4_0_start_dpg_mode()
958 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v4_0_start_dpg_mode()
960 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);  in vcn_v4_0_start_dpg_mode()
962 	WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);  in vcn_v4_0_start_dpg_mode()
964 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);  in vcn_v4_0_start_dpg_mode()
965 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);  in vcn_v4_0_start_dpg_mode()
967 	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);  in vcn_v4_0_start_dpg_mode()
968 	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);  in vcn_v4_0_start_dpg_mode()
969 	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);  in vcn_v4_0_start_dpg_mode()
971 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);  in vcn_v4_0_start_dpg_mode()
973 	WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);  in vcn_v4_0_start_dpg_mode()
976 	WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,  in vcn_v4_0_start_dpg_mode()
1013 		tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;  in vcn_v4_0_start()
1014 		WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);  in vcn_v4_0_start()
1020 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),  in vcn_v4_0_start()
1024 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,  in vcn_v4_0_start()
1028 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,  in vcn_v4_0_start()
1031 		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);  in vcn_v4_0_start()
1034 		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);  in vcn_v4_0_start()
1037 		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);  in vcn_v4_0_start()
1038 		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |  in vcn_v4_0_start()
1045 		tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);  in vcn_v4_0_start()
1048 		WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);  in vcn_v4_0_start()
1051 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,  in vcn_v4_0_start()
1058 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,  in vcn_v4_0_start()
1065 		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,  in vcn_v4_0_start()
1073 		WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,  in vcn_v4_0_start()
1077 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,  in vcn_v4_0_start()
1081 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,  in vcn_v4_0_start()
1088 				status = RREG32_SOC15(VCN, i, regUVD_STATUS);  in vcn_v4_0_start()
1108 				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),  in vcn_v4_0_start()
1112 				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,  in vcn_v4_0_start()
1126 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),  in vcn_v4_0_start()
1131 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,  in vcn_v4_0_start()
1135 		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,  in vcn_v4_0_start()
1139 		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v4_0_start()
1140 		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v4_0_start()
1141 		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v4_0_start()
1143 		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);  in vcn_v4_0_start()
1145 		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);  in vcn_v4_0_start()
1147 		WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);  in vcn_v4_0_start()
1148 		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);  in vcn_v4_0_start()
1150 		tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);  in vcn_v4_0_start()
1151 		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);  in vcn_v4_0_start()
1152 		ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);  in vcn_v4_0_start()
1154 		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);  in vcn_v4_0_start()
1156 		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);  in vcn_v4_0_start()
1214 		MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1221 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1224 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1228 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1232 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1235 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1239 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1244 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1249 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1252 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1255 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1258 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1264 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1267 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1270 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1273 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1290 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1293 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1296 		MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,  in vcn_v4_0_start_sriov()
1320 	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));  in vcn_v4_0_start_sriov()
1321 	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));  in vcn_v4_0_start_sriov()
1324 	tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);  in vcn_v4_0_start_sriov()
1328 	WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);  in vcn_v4_0_start_sriov()
1332 	WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);  in vcn_v4_0_start_sriov()
1335 	WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);  in vcn_v4_0_start_sriov()
1341 	WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);  in vcn_v4_0_start_sriov()
1347 		resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);  in vcn_v4_0_start_sriov()
1384 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,  in vcn_v4_0_stop_dpg_mode()
1388 	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);  in vcn_v4_0_stop_dpg_mode()
1389 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v4_0_stop_dpg_mode()
1391 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,  in vcn_v4_0_stop_dpg_mode()
1395 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,  in vcn_v4_0_stop_dpg_mode()
1422 		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);  in vcn_v4_0_stop()
1430 		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);  in vcn_v4_0_stop()
1435 		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);  in vcn_v4_0_stop()
1437 		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);  in vcn_v4_0_stop()
1440 		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);  in vcn_v4_0_stop()
1445 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),  in vcn_v4_0_stop()
1450 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),  in vcn_v4_0_stop()
1455 		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,  in vcn_v4_0_stop()
1459 		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);  in vcn_v4_0_stop()
1461 		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);  in vcn_v4_0_stop()
1462 		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);  in vcn_v4_0_stop()
1464 		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);  in vcn_v4_0_stop()
1467 		WREG32_SOC15(VCN, i, regUVD_STATUS, 0);  in vcn_v4_0_stop()
1501 		reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &  in vcn_v4_0_pause_dpg_mode()
1505 			ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,  in vcn_v4_0_pause_dpg_mode()
1511 				WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);  in vcn_v4_0_pause_dpg_mode()
1514 				SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,  in vcn_v4_0_pause_dpg_mode()
1518 				SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,  in vcn_v4_0_pause_dpg_mode()
1524 			WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);  in vcn_v4_0_pause_dpg_mode()
1546 	return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);  in vcn_v4_0_unified_ring_get_rptr()
1566 		return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);  in vcn_v4_0_unified_ring_get_wptr()
1587 		WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v4_0_unified_ring_set_wptr()
1790 		ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v4_0_is_idle()
1812 		ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v4_0_wait_for_idle()
1840 			if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)  in vcn_v4_0_set_clockgating_state()