Searched refs:PORT_BASE (Results 1 – 8 of 8) sorted by relevance
112 #define PORT_BASE (0x800) macro114 #define PHY_CFG (PORT_BASE + 0x0)119 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)126 #define PHY_CTRL (PORT_BASE + 0x14)129 #define PHY_RATE_NEGO (PORT_BASE + 0x30)130 #define PHY_PCN (PORT_BASE + 0x44)131 #define SL_TOUT_CFG (PORT_BASE + 0x8c)132 #define SL_CONTROL (PORT_BASE + 0x94)135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)136 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)[all …]
170 #define PORT_BASE (0x2000) macro172 #define PHY_CFG (PORT_BASE + 0x0)173 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)178 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)181 #define PHY_CTRL (PORT_BASE + 0x14)184 #define SAS_PHY_CTRL (PORT_BASE + 0x20)185 #define SL_CFG (PORT_BASE + 0x84)186 #define PHY_PCN (PORT_BASE + 0x44)187 #define SL_TOUT_CFG (PORT_BASE + 0x8c)188 #define SL_CONTROL (PORT_BASE + 0x94)[all …]
185 #define PORT_BASE (0x2000) macro186 #define PHY_CFG (PORT_BASE + 0x0)187 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)194 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)199 #define PHY_CTRL (PORT_BASE + 0x14)204 #define SERDES_CFG (PORT_BASE + 0x1c)207 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)218 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)219 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)220 #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)[all …]
417 typeflags, (uint16_t)PORT_BASE, in test_datapath()418 (uint16_t)(PORT_BASE + port_off)); in test_datapath()433 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()434 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
21 #define PORT_BASE 8000 macro
229 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()590 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
70 #define PORT_BASE 0x100 macro184 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))