Lines Matching refs:PORT_BASE
185 #define PORT_BASE (0x2000) macro
186 #define PHY_CFG (PORT_BASE + 0x0)
187 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
194 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
199 #define PHY_CTRL (PORT_BASE + 0x14)
204 #define SERDES_CFG (PORT_BASE + 0x1c)
207 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
218 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
219 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
220 #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
221 #define SL_CFG (PORT_BASE + 0x84)
222 #define AIP_LIMIT (PORT_BASE + 0x90)
223 #define SL_CONTROL (PORT_BASE + 0x94)
228 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
231 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
232 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
233 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
234 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
235 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
236 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
237 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
238 #define TXID_AUTO (PORT_BASE + 0xb8)
243 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
244 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
245 #define STP_LINK_TIMER (PORT_BASE + 0x120)
246 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
247 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
248 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
249 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
250 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
251 #define CHL_INT0 (PORT_BASE + 0x1b4)
262 #define CHL_INT1 (PORT_BASE + 0x1b8)
275 #define CHL_INT2 (PORT_BASE + 0x1bc)
281 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
282 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
283 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
284 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
285 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
286 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
287 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
288 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
289 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
290 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
291 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
292 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
293 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
296 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
300 #define COARSETUNE_TIME (PORT_BASE + 0x304)
301 #define TXDEEMPH_G1 (PORT_BASE + 0x350)
302 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
303 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
304 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
305 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
306 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
307 #define DFX_FIFO_CTRL (PORT_BASE + 0x3a0)
316 #define DFX_FIFO_TRIGGER (PORT_BASE + 0x3a4)
317 #define DFX_FIFO_TRIGGER_MSK (PORT_BASE + 0x3a8)
318 #define DFX_FIFO_DUMP_MSK (PORT_BASE + 0x3aC)
319 #define DFX_FIFO_RD_DATA (PORT_BASE + 0x3b0)
2881 .base_off = PORT_BASE,