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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 25 of 338) sorted by relevance

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/linux-6.1.9/drivers/clk/hisilicon/
Dclk-hi3670.c81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
87 CLK_SET_RATE_PARENT, 0x460, 16, 0, },
89 CLK_SET_RATE_PARENT, 0x460, 18, 0, },
91 CLK_SET_RATE_PARENT, 0x460, 20, 0, },
93 CLK_SET_RATE_PARENT, 0x410, 27, 0, },
95 CLK_SET_RATE_PARENT, 0x410, 28, 0, },
97 CLK_SET_RATE_PARENT, 0x410, 26, 0, },
99 CLK_SET_RATE_PARENT, 0x410, 30, 0, },
[all …]
Dclk-hi3660.c53 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
55 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
57 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
61 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
63 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
71 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
[all …]
Dclk-hi6220.c55 …{ HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12,…
56 …{ HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13,…
57 …{ HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14,…
58 …{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15,…
59 …{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16,…
60 …{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17,…
61 …{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18,…
62 …{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19,…
63 …{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20,…
64 …{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21,…
[all …]
Dclk-hi3620.c86 …{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,…
87 …{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,…
88 …{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,…
89 …{ HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,…
90 …{ HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x…
91 …{ HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x…
92 …{ HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x…
93 …{ HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x…
94 …{ HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x…
95 …{ HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x…
[all …]
Dcrg-hi3798cv200.c76 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
79 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
82 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
84 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
93 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
96 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
103 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
110 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
[all …]
Dclk-hi3559a.c142 CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
146 CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
150 CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
155 CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
160 CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
165 CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
170 CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
175 CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
180 CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
187 CLK_SET_RATE_PARENT, 0x170, 1, 0,
[all …]
Dclk-hix5hd2.c60 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
62 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
64 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
75 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
82 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
85 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
[all …]
Dcrg-hi3516cv300.c70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
89 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
91 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
[all …]
/linux-6.1.9/drivers/clk/mmp/
Dclk-of-pxa168.c123 CLK_SET_RATE_PARENT, in pxa168_pll_init()
161 …{0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0…
162 …{0, "twsi1_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1…
163 …{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3…
164 …{0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4,…
165 …{0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4,…
166 …{0, "pwm2_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4,…
167 …{0, "pwm3_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4,…
168 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
169 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
[all …]
Dclk-of-mmp2.c173 …{MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0…
174 …{MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0…
199 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
206 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
211 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
237 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
238 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
239 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
240 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
241 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
[all …]
Dclk-of-pxa910.c103 CLK_SET_RATE_PARENT, in pxa910_pll_init()
126 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
127 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
128 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
129 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
130 …{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
131 …{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
135 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
139 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
140 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
[all …]
Dclk-of-pxa1928.c77 CLK_SET_RATE_PARENT, in pxa1928_pll_init()
96 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
97 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
98 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
99 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
100 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
101 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
105 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
106 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
107 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
[all …]
Dclk-mmp2.c116 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
120 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
124 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
128 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
132 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
136 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
140 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
144 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
148 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
152 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
[all …]
Dclk-pxa168.c103 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
107 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
111 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
115 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
119 CLK_SET_RATE_PARENT, 1, 3); in pxa168_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
135 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
139 CLK_SET_RATE_PARENT, 1, 13); in pxa168_clk_init()
[all …]
Dclk-pxa910.c108 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
112 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
116 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
120 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
124 CLK_SET_RATE_PARENT, 1, 3); in pxa910_clk_init()
128 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
132 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
136 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
140 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
144 CLK_SET_RATE_PARENT, 1, 13); in pxa910_clk_init()
[all …]
/linux-6.1.9/drivers/clk/rockchip/
Dclk-rk3308.c199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
231 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
235 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-px30.c209 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
213 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
217 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
221 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
225 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
229 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
233 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
237 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
241 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
245 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
[all …]
/linux-6.1.9/drivers/clk/qcom/
Dgcc-ipq8074.c422 .flags = CLK_SET_RATE_PARENT,
469 .flags = CLK_SET_RATE_PARENT,
502 .flags = CLK_SET_RATE_PARENT,
536 .flags = CLK_SET_RATE_PARENT,
550 .flags = CLK_SET_RATE_PARENT,
583 .flags = CLK_SET_RATE_PARENT,
615 .flags = CLK_SET_RATE_PARENT,
650 .flags = CLK_SET_RATE_PARENT,
1009 .flags = CLK_SET_RATE_PARENT,
1052 .flags = CLK_SET_RATE_PARENT,
[all …]
Ddispcc-sm8450.c257 .flags = CLK_SET_RATE_PARENT,
277 .flags = CLK_SET_RATE_PARENT,
292 .flags = CLK_SET_RATE_PARENT,
307 .flags = CLK_SET_RATE_PARENT,
330 .flags = CLK_SET_RATE_PARENT,
345 .flags = CLK_SET_RATE_PARENT,
360 .flags = CLK_SET_RATE_PARENT,
375 .flags = CLK_SET_RATE_PARENT,
390 .flags = CLK_SET_RATE_PARENT,
405 .flags = CLK_SET_RATE_PARENT,
[all …]
Dcamcc-sm8250.c89 .flags = CLK_SET_RATE_PARENT,
112 .flags = CLK_SET_RATE_PARENT,
163 .flags = CLK_SET_RATE_PARENT,
214 .flags = CLK_SET_RATE_PARENT,
265 .flags = CLK_SET_RATE_PARENT,
316 .flags = CLK_SET_RATE_PARENT,
413 .flags = CLK_SET_RATE_PARENT,
435 .flags = CLK_SET_RATE_PARENT,
456 .flags = CLK_SET_RATE_PARENT,
471 .flags = CLK_SET_RATE_PARENT,
[all …]
Dcamcc-sm8450.c102 .flags = CLK_SET_RATE_PARENT,
125 .flags = CLK_SET_RATE_PARENT,
173 .flags = CLK_SET_RATE_PARENT,
244 .flags = CLK_SET_RATE_PARENT,
292 .flags = CLK_SET_RATE_PARENT,
340 .flags = CLK_SET_RATE_PARENT,
388 .flags = CLK_SET_RATE_PARENT,
436 .flags = CLK_SET_RATE_PARENT,
484 .flags = CLK_SET_RATE_PARENT,
612 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-apq8084.c576 .flags = CLK_SET_RATE_PARENT,
590 .flags = CLK_SET_RATE_PARENT,
841 .flags = CLK_SET_RATE_PARENT,
854 .flags = CLK_SET_RATE_PARENT,
892 .flags = CLK_SET_RATE_PARENT,
961 .flags = CLK_SET_RATE_PARENT,
1110 .flags = CLK_SET_RATE_PARENT,
1127 .flags = CLK_SET_RATE_PARENT,
1144 .flags = CLK_SET_RATE_PARENT,
1161 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8996.c108 .flags = CLK_SET_RATE_PARENT,
142 .flags = CLK_SET_RATE_PARENT,
172 .flags = CLK_SET_RATE_PARENT,
202 .flags = CLK_SET_RATE_PARENT,
232 .flags = CLK_SET_RATE_PARENT,
262 .flags = CLK_SET_RATE_PARENT,
292 .flags = CLK_SET_RATE_PARENT,
322 .flags = CLK_SET_RATE_PARENT,
575 .flags = CLK_SET_RATE_PARENT,
694 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-ipq6018.c78 .flags = CLK_SET_RATE_PARENT,
92 .flags = CLK_SET_RATE_PARENT,
136 .flags = CLK_SET_RATE_PARENT,
167 .flags = CLK_SET_RATE_PARENT,
198 .flags = CLK_SET_RATE_PARENT,
249 .flags = CLK_SET_RATE_PARENT,
280 .flags = CLK_SET_RATE_PARENT,
359 .flags = CLK_SET_RATE_PARENT,
412 .flags = CLK_SET_RATE_PARENT,
713 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-sc8180x.c281 .flags = CLK_SET_RATE_PARENT,
304 .flags = CLK_SET_RATE_PARENT,
330 .flags = CLK_SET_RATE_PARENT,
354 .flags = CLK_SET_RATE_PARENT,
369 .flags = CLK_SET_RATE_PARENT,
384 .flags = CLK_SET_RATE_PARENT,
399 .flags = CLK_SET_RATE_PARENT,
414 .flags = CLK_SET_RATE_PARENT,
440 .flags = CLK_SET_RATE_PARENT,
461 .flags = CLK_SET_RATE_PARENT,
[all …]

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