1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Ltd.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/err.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of.h>
14 #include <linux/regmap.h>
15 #include <linux/pm_runtime.h>
16
17 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
18
19 #include "common.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-regmap.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-regmap-mux.h"
27 #include "reset.h"
28 #include "gdsc.h"
29
30 /* Need to match the order of clocks in DT binding */
31 enum {
32 DT_BI_TCXO,
33 DT_BI_TCXO_AO,
34 DT_AHB_CLK,
35 DT_SLEEP_CLK,
36
37 DT_DSI0_PHY_PLL_OUT_BYTECLK,
38 DT_DSI0_PHY_PLL_OUT_DSICLK,
39 DT_DSI1_PHY_PLL_OUT_BYTECLK,
40 DT_DSI1_PHY_PLL_OUT_DSICLK,
41
42 DT_DP0_PHY_PLL_LINK_CLK,
43 DT_DP0_PHY_PLL_VCO_DIV_CLK,
44 DT_DP1_PHY_PLL_LINK_CLK,
45 DT_DP1_PHY_PLL_VCO_DIV_CLK,
46 DT_DP2_PHY_PLL_LINK_CLK,
47 DT_DP2_PHY_PLL_VCO_DIV_CLK,
48 DT_DP3_PHY_PLL_LINK_CLK,
49 DT_DP3_PHY_PLL_VCO_DIV_CLK,
50 };
51
52 #define DISP_CC_MISC_CMD 0xF000
53
54 enum {
55 P_BI_TCXO,
56 P_DISP_CC_PLL0_OUT_MAIN,
57 P_DISP_CC_PLL1_OUT_EVEN,
58 P_DISP_CC_PLL1_OUT_MAIN,
59 P_DP0_PHY_PLL_LINK_CLK,
60 P_DP0_PHY_PLL_VCO_DIV_CLK,
61 P_DP1_PHY_PLL_LINK_CLK,
62 P_DP1_PHY_PLL_VCO_DIV_CLK,
63 P_DP2_PHY_PLL_LINK_CLK,
64 P_DP2_PHY_PLL_VCO_DIV_CLK,
65 P_DP3_PHY_PLL_LINK_CLK,
66 P_DP3_PHY_PLL_VCO_DIV_CLK,
67 P_DSI0_PHY_PLL_OUT_BYTECLK,
68 P_DSI0_PHY_PLL_OUT_DSICLK,
69 P_DSI1_PHY_PLL_OUT_BYTECLK,
70 P_DSI1_PHY_PLL_OUT_DSICLK,
71 P_SLEEP_CLK,
72 };
73
74 static struct pll_vco lucid_evo_vco[] = {
75 { 249600000, 2000000000, 0 },
76 };
77
78 static const struct alpha_pll_config disp_cc_pll0_config = {
79 .l = 0xD,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x32AA299C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
86 };
87
88 static struct clk_alpha_pll disp_cc_pll0 = {
89 .offset = 0x0,
90 .vco_table = lucid_evo_vco,
91 .num_vco = ARRAY_SIZE(lucid_evo_vco),
92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
93 .clkr = {
94 .hw.init = &(struct clk_init_data) {
95 .name = "disp_cc_pll0",
96 .parent_data = &(const struct clk_parent_data) {
97 .index = DT_BI_TCXO,
98 },
99 .num_parents = 1,
100 .ops = &clk_alpha_pll_reset_lucid_evo_ops,
101 },
102 },
103 };
104
105 static const struct alpha_pll_config disp_cc_pll1_config = {
106 .l = 0x1F,
107 .alpha = 0x4000,
108 .config_ctl_val = 0x20485699,
109 .config_ctl_hi_val = 0x00182261,
110 .config_ctl_hi1_val = 0x32AA299C,
111 .user_ctl_val = 0x00000000,
112 .user_ctl_hi_val = 0x00000805,
113 };
114
115 static struct clk_alpha_pll disp_cc_pll1 = {
116 .offset = 0x1000,
117 .vco_table = lucid_evo_vco,
118 .num_vco = ARRAY_SIZE(lucid_evo_vco),
119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
120 .clkr = {
121 .hw.init = &(struct clk_init_data) {
122 .name = "disp_cc_pll1",
123 .parent_data = &(const struct clk_parent_data) {
124 .index = DT_BI_TCXO,
125 },
126 .num_parents = 1,
127 .ops = &clk_alpha_pll_reset_lucid_evo_ops,
128 },
129 },
130 };
131
132 static const struct parent_map disp_cc_parent_map_0[] = {
133 { P_BI_TCXO, 0 },
134 { P_DP0_PHY_PLL_LINK_CLK, 1 },
135 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
136 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
137 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
138 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
139 };
140
141 static const struct clk_parent_data disp_cc_parent_data_0[] = {
142 { .index = DT_BI_TCXO },
143 { .index = DT_DP0_PHY_PLL_LINK_CLK },
144 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
145 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
146 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
147 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
148 };
149
150 static const struct parent_map disp_cc_parent_map_1[] = {
151 { P_BI_TCXO, 0 },
152 };
153
154 static const struct clk_parent_data disp_cc_parent_data_1[] = {
155 { .index = DT_BI_TCXO },
156 };
157
158 static const struct clk_parent_data disp_cc_parent_data_1_ao[] = {
159 { .index = DT_BI_TCXO_AO },
160 };
161
162 static const struct parent_map disp_cc_parent_map_2[] = {
163 { P_BI_TCXO, 0 },
164 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
165 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
166 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
167 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
168 };
169
170 static const struct clk_parent_data disp_cc_parent_data_2[] = {
171 { .index = DT_BI_TCXO },
172 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
173 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
174 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
175 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
176 };
177
178 static const struct parent_map disp_cc_parent_map_3[] = {
179 { P_BI_TCXO, 0 },
180 { P_DP0_PHY_PLL_LINK_CLK, 1 },
181 { P_DP1_PHY_PLL_LINK_CLK, 2 },
182 { P_DP2_PHY_PLL_LINK_CLK, 3 },
183 { P_DP3_PHY_PLL_LINK_CLK, 4 },
184 };
185
186 static const struct clk_parent_data disp_cc_parent_data_3[] = {
187 { .index = DT_BI_TCXO },
188 { .index = DT_DP0_PHY_PLL_LINK_CLK },
189 { .index = DT_DP1_PHY_PLL_LINK_CLK },
190 { .index = DT_DP2_PHY_PLL_LINK_CLK },
191 { .index = DT_DP3_PHY_PLL_LINK_CLK },
192 };
193
194 static const struct parent_map disp_cc_parent_map_4[] = {
195 { P_BI_TCXO, 0 },
196 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
197 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
198 };
199
200 static const struct clk_parent_data disp_cc_parent_data_4[] = {
201 { .index = DT_BI_TCXO },
202 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
203 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
204 };
205
206 static const struct parent_map disp_cc_parent_map_5[] = {
207 { P_BI_TCXO, 0 },
208 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
209 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
210 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
211 };
212
213 static const struct clk_parent_data disp_cc_parent_data_5[] = {
214 { .index = DT_BI_TCXO },
215 { .hw = &disp_cc_pll0.clkr.hw },
216 { .hw = &disp_cc_pll1.clkr.hw },
217 { .hw = &disp_cc_pll1.clkr.hw },
218 };
219
220 static const struct parent_map disp_cc_parent_map_6[] = {
221 { P_BI_TCXO, 0 },
222 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
223 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
224 };
225
226 static const struct clk_parent_data disp_cc_parent_data_6[] = {
227 { .index = DT_BI_TCXO },
228 { .hw = &disp_cc_pll1.clkr.hw },
229 { .hw = &disp_cc_pll1.clkr.hw },
230 };
231
232 static const struct parent_map disp_cc_parent_map_7[] = {
233 { P_SLEEP_CLK, 0 },
234 };
235
236 static const struct clk_parent_data disp_cc_parent_data_7[] = {
237 { .index = DT_SLEEP_CLK },
238 };
239
240 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
241 F(19200000, P_BI_TCXO, 1, 0, 0),
242 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
243 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
244 { }
245 };
246
247 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
248 .cmd_rcgr = 0x8324,
249 .mnd_width = 0,
250 .hid_width = 5,
251 .parent_map = disp_cc_parent_map_6,
252 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
253 .clkr.hw.init = &(struct clk_init_data) {
254 .name = "disp_cc_mdss_ahb_clk_src",
255 .parent_data = disp_cc_parent_data_6,
256 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
257 .flags = CLK_SET_RATE_PARENT,
258 .ops = &clk_rcg2_shared_ops,
259 },
260 };
261
262 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
263 F(19200000, P_BI_TCXO, 1, 0, 0),
264 { }
265 };
266
267 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
268 .cmd_rcgr = 0x8134,
269 .mnd_width = 0,
270 .hid_width = 5,
271 .parent_map = disp_cc_parent_map_2,
272 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
273 .clkr.hw.init = &(struct clk_init_data) {
274 .name = "disp_cc_mdss_byte0_clk_src",
275 .parent_data = disp_cc_parent_data_2,
276 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
277 .flags = CLK_SET_RATE_PARENT,
278 .ops = &clk_byte2_ops,
279 },
280 };
281
282 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
283 .cmd_rcgr = 0x8150,
284 .mnd_width = 0,
285 .hid_width = 5,
286 .parent_map = disp_cc_parent_map_2,
287 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
288 .clkr.hw.init = &(struct clk_init_data) {
289 .name = "disp_cc_mdss_byte1_clk_src",
290 .parent_data = disp_cc_parent_data_2,
291 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
292 .flags = CLK_SET_RATE_PARENT,
293 .ops = &clk_byte2_ops,
294 },
295 };
296
297 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
298 .cmd_rcgr = 0x81ec,
299 .mnd_width = 0,
300 .hid_width = 5,
301 .parent_map = disp_cc_parent_map_1,
302 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
303 .clkr.hw.init = &(struct clk_init_data) {
304 .name = "disp_cc_mdss_dptx0_aux_clk_src",
305 .parent_data = disp_cc_parent_data_1,
306 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
307 .flags = CLK_SET_RATE_PARENT,
308 .ops = &clk_rcg2_ops,
309 },
310 };
311
312 static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
313 F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
314 F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
315 F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
316 F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
317 { }
318 };
319
320 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
321 .cmd_rcgr = 0x819c,
322 .mnd_width = 0,
323 .hid_width = 5,
324 .parent_map = disp_cc_parent_map_3,
325 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
326 .clkr.hw.init = &(struct clk_init_data) {
327 .name = "disp_cc_mdss_dptx0_link_clk_src",
328 .parent_data = disp_cc_parent_data_3,
329 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
330 .flags = CLK_SET_RATE_PARENT,
331 .ops = &clk_rcg2_ops,
332 },
333 };
334
335 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
336 .cmd_rcgr = 0x81bc,
337 .mnd_width = 16,
338 .hid_width = 5,
339 .parent_map = disp_cc_parent_map_0,
340 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
341 .clkr.hw.init = &(struct clk_init_data) {
342 .name = "disp_cc_mdss_dptx0_pixel0_clk_src",
343 .parent_data = disp_cc_parent_data_0,
344 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
345 .flags = CLK_SET_RATE_PARENT,
346 .ops = &clk_dp_ops,
347 },
348 };
349
350 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
351 .cmd_rcgr = 0x81d4,
352 .mnd_width = 16,
353 .hid_width = 5,
354 .parent_map = disp_cc_parent_map_0,
355 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
356 .clkr.hw.init = &(struct clk_init_data) {
357 .name = "disp_cc_mdss_dptx0_pixel1_clk_src",
358 .parent_data = disp_cc_parent_data_0,
359 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
360 .flags = CLK_SET_RATE_PARENT,
361 .ops = &clk_dp_ops,
362 },
363 };
364
365 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
366 .cmd_rcgr = 0x8254,
367 .mnd_width = 0,
368 .hid_width = 5,
369 .parent_map = disp_cc_parent_map_1,
370 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
371 .clkr.hw.init = &(struct clk_init_data) {
372 .name = "disp_cc_mdss_dptx1_aux_clk_src",
373 .parent_data = disp_cc_parent_data_1,
374 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
375 .flags = CLK_SET_RATE_PARENT,
376 .ops = &clk_dp_ops,
377 },
378 };
379
380 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
381 .cmd_rcgr = 0x8234,
382 .mnd_width = 0,
383 .hid_width = 5,
384 .parent_map = disp_cc_parent_map_3,
385 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
386 .clkr.hw.init = &(struct clk_init_data) {
387 .name = "disp_cc_mdss_dptx1_link_clk_src",
388 .parent_data = disp_cc_parent_data_3,
389 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
390 .flags = CLK_SET_RATE_PARENT,
391 .ops = &clk_rcg2_ops,
392 },
393 };
394
395 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
396 .cmd_rcgr = 0x8204,
397 .mnd_width = 16,
398 .hid_width = 5,
399 .parent_map = disp_cc_parent_map_0,
400 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
401 .clkr.hw.init = &(struct clk_init_data) {
402 .name = "disp_cc_mdss_dptx1_pixel0_clk_src",
403 .parent_data = disp_cc_parent_data_0,
404 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
405 .flags = CLK_SET_RATE_PARENT,
406 .ops = &clk_dp_ops,
407 },
408 };
409
410 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
411 .cmd_rcgr = 0x821c,
412 .mnd_width = 16,
413 .hid_width = 5,
414 .parent_map = disp_cc_parent_map_0,
415 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
416 .clkr.hw.init = &(struct clk_init_data) {
417 .name = "disp_cc_mdss_dptx1_pixel1_clk_src",
418 .parent_data = disp_cc_parent_data_0,
419 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
420 .flags = CLK_SET_RATE_PARENT,
421 .ops = &clk_dp_ops,
422 },
423 };
424
425 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
426 .cmd_rcgr = 0x82bc,
427 .mnd_width = 0,
428 .hid_width = 5,
429 .parent_map = disp_cc_parent_map_1,
430 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
431 .clkr.hw.init = &(struct clk_init_data) {
432 .name = "disp_cc_mdss_dptx2_aux_clk_src",
433 .parent_data = disp_cc_parent_data_1,
434 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
435 .flags = CLK_SET_RATE_PARENT,
436 .ops = &clk_rcg2_ops,
437 },
438 };
439
440 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
441 .cmd_rcgr = 0x826c,
442 .mnd_width = 0,
443 .hid_width = 5,
444 .parent_map = disp_cc_parent_map_3,
445 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
446 .clkr.hw.init = &(struct clk_init_data) {
447 .name = "disp_cc_mdss_dptx2_link_clk_src",
448 .parent_data = disp_cc_parent_data_3,
449 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
450 .flags = CLK_SET_RATE_PARENT,
451 .ops = &clk_rcg2_ops,
452 },
453 };
454
455 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
456 .cmd_rcgr = 0x828c,
457 .mnd_width = 16,
458 .hid_width = 5,
459 .parent_map = disp_cc_parent_map_0,
460 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
461 .clkr.hw.init = &(struct clk_init_data) {
462 .name = "disp_cc_mdss_dptx2_pixel0_clk_src",
463 .parent_data = disp_cc_parent_data_0,
464 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
465 .flags = CLK_SET_RATE_PARENT,
466 .ops = &clk_dp_ops,
467 },
468 };
469
470 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
471 .cmd_rcgr = 0x82a4,
472 .mnd_width = 16,
473 .hid_width = 5,
474 .parent_map = disp_cc_parent_map_0,
475 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
476 .clkr.hw.init = &(struct clk_init_data) {
477 .name = "disp_cc_mdss_dptx2_pixel1_clk_src",
478 .parent_data = disp_cc_parent_data_0,
479 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
480 .flags = CLK_SET_RATE_PARENT,
481 .ops = &clk_dp_ops,
482 },
483 };
484
485 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
486 .cmd_rcgr = 0x8308,
487 .mnd_width = 0,
488 .hid_width = 5,
489 .parent_map = disp_cc_parent_map_1,
490 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
491 .clkr.hw.init = &(struct clk_init_data) {
492 .name = "disp_cc_mdss_dptx3_aux_clk_src",
493 .parent_data = disp_cc_parent_data_1,
494 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
495 .flags = CLK_SET_RATE_PARENT,
496 .ops = &clk_rcg2_ops,
497 },
498 };
499
500 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
501 .cmd_rcgr = 0x82ec,
502 .mnd_width = 0,
503 .hid_width = 5,
504 .parent_map = disp_cc_parent_map_3,
505 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
506 .clkr.hw.init = &(struct clk_init_data) {
507 .name = "disp_cc_mdss_dptx3_link_clk_src",
508 .parent_data = disp_cc_parent_data_3,
509 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
510 .flags = CLK_SET_RATE_PARENT,
511 .ops = &clk_rcg2_ops,
512 },
513 };
514
515 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
516 .cmd_rcgr = 0x82d4,
517 .mnd_width = 16,
518 .hid_width = 5,
519 .parent_map = disp_cc_parent_map_0,
520 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
521 .clkr.hw.init = &(struct clk_init_data) {
522 .name = "disp_cc_mdss_dptx3_pixel0_clk_src",
523 .parent_data = disp_cc_parent_data_0,
524 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
525 .flags = CLK_SET_RATE_PARENT,
526 .ops = &clk_dp_ops,
527 },
528 };
529
530 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
531 .cmd_rcgr = 0x816c,
532 .mnd_width = 0,
533 .hid_width = 5,
534 .parent_map = disp_cc_parent_map_4,
535 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
536 .clkr.hw.init = &(struct clk_init_data) {
537 .name = "disp_cc_mdss_esc0_clk_src",
538 .parent_data = disp_cc_parent_data_4,
539 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
540 .flags = CLK_SET_RATE_PARENT,
541 .ops = &clk_rcg2_ops,
542 },
543 };
544
545 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
546 .cmd_rcgr = 0x8184,
547 .mnd_width = 0,
548 .hid_width = 5,
549 .parent_map = disp_cc_parent_map_4,
550 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
551 .clkr.hw.init = &(struct clk_init_data) {
552 .name = "disp_cc_mdss_esc1_clk_src",
553 .parent_data = disp_cc_parent_data_4,
554 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
555 .flags = CLK_SET_RATE_PARENT,
556 .ops = &clk_rcg2_ops,
557 },
558 };
559
560 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
561 F(19200000, P_BI_TCXO, 1, 0, 0),
562 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
563 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
564 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
565 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
566 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
567 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
568 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
569 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
570 { }
571 };
572
573 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
574 .cmd_rcgr = 0x80ec,
575 .mnd_width = 0,
576 .hid_width = 5,
577 .parent_map = disp_cc_parent_map_5,
578 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
579 .clkr.hw.init = &(struct clk_init_data) {
580 .name = "disp_cc_mdss_mdp_clk_src",
581 .parent_data = disp_cc_parent_data_5,
582 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
583 .flags = CLK_SET_RATE_PARENT,
584 .ops = &clk_rcg2_shared_ops,
585 },
586 };
587
588 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
589 .cmd_rcgr = 0x80bc,
590 .mnd_width = 8,
591 .hid_width = 5,
592 .parent_map = disp_cc_parent_map_2,
593 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
594 .clkr.hw.init = &(struct clk_init_data) {
595 .name = "disp_cc_mdss_pclk0_clk_src",
596 .parent_data = disp_cc_parent_data_2,
597 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
598 .flags = CLK_SET_RATE_PARENT,
599 .ops = &clk_pixel_ops,
600 },
601 };
602
603 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
604 .cmd_rcgr = 0x80d4,
605 .mnd_width = 8,
606 .hid_width = 5,
607 .parent_map = disp_cc_parent_map_2,
608 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
609 .clkr.hw.init = &(struct clk_init_data) {
610 .name = "disp_cc_mdss_pclk1_clk_src",
611 .parent_data = disp_cc_parent_data_2,
612 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
613 .flags = CLK_SET_RATE_PARENT,
614 .ops = &clk_pixel_ops,
615 },
616 };
617
618 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
619 F(19200000, P_BI_TCXO, 1, 0, 0),
620 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
621 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
622 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
623 { }
624 };
625
626 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
627 .cmd_rcgr = 0x8104,
628 .mnd_width = 0,
629 .hid_width = 5,
630 .parent_map = disp_cc_parent_map_5,
631 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
632 .clkr.hw.init = &(struct clk_init_data) {
633 .name = "disp_cc_mdss_rot_clk_src",
634 .parent_data = disp_cc_parent_data_5,
635 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
636 .flags = CLK_SET_RATE_PARENT,
637 .ops = &clk_rcg2_shared_ops,
638 },
639 };
640
641 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
642 .cmd_rcgr = 0x811c,
643 .mnd_width = 0,
644 .hid_width = 5,
645 .parent_map = disp_cc_parent_map_1,
646 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
647 .clkr.hw.init = &(struct clk_init_data) {
648 .name = "disp_cc_mdss_vsync_clk_src",
649 .parent_data = disp_cc_parent_data_1,
650 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
651 .flags = CLK_SET_RATE_PARENT,
652 .ops = &clk_rcg2_ops,
653 },
654 };
655
656 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
657 F(32000, P_SLEEP_CLK, 1, 0, 0),
658 { }
659 };
660
661 static struct clk_rcg2 disp_cc_sleep_clk_src = {
662 .cmd_rcgr = 0xe060,
663 .mnd_width = 0,
664 .hid_width = 5,
665 .parent_map = disp_cc_parent_map_7,
666 .freq_tbl = ftbl_disp_cc_sleep_clk_src,
667 .clkr.hw.init = &(struct clk_init_data) {
668 .name = "disp_cc_sleep_clk_src",
669 .parent_data = disp_cc_parent_data_7,
670 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
671 .flags = CLK_SET_RATE_PARENT,
672 .ops = &clk_rcg2_ops,
673 },
674 };
675
676 static struct clk_rcg2 disp_cc_xo_clk_src = {
677 .cmd_rcgr = 0xe044,
678 .mnd_width = 0,
679 .hid_width = 5,
680 .parent_map = disp_cc_parent_map_1,
681 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
682 .clkr.hw.init = &(struct clk_init_data) {
683 .name = "disp_cc_xo_clk_src",
684 .parent_data = disp_cc_parent_data_1_ao,
685 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao),
686 .flags = CLK_SET_RATE_PARENT,
687 .ops = &clk_rcg2_ops,
688 },
689 };
690
691 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
692 .reg = 0x814c,
693 .shift = 0,
694 .width = 4,
695 .clkr.hw.init = &(struct clk_init_data) {
696 .name = "disp_cc_mdss_byte0_div_clk_src",
697 .parent_data = &(const struct clk_parent_data) {
698 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
699 },
700 .num_parents = 1,
701 .ops = &clk_regmap_div_ops,
702 },
703 };
704
705 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
706 .reg = 0x8168,
707 .shift = 0,
708 .width = 4,
709 .clkr.hw.init = &(struct clk_init_data) {
710 .name = "disp_cc_mdss_byte1_div_clk_src",
711 .parent_data = &(const struct clk_parent_data) {
712 .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
713 },
714 .num_parents = 1,
715 .ops = &clk_regmap_div_ops,
716 },
717 };
718
719 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
720 .reg = 0x81b4,
721 .shift = 0,
722 .width = 4,
723 .clkr.hw.init = &(struct clk_init_data) {
724 .name = "disp_cc_mdss_dptx0_link_div_clk_src",
725 .parent_data = &(const struct clk_parent_data) {
726 .hw = &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
727 },
728 .num_parents = 1,
729 .flags = CLK_SET_RATE_PARENT,
730 .ops = &clk_regmap_div_ro_ops,
731 },
732 };
733
734 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
735 .reg = 0x824c,
736 .shift = 0,
737 .width = 4,
738 .clkr.hw.init = &(struct clk_init_data) {
739 .name = "disp_cc_mdss_dptx1_link_div_clk_src",
740 .parent_data = &(const struct clk_parent_data) {
741 .hw = &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
742 },
743 .num_parents = 1,
744 .flags = CLK_SET_RATE_PARENT,
745 .ops = &clk_regmap_div_ro_ops,
746 },
747 };
748
749 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
750 .reg = 0x8284,
751 .shift = 0,
752 .width = 4,
753 .clkr.hw.init = &(struct clk_init_data) {
754 .name = "disp_cc_mdss_dptx2_link_div_clk_src",
755 .parent_data = &(const struct clk_parent_data) {
756 .hw = &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
757 },
758 .num_parents = 1,
759 .flags = CLK_SET_RATE_PARENT,
760 .ops = &clk_regmap_div_ro_ops,
761 },
762 };
763
764 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
765 .reg = 0x8304,
766 .shift = 0,
767 .width = 4,
768 .clkr.hw.init = &(struct clk_init_data) {
769 .name = "disp_cc_mdss_dptx3_link_div_clk_src",
770 .parent_data = &(const struct clk_parent_data) {
771 .hw = &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
772 },
773 .num_parents = 1,
774 .flags = CLK_SET_RATE_PARENT,
775 .ops = &clk_regmap_div_ro_ops,
776 },
777 };
778
779 static struct clk_branch disp_cc_mdss_ahb1_clk = {
780 .halt_reg = 0xa020,
781 .halt_check = BRANCH_HALT,
782 .clkr = {
783 .enable_reg = 0xa020,
784 .enable_mask = BIT(0),
785 .hw.init = &(struct clk_init_data) {
786 .name = "disp_cc_mdss_ahb1_clk",
787 .parent_data = &(const struct clk_parent_data) {
788 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
789 },
790 .num_parents = 1,
791 .flags = CLK_SET_RATE_PARENT,
792 .ops = &clk_branch2_ops,
793 },
794 },
795 };
796
797 static struct clk_branch disp_cc_mdss_ahb_clk = {
798 .halt_reg = 0x80a4,
799 .halt_check = BRANCH_HALT,
800 .clkr = {
801 .enable_reg = 0x80a4,
802 .enable_mask = BIT(0),
803 .hw.init = &(struct clk_init_data) {
804 .name = "disp_cc_mdss_ahb_clk",
805 .parent_data = &(const struct clk_parent_data) {
806 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
807 },
808 .num_parents = 1,
809 .flags = CLK_SET_RATE_PARENT,
810 .ops = &clk_branch2_ops,
811 },
812 },
813 };
814
815 static struct clk_branch disp_cc_mdss_byte0_clk = {
816 .halt_reg = 0x8028,
817 .halt_check = BRANCH_HALT,
818 .clkr = {
819 .enable_reg = 0x8028,
820 .enable_mask = BIT(0),
821 .hw.init = &(struct clk_init_data) {
822 .name = "disp_cc_mdss_byte0_clk",
823 .parent_data = &(const struct clk_parent_data) {
824 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
825 },
826 .num_parents = 1,
827 .flags = CLK_SET_RATE_PARENT,
828 .ops = &clk_branch2_ops,
829 },
830 },
831 };
832
833 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
834 .halt_reg = 0x802c,
835 .halt_check = BRANCH_HALT,
836 .clkr = {
837 .enable_reg = 0x802c,
838 .enable_mask = BIT(0),
839 .hw.init = &(struct clk_init_data) {
840 .name = "disp_cc_mdss_byte0_intf_clk",
841 .parent_data = &(const struct clk_parent_data) {
842 .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
843 },
844 .num_parents = 1,
845 .flags = CLK_SET_RATE_PARENT,
846 .ops = &clk_branch2_ops,
847 },
848 },
849 };
850
851 static struct clk_branch disp_cc_mdss_byte1_clk = {
852 .halt_reg = 0x8030,
853 .halt_check = BRANCH_HALT,
854 .clkr = {
855 .enable_reg = 0x8030,
856 .enable_mask = BIT(0),
857 .hw.init = &(struct clk_init_data) {
858 .name = "disp_cc_mdss_byte1_clk",
859 .parent_data = &(const struct clk_parent_data) {
860 .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw,
861 },
862 .num_parents = 1,
863 .flags = CLK_SET_RATE_PARENT,
864 .ops = &clk_branch2_ops,
865 },
866 },
867 };
868
869 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
870 .halt_reg = 0x8034,
871 .halt_check = BRANCH_HALT,
872 .clkr = {
873 .enable_reg = 0x8034,
874 .enable_mask = BIT(0),
875 .hw.init = &(struct clk_init_data) {
876 .name = "disp_cc_mdss_byte1_intf_clk",
877 .parent_data = &(const struct clk_parent_data) {
878 .hw = &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
879 },
880 .num_parents = 1,
881 .flags = CLK_SET_RATE_PARENT,
882 .ops = &clk_branch2_ops,
883 },
884 },
885 };
886
887 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
888 .halt_reg = 0x8058,
889 .halt_check = BRANCH_HALT,
890 .clkr = {
891 .enable_reg = 0x8058,
892 .enable_mask = BIT(0),
893 .hw.init = &(struct clk_init_data) {
894 .name = "disp_cc_mdss_dptx0_aux_clk",
895 .parent_data = &(const struct clk_parent_data) {
896 .hw = &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
897 },
898 .num_parents = 1,
899 .flags = CLK_SET_RATE_PARENT,
900 .ops = &clk_branch2_ops,
901 },
902 },
903 };
904
905 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
906 .halt_reg = 0x804c,
907 .halt_check = BRANCH_HALT,
908 .clkr = {
909 .enable_reg = 0x804c,
910 .enable_mask = BIT(0),
911 .hw.init = &(struct clk_init_data) {
912 .name = "disp_cc_mdss_dptx0_crypto_clk",
913 .parent_data = &(const struct clk_parent_data) {
914 .hw = &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
915 },
916 .num_parents = 1,
917 .flags = CLK_SET_RATE_PARENT,
918 .ops = &clk_branch2_ops,
919 },
920 },
921 };
922
923 static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
924 .halt_reg = 0x8040,
925 .halt_check = BRANCH_HALT,
926 .clkr = {
927 .enable_reg = 0x8040,
928 .enable_mask = BIT(0),
929 .hw.init = &(struct clk_init_data) {
930 .name = "disp_cc_mdss_dptx0_link_clk",
931 .parent_data = &(const struct clk_parent_data) {
932 .hw = &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
933 },
934 .num_parents = 1,
935 .flags = CLK_SET_RATE_PARENT,
936 .ops = &clk_branch2_ops,
937 },
938 },
939 };
940
941 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
942 .halt_reg = 0x8048,
943 .halt_check = BRANCH_HALT,
944 .clkr = {
945 .enable_reg = 0x8048,
946 .enable_mask = BIT(0),
947 .hw.init = &(struct clk_init_data) {
948 .name = "disp_cc_mdss_dptx0_link_intf_clk",
949 .parent_data = &(const struct clk_parent_data) {
950 .hw = &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
951 },
952 .num_parents = 1,
953 .flags = CLK_SET_RATE_PARENT,
954 .ops = &clk_branch2_ops,
955 },
956 },
957 };
958
959 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
960 .halt_reg = 0x8050,
961 .halt_check = BRANCH_HALT,
962 .clkr = {
963 .enable_reg = 0x8050,
964 .enable_mask = BIT(0),
965 .hw.init = &(struct clk_init_data) {
966 .name = "disp_cc_mdss_dptx0_pixel0_clk",
967 .parent_data = &(const struct clk_parent_data) {
968 .hw = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
969 },
970 .num_parents = 1,
971 .flags = CLK_SET_RATE_PARENT,
972 .ops = &clk_branch2_ops,
973 },
974 },
975 };
976
977 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
978 .halt_reg = 0x8054,
979 .halt_check = BRANCH_HALT,
980 .clkr = {
981 .enable_reg = 0x8054,
982 .enable_mask = BIT(0),
983 .hw.init = &(struct clk_init_data) {
984 .name = "disp_cc_mdss_dptx0_pixel1_clk",
985 .parent_data = &(const struct clk_parent_data) {
986 .hw = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
987 },
988 .num_parents = 1,
989 .flags = CLK_SET_RATE_PARENT,
990 .ops = &clk_branch2_ops,
991 },
992 },
993 };
994
995 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
996 .halt_reg = 0x8044,
997 .halt_check = BRANCH_HALT,
998 .clkr = {
999 .enable_reg = 0x8044,
1000 .enable_mask = BIT(0),
1001 .hw.init = &(struct clk_init_data) {
1002 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1003 .parent_data = &(const struct clk_parent_data) {
1004 .hw = &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1005 },
1006 .num_parents = 1,
1007 .flags = CLK_SET_RATE_PARENT,
1008 .ops = &clk_branch2_ops,
1009 },
1010 },
1011 };
1012
1013 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1014 .halt_reg = 0x8074,
1015 .halt_check = BRANCH_HALT,
1016 .clkr = {
1017 .enable_reg = 0x8074,
1018 .enable_mask = BIT(0),
1019 .hw.init = &(struct clk_init_data) {
1020 .name = "disp_cc_mdss_dptx1_aux_clk",
1021 .parent_data = &(const struct clk_parent_data) {
1022 .hw = &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1023 },
1024 .num_parents = 1,
1025 .flags = CLK_SET_RATE_PARENT,
1026 .ops = &clk_branch2_ops,
1027 },
1028 },
1029 };
1030
1031 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1032 .halt_reg = 0x8070,
1033 .halt_check = BRANCH_HALT,
1034 .clkr = {
1035 .enable_reg = 0x8070,
1036 .enable_mask = BIT(0),
1037 .hw.init = &(struct clk_init_data) {
1038 .name = "disp_cc_mdss_dptx1_crypto_clk",
1039 .parent_data = &(const struct clk_parent_data) {
1040 .hw = &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1041 },
1042 .num_parents = 1,
1043 .flags = CLK_SET_RATE_PARENT,
1044 .ops = &clk_branch2_ops,
1045 },
1046 },
1047 };
1048
1049 static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1050 .halt_reg = 0x8064,
1051 .halt_check = BRANCH_HALT,
1052 .clkr = {
1053 .enable_reg = 0x8064,
1054 .enable_mask = BIT(0),
1055 .hw.init = &(struct clk_init_data) {
1056 .name = "disp_cc_mdss_dptx1_link_clk",
1057 .parent_data = &(const struct clk_parent_data) {
1058 .hw = &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1059 },
1060 .num_parents = 1,
1061 .flags = CLK_SET_RATE_PARENT,
1062 .ops = &clk_branch2_ops,
1063 },
1064 },
1065 };
1066
1067 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1068 .halt_reg = 0x806c,
1069 .halt_check = BRANCH_HALT,
1070 .clkr = {
1071 .enable_reg = 0x806c,
1072 .enable_mask = BIT(0),
1073 .hw.init = &(struct clk_init_data) {
1074 .name = "disp_cc_mdss_dptx1_link_intf_clk",
1075 .parent_data = &(const struct clk_parent_data) {
1076 .hw = &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1077 },
1078 .num_parents = 1,
1079 .flags = CLK_SET_RATE_PARENT,
1080 .ops = &clk_branch2_ops,
1081 },
1082 },
1083 };
1084
1085 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1086 .halt_reg = 0x805c,
1087 .halt_check = BRANCH_HALT,
1088 .clkr = {
1089 .enable_reg = 0x805c,
1090 .enable_mask = BIT(0),
1091 .hw.init = &(struct clk_init_data) {
1092 .name = "disp_cc_mdss_dptx1_pixel0_clk",
1093 .parent_data = &(const struct clk_parent_data) {
1094 .hw = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1095 },
1096 .num_parents = 1,
1097 .flags = CLK_SET_RATE_PARENT,
1098 .ops = &clk_branch2_ops,
1099 },
1100 },
1101 };
1102
1103 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1104 .halt_reg = 0x8060,
1105 .halt_check = BRANCH_HALT,
1106 .clkr = {
1107 .enable_reg = 0x8060,
1108 .enable_mask = BIT(0),
1109 .hw.init = &(struct clk_init_data) {
1110 .name = "disp_cc_mdss_dptx1_pixel1_clk",
1111 .parent_data = &(const struct clk_parent_data) {
1112 .hw = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1113 },
1114 .num_parents = 1,
1115 .flags = CLK_SET_RATE_PARENT,
1116 .ops = &clk_branch2_ops,
1117 },
1118 },
1119 };
1120
1121 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1122 .halt_reg = 0x8068,
1123 .halt_check = BRANCH_HALT,
1124 .clkr = {
1125 .enable_reg = 0x8068,
1126 .enable_mask = BIT(0),
1127 .hw.init = &(struct clk_init_data) {
1128 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1129 .parent_data = &(const struct clk_parent_data) {
1130 .hw = &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1131 },
1132 .num_parents = 1,
1133 .flags = CLK_SET_RATE_PARENT,
1134 .ops = &clk_branch2_ops,
1135 },
1136 },
1137 };
1138
1139 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1140 .halt_reg = 0x808c,
1141 .halt_check = BRANCH_HALT,
1142 .clkr = {
1143 .enable_reg = 0x808c,
1144 .enable_mask = BIT(0),
1145 .hw.init = &(struct clk_init_data) {
1146 .name = "disp_cc_mdss_dptx2_aux_clk",
1147 .parent_data = &(const struct clk_parent_data) {
1148 .hw = &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1149 },
1150 .num_parents = 1,
1151 .flags = CLK_SET_RATE_PARENT,
1152 .ops = &clk_branch2_ops,
1153 },
1154 },
1155 };
1156
1157 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1158 .halt_reg = 0x8088,
1159 .halt_check = BRANCH_HALT,
1160 .clkr = {
1161 .enable_reg = 0x8088,
1162 .enable_mask = BIT(0),
1163 .hw.init = &(struct clk_init_data) {
1164 .name = "disp_cc_mdss_dptx2_crypto_clk",
1165 .parent_data = &(const struct clk_parent_data) {
1166 .hw = &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1167 },
1168 .num_parents = 1,
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1171 },
1172 },
1173 };
1174
1175 static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1176 .halt_reg = 0x8080,
1177 .halt_check = BRANCH_HALT,
1178 .clkr = {
1179 .enable_reg = 0x8080,
1180 .enable_mask = BIT(0),
1181 .hw.init = &(struct clk_init_data) {
1182 .name = "disp_cc_mdss_dptx2_link_clk",
1183 .parent_data = &(const struct clk_parent_data) {
1184 .hw = &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1185 },
1186 .num_parents = 1,
1187 .flags = CLK_SET_RATE_PARENT,
1188 .ops = &clk_branch2_ops,
1189 },
1190 },
1191 };
1192
1193 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1194 .halt_reg = 0x8084,
1195 .halt_check = BRANCH_HALT,
1196 .clkr = {
1197 .enable_reg = 0x8084,
1198 .enable_mask = BIT(0),
1199 .hw.init = &(struct clk_init_data) {
1200 .name = "disp_cc_mdss_dptx2_link_intf_clk",
1201 .parent_data = &(const struct clk_parent_data) {
1202 .hw = &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1203 },
1204 .num_parents = 1,
1205 .flags = CLK_SET_RATE_PARENT,
1206 .ops = &clk_branch2_ops,
1207 },
1208 },
1209 };
1210
1211 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1212 .halt_reg = 0x8078,
1213 .halt_check = BRANCH_HALT,
1214 .clkr = {
1215 .enable_reg = 0x8078,
1216 .enable_mask = BIT(0),
1217 .hw.init = &(struct clk_init_data) {
1218 .name = "disp_cc_mdss_dptx2_pixel0_clk",
1219 .parent_data = &(const struct clk_parent_data) {
1220 .hw = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1221 },
1222 .num_parents = 1,
1223 .flags = CLK_SET_RATE_PARENT,
1224 .ops = &clk_branch2_ops,
1225 },
1226 },
1227 };
1228
1229 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1230 .halt_reg = 0x807c,
1231 .halt_check = BRANCH_HALT,
1232 .clkr = {
1233 .enable_reg = 0x807c,
1234 .enable_mask = BIT(0),
1235 .hw.init = &(struct clk_init_data) {
1236 .name = "disp_cc_mdss_dptx2_pixel1_clk",
1237 .parent_data = &(const struct clk_parent_data) {
1238 .hw = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1239 },
1240 .num_parents = 1,
1241 .flags = CLK_SET_RATE_PARENT,
1242 .ops = &clk_branch2_ops,
1243 },
1244 },
1245 };
1246
1247 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1248 .halt_reg = 0x809c,
1249 .halt_check = BRANCH_HALT,
1250 .clkr = {
1251 .enable_reg = 0x809c,
1252 .enable_mask = BIT(0),
1253 .hw.init = &(struct clk_init_data) {
1254 .name = "disp_cc_mdss_dptx3_aux_clk",
1255 .parent_data = &(const struct clk_parent_data) {
1256 .hw = &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1257 },
1258 .num_parents = 1,
1259 .flags = CLK_SET_RATE_PARENT,
1260 .ops = &clk_branch2_ops,
1261 },
1262 },
1263 };
1264
1265 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1266 .halt_reg = 0x80a0,
1267 .halt_check = BRANCH_HALT,
1268 .clkr = {
1269 .enable_reg = 0x80a0,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data) {
1272 .name = "disp_cc_mdss_dptx3_crypto_clk",
1273 .parent_data = &(const struct clk_parent_data) {
1274 .hw = &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1275 },
1276 .num_parents = 1,
1277 .flags = CLK_SET_RATE_PARENT,
1278 .ops = &clk_branch2_ops,
1279 },
1280 },
1281 };
1282
1283 static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1284 .halt_reg = 0x8094,
1285 .halt_check = BRANCH_HALT,
1286 .clkr = {
1287 .enable_reg = 0x8094,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data) {
1290 .name = "disp_cc_mdss_dptx3_link_clk",
1291 .parent_data = &(const struct clk_parent_data) {
1292 .hw = &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1293 },
1294 .num_parents = 1,
1295 .flags = CLK_SET_RATE_PARENT,
1296 .ops = &clk_branch2_ops,
1297 },
1298 },
1299 };
1300
1301 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1302 .halt_reg = 0x8098,
1303 .halt_check = BRANCH_HALT,
1304 .clkr = {
1305 .enable_reg = 0x8098,
1306 .enable_mask = BIT(0),
1307 .hw.init = &(struct clk_init_data) {
1308 .name = "disp_cc_mdss_dptx3_link_intf_clk",
1309 .parent_data = &(const struct clk_parent_data) {
1310 .hw = &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1311 },
1312 .num_parents = 1,
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_branch2_ops,
1315 },
1316 },
1317 };
1318
1319 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1320 .halt_reg = 0x8090,
1321 .halt_check = BRANCH_HALT,
1322 .clkr = {
1323 .enable_reg = 0x8090,
1324 .enable_mask = BIT(0),
1325 .hw.init = &(struct clk_init_data) {
1326 .name = "disp_cc_mdss_dptx3_pixel0_clk",
1327 .parent_data = &(const struct clk_parent_data) {
1328 .hw = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1329 },
1330 .num_parents = 1,
1331 .flags = CLK_SET_RATE_PARENT,
1332 .ops = &clk_branch2_ops,
1333 },
1334 },
1335 };
1336
1337 static struct clk_branch disp_cc_mdss_esc0_clk = {
1338 .halt_reg = 0x8038,
1339 .halt_check = BRANCH_HALT,
1340 .clkr = {
1341 .enable_reg = 0x8038,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data) {
1344 .name = "disp_cc_mdss_esc0_clk",
1345 .parent_data = &(const struct clk_parent_data) {
1346 .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
1347 },
1348 .num_parents = 1,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1351 },
1352 },
1353 };
1354
1355 static struct clk_branch disp_cc_mdss_esc1_clk = {
1356 .halt_reg = 0x803c,
1357 .halt_check = BRANCH_HALT,
1358 .clkr = {
1359 .enable_reg = 0x803c,
1360 .enable_mask = BIT(0),
1361 .hw.init = &(struct clk_init_data) {
1362 .name = "disp_cc_mdss_esc1_clk",
1363 .parent_data = &(const struct clk_parent_data) {
1364 .hw = &disp_cc_mdss_esc1_clk_src.clkr.hw,
1365 },
1366 .num_parents = 1,
1367 .flags = CLK_SET_RATE_PARENT,
1368 .ops = &clk_branch2_ops,
1369 },
1370 },
1371 };
1372
1373 static struct clk_branch disp_cc_mdss_mdp1_clk = {
1374 .halt_reg = 0xa004,
1375 .halt_check = BRANCH_HALT,
1376 .clkr = {
1377 .enable_reg = 0xa004,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data) {
1380 .name = "disp_cc_mdss_mdp1_clk",
1381 .parent_data = &(const struct clk_parent_data) {
1382 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
1383 },
1384 .num_parents = 1,
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1387 },
1388 },
1389 };
1390
1391 static struct clk_branch disp_cc_mdss_mdp_clk = {
1392 .halt_reg = 0x800c,
1393 .halt_check = BRANCH_HALT,
1394 .clkr = {
1395 .enable_reg = 0x800c,
1396 .enable_mask = BIT(0),
1397 .hw.init = &(struct clk_init_data) {
1398 .name = "disp_cc_mdss_mdp_clk",
1399 .parent_data = &(const struct clk_parent_data) {
1400 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
1401 },
1402 .num_parents = 1,
1403 .flags = CLK_SET_RATE_PARENT,
1404 .ops = &clk_branch2_ops,
1405 },
1406 },
1407 };
1408
1409 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1410 .halt_reg = 0xa014,
1411 .halt_check = BRANCH_HALT,
1412 .clkr = {
1413 .enable_reg = 0xa014,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data) {
1416 .name = "disp_cc_mdss_mdp_lut1_clk",
1417 .parent_data = &(const struct clk_parent_data) {
1418 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
1419 },
1420 .num_parents = 1,
1421 .flags = CLK_SET_RATE_PARENT,
1422 .ops = &clk_branch2_ops,
1423 },
1424 },
1425 };
1426
1427 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1428 .halt_reg = 0x801c,
1429 .halt_check = BRANCH_HALT_VOTED,
1430 .clkr = {
1431 .enable_reg = 0x801c,
1432 .enable_mask = BIT(0),
1433 .hw.init = &(struct clk_init_data) {
1434 .name = "disp_cc_mdss_mdp_lut_clk",
1435 .parent_data = &(const struct clk_parent_data) {
1436 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
1437 },
1438 .num_parents = 1,
1439 .flags = CLK_SET_RATE_PARENT,
1440 .ops = &clk_branch2_ops,
1441 },
1442 },
1443 };
1444
1445 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1446 .halt_reg = 0xc004,
1447 .halt_check = BRANCH_HALT_VOTED,
1448 .clkr = {
1449 .enable_reg = 0xc004,
1450 .enable_mask = BIT(0),
1451 .hw.init = &(struct clk_init_data) {
1452 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1453 .parent_data = &(const struct clk_parent_data) {
1454 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
1455 },
1456 .num_parents = 1,
1457 .flags = CLK_SET_RATE_PARENT,
1458 .ops = &clk_branch2_ops,
1459 },
1460 },
1461 };
1462
1463 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1464 .halt_reg = 0x8004,
1465 .halt_check = BRANCH_HALT,
1466 .clkr = {
1467 .enable_reg = 0x8004,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data) {
1470 .name = "disp_cc_mdss_pclk0_clk",
1471 .parent_data = &(const struct clk_parent_data) {
1472 .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1473 },
1474 .num_parents = 1,
1475 .flags = CLK_SET_RATE_PARENT,
1476 .ops = &clk_branch2_ops,
1477 },
1478 },
1479 };
1480
1481 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1482 .halt_reg = 0x8008,
1483 .halt_check = BRANCH_HALT,
1484 .clkr = {
1485 .enable_reg = 0x8008,
1486 .enable_mask = BIT(0),
1487 .hw.init = &(struct clk_init_data) {
1488 .name = "disp_cc_mdss_pclk1_clk",
1489 .parent_data = &(const struct clk_parent_data) {
1490 .hw = &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1491 },
1492 .num_parents = 1,
1493 .flags = CLK_SET_RATE_PARENT,
1494 .ops = &clk_branch2_ops,
1495 },
1496 },
1497 };
1498
1499 static struct clk_branch disp_cc_mdss_rot1_clk = {
1500 .halt_reg = 0xa00c,
1501 .halt_check = BRANCH_HALT,
1502 .clkr = {
1503 .enable_reg = 0xa00c,
1504 .enable_mask = BIT(0),
1505 .hw.init = &(struct clk_init_data) {
1506 .name = "disp_cc_mdss_rot1_clk",
1507 .parent_data = &(const struct clk_parent_data) {
1508 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
1509 },
1510 .num_parents = 1,
1511 .flags = CLK_SET_RATE_PARENT,
1512 .ops = &clk_branch2_ops,
1513 },
1514 },
1515 };
1516
1517 static struct clk_branch disp_cc_mdss_rot_clk = {
1518 .halt_reg = 0x8014,
1519 .halt_check = BRANCH_HALT,
1520 .clkr = {
1521 .enable_reg = 0x8014,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data) {
1524 .name = "disp_cc_mdss_rot_clk",
1525 .parent_data = &(const struct clk_parent_data) {
1526 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
1527 },
1528 .num_parents = 1,
1529 .flags = CLK_SET_RATE_PARENT,
1530 .ops = &clk_branch2_ops,
1531 },
1532 },
1533 };
1534
1535 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1536 .halt_reg = 0xc00c,
1537 .halt_check = BRANCH_HALT,
1538 .clkr = {
1539 .enable_reg = 0xc00c,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data) {
1542 .name = "disp_cc_mdss_rscc_ahb_clk",
1543 .parent_data = &(const struct clk_parent_data) {
1544 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
1545 },
1546 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT,
1548 .ops = &clk_branch2_ops,
1549 },
1550 },
1551 };
1552
1553 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1554 .halt_reg = 0xc008,
1555 .halt_check = BRANCH_HALT,
1556 .clkr = {
1557 .enable_reg = 0xc008,
1558 .enable_mask = BIT(0),
1559 .hw.init = &(struct clk_init_data) {
1560 .name = "disp_cc_mdss_rscc_vsync_clk",
1561 .parent_data = &(const struct clk_parent_data) {
1562 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
1563 },
1564 .num_parents = 1,
1565 .flags = CLK_SET_RATE_PARENT,
1566 .ops = &clk_branch2_ops,
1567 },
1568 },
1569 };
1570
1571 static struct clk_branch disp_cc_mdss_vsync1_clk = {
1572 .halt_reg = 0xa01c,
1573 .halt_check = BRANCH_HALT,
1574 .clkr = {
1575 .enable_reg = 0xa01c,
1576 .enable_mask = BIT(0),
1577 .hw.init = &(struct clk_init_data) {
1578 .name = "disp_cc_mdss_vsync1_clk",
1579 .parent_data = &(const struct clk_parent_data) {
1580 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
1581 },
1582 .num_parents = 1,
1583 .flags = CLK_SET_RATE_PARENT,
1584 .ops = &clk_branch2_ops,
1585 },
1586 },
1587 };
1588
1589 static struct clk_branch disp_cc_mdss_vsync_clk = {
1590 .halt_reg = 0x8024,
1591 .halt_check = BRANCH_HALT,
1592 .clkr = {
1593 .enable_reg = 0x8024,
1594 .enable_mask = BIT(0),
1595 .hw.init = &(struct clk_init_data) {
1596 .name = "disp_cc_mdss_vsync_clk",
1597 .parent_data = &(const struct clk_parent_data) {
1598 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
1599 },
1600 .num_parents = 1,
1601 .flags = CLK_SET_RATE_PARENT,
1602 .ops = &clk_branch2_ops,
1603 },
1604 },
1605 };
1606
1607 static struct clk_branch disp_cc_sleep_clk = {
1608 .halt_reg = 0xe078,
1609 .halt_check = BRANCH_HALT,
1610 .clkr = {
1611 .enable_reg = 0xe078,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data) {
1614 .name = "disp_cc_sleep_clk",
1615 .parent_data = &(const struct clk_parent_data) {
1616 .hw = &disp_cc_sleep_clk_src.clkr.hw,
1617 },
1618 .num_parents = 1,
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1621 },
1622 },
1623 };
1624
1625 static struct gdsc mdss_gdsc = {
1626 .gdscr = 0x9000,
1627 .pd = {
1628 .name = "mdss_gdsc",
1629 },
1630 .pwrsts = PWRSTS_OFF_ON,
1631 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1632 };
1633
1634 static struct gdsc mdss_int2_gdsc = {
1635 .gdscr = 0xb000,
1636 .pd = {
1637 .name = "mdss_int2_gdsc",
1638 },
1639 .pwrsts = PWRSTS_OFF_ON,
1640 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1641 };
1642
1643 static struct clk_regmap *disp_cc_sm8450_clocks[] = {
1644 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1645 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1646 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1647 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1648 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1649 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1650 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1651 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1652 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1653 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1654 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1655 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1656 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1657 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1658 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1659 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1660 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1661 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1662 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1663 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1664 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1665 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1666 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1667 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1668 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1669 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1670 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1671 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1672 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1673 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1674 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1675 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1676 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1677 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1678 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1679 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1680 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1681 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1682 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1683 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1684 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1685 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1686 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1687 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1688 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1689 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1690 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1691 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1692 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1693 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1694 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1695 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1696 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1697 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1698 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1699 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1700 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1701 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1702 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1703 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1704 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1705 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1706 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1707 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1708 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1709 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1710 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1711 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1712 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1713 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1714 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1715 [DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr,
1716 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1717 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1718 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1719 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1720 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1721 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1722 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1723 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1724 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1725 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
1726 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1727 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1728 };
1729
1730 static const struct qcom_reset_map disp_cc_sm8450_resets[] = {
1731 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1732 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1733 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1734 };
1735
1736 static struct gdsc *disp_cc_sm8450_gdscs[] = {
1737 [MDSS_GDSC] = &mdss_gdsc,
1738 [MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1739 };
1740
1741 static const struct regmap_config disp_cc_sm8450_regmap_config = {
1742 .reg_bits = 32,
1743 .reg_stride = 4,
1744 .val_bits = 32,
1745 .max_register = 0x11008,
1746 .fast_io = true,
1747 };
1748
1749 static struct qcom_cc_desc disp_cc_sm8450_desc = {
1750 .config = &disp_cc_sm8450_regmap_config,
1751 .clks = disp_cc_sm8450_clocks,
1752 .num_clks = ARRAY_SIZE(disp_cc_sm8450_clocks),
1753 .resets = disp_cc_sm8450_resets,
1754 .num_resets = ARRAY_SIZE(disp_cc_sm8450_resets),
1755 .gdscs = disp_cc_sm8450_gdscs,
1756 .num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs),
1757 };
1758
1759 static const struct of_device_id disp_cc_sm8450_match_table[] = {
1760 { .compatible = "qcom,sm8450-dispcc" },
1761 { }
1762 };
1763 MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);
1764
disp_cc_sm8450_pm_runtime_disable(void * data)1765 static void disp_cc_sm8450_pm_runtime_disable(void *data)
1766 {
1767 pm_runtime_disable(data);
1768 }
1769
disp_cc_sm8450_probe(struct platform_device * pdev)1770 static int disp_cc_sm8450_probe(struct platform_device *pdev)
1771 {
1772 struct regmap *regmap;
1773 int ret;
1774
1775 pm_runtime_enable(&pdev->dev);
1776
1777 ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8450_pm_runtime_disable, &pdev->dev);
1778 if (ret)
1779 return ret;
1780
1781 ret = pm_runtime_resume_and_get(&pdev->dev);
1782 if (ret)
1783 return ret;
1784
1785 regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc);
1786 if (IS_ERR(regmap))
1787 return PTR_ERR(regmap);
1788
1789 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1790 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1791
1792 /* Enable clock gating for MDP clocks */
1793 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1794
1795 /*
1796 * Keep clocks always enabled:
1797 * disp_cc_xo_clk
1798 */
1799 regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0));
1800
1801 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap);
1802
1803 pm_runtime_put(&pdev->dev);
1804
1805 return ret;
1806 }
1807
1808 static struct platform_driver disp_cc_sm8450_driver = {
1809 .probe = disp_cc_sm8450_probe,
1810 .driver = {
1811 .name = "disp_cc-sm8450",
1812 .of_match_table = disp_cc_sm8450_match_table,
1813 },
1814 };
1815
disp_cc_sm8450_init(void)1816 static int __init disp_cc_sm8450_init(void)
1817 {
1818 return platform_driver_register(&disp_cc_sm8450_driver);
1819 }
1820 subsys_initcall(disp_cc_sm8450_init);
1821
disp_cc_sm8450_exit(void)1822 static void __exit disp_cc_sm8450_exit(void)
1823 {
1824 platform_driver_unregister(&disp_cc_sm8450_driver);
1825 }
1826 module_exit(disp_cc_sm8450_exit);
1827
1828 MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
1829 MODULE_LICENSE("GPL");
1830