1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * pxa910 clock framework source file
4 *
5 * Copyright (C) 2012 Marvell
6 * Chao Xie <xiechao.mail@gmail.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk/mmp.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17
18 #include "clk.h"
19
20 #define APBC_RTC 0x28
21 #define APBC_TWSI0 0x2c
22 #define APBC_KPC 0x18
23 #define APBC_UART0 0x0
24 #define APBC_UART1 0x4
25 #define APBC_GPIO 0x8
26 #define APBC_PWM0 0xc
27 #define APBC_PWM1 0x10
28 #define APBC_PWM2 0x14
29 #define APBC_PWM3 0x18
30 #define APBC_SSP0 0x1c
31 #define APBC_SSP1 0x20
32 #define APBC_SSP2 0x4c
33 #define APBCP_TWSI1 0x28
34 #define APBCP_UART2 0x1c
35 #define APMU_SDH0 0x54
36 #define APMU_SDH1 0x58
37 #define APMU_USB 0x5c
38 #define APMU_DISP0 0x4c
39 #define APMU_CCIC0 0x50
40 #define APMU_DFC 0x60
41 #define MPMU_UART_PLL 0x14
42
43 static DEFINE_SPINLOCK(clk_lock);
44
45 static struct mmp_clk_factor_masks uart_factor_masks = {
46 .factor = 2,
47 .num_mask = 0x1fff,
48 .den_mask = 0x1fff,
49 .num_shift = 16,
50 .den_shift = 0,
51 };
52
53 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
54 {.num = 8125, .den = 1536}, /*14.745MHZ */
55 };
56
57 static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
58 static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
59 static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
60 static const char *disp_parent[] = {"pll1_2", "pll1_12"};
61 static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
62 static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
63
pxa910_clk_init(phys_addr_t mpmu_phys,phys_addr_t apmu_phys,phys_addr_t apbc_phys,phys_addr_t apbcp_phys)64 void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
65 phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
66 {
67 struct clk *clk;
68 struct clk *uart_pll;
69 void __iomem *mpmu_base;
70 void __iomem *apmu_base;
71 void __iomem *apbcp_base;
72 void __iomem *apbc_base;
73
74 mpmu_base = ioremap(mpmu_phys, SZ_4K);
75 if (!mpmu_base) {
76 pr_err("error to ioremap MPMU base\n");
77 return;
78 }
79
80 apmu_base = ioremap(apmu_phys, SZ_4K);
81 if (!apmu_base) {
82 pr_err("error to ioremap APMU base\n");
83 return;
84 }
85
86 apbcp_base = ioremap(apbcp_phys, SZ_4K);
87 if (!apbcp_base) {
88 pr_err("error to ioremap APBC extension base\n");
89 return;
90 }
91
92 apbc_base = ioremap(apbc_phys, SZ_4K);
93 if (!apbc_base) {
94 pr_err("error to ioremap APBC base\n");
95 return;
96 }
97
98 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
99 clk_register_clkdev(clk, "clk32", NULL);
100
101 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
102 clk_register_clkdev(clk, "vctcxo", NULL);
103
104 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
105 clk_register_clkdev(clk, "pll1", NULL);
106
107 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
108 CLK_SET_RATE_PARENT, 1, 2);
109 clk_register_clkdev(clk, "pll1_2", NULL);
110
111 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
112 CLK_SET_RATE_PARENT, 1, 2);
113 clk_register_clkdev(clk, "pll1_4", NULL);
114
115 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
116 CLK_SET_RATE_PARENT, 1, 2);
117 clk_register_clkdev(clk, "pll1_8", NULL);
118
119 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
120 CLK_SET_RATE_PARENT, 1, 2);
121 clk_register_clkdev(clk, "pll1_16", NULL);
122
123 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
124 CLK_SET_RATE_PARENT, 1, 3);
125 clk_register_clkdev(clk, "pll1_6", NULL);
126
127 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
128 CLK_SET_RATE_PARENT, 1, 2);
129 clk_register_clkdev(clk, "pll1_12", NULL);
130
131 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
132 CLK_SET_RATE_PARENT, 1, 2);
133 clk_register_clkdev(clk, "pll1_24", NULL);
134
135 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
136 CLK_SET_RATE_PARENT, 1, 2);
137 clk_register_clkdev(clk, "pll1_48", NULL);
138
139 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
140 CLK_SET_RATE_PARENT, 1, 2);
141 clk_register_clkdev(clk, "pll1_96", NULL);
142
143 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
144 CLK_SET_RATE_PARENT, 1, 13);
145 clk_register_clkdev(clk, "pll1_13", NULL);
146
147 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
148 CLK_SET_RATE_PARENT, 2, 3);
149 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
150
151 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
152 CLK_SET_RATE_PARENT, 2, 3);
153 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
154
155 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
156 CLK_SET_RATE_PARENT, 3, 16);
157 clk_register_clkdev(clk, "pll1_3_16", NULL);
158
159 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
160 mpmu_base + MPMU_UART_PLL,
161 &uart_factor_masks, uart_factor_tbl,
162 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
163 clk_set_rate(uart_pll, 14745600);
164 clk_register_clkdev(uart_pll, "uart_pll", NULL);
165
166 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
167 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
168 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
169
170 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
171 apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
172 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
173
174 clk = mmp_clk_register_apbc("gpio", "vctcxo",
175 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
176 clk_register_clkdev(clk, NULL, "mmp-gpio");
177
178 clk = mmp_clk_register_apbc("kpc", "clk32",
179 apbc_base + APBC_KPC, 10, 0, &clk_lock);
180 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
181
182 clk = mmp_clk_register_apbc("rtc", "clk32",
183 apbc_base + APBC_RTC, 10, 0, &clk_lock);
184 clk_register_clkdev(clk, NULL, "sa1100-rtc");
185
186 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
187 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
188 clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
189
190 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
191 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
192 clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
193
194 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
195 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
196 clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
197
198 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
199 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
200 clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
201
202 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
203 ARRAY_SIZE(uart_parent),
204 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
205 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
206 clk_set_parent(clk, uart_pll);
207 clk_register_clkdev(clk, "uart_mux.0", NULL);
208
209 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
210 apbc_base + APBC_UART0, 10, 0, &clk_lock);
211 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
212
213 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
214 ARRAY_SIZE(uart_parent),
215 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
216 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
217 clk_set_parent(clk, uart_pll);
218 clk_register_clkdev(clk, "uart_mux.1", NULL);
219
220 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
221 apbc_base + APBC_UART1, 10, 0, &clk_lock);
222 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
223
224 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
225 ARRAY_SIZE(uart_parent),
226 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
227 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
228 clk_set_parent(clk, uart_pll);
229 clk_register_clkdev(clk, "uart_mux.2", NULL);
230
231 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
232 apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
233 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
234
235 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
236 ARRAY_SIZE(ssp_parent),
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
239 clk_register_clkdev(clk, "uart_mux.0", NULL);
240
241 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
242 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
243 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
244
245 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
246 ARRAY_SIZE(ssp_parent),
247 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
248 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
249 clk_register_clkdev(clk, "ssp_mux.1", NULL);
250
251 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
252 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
253 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
254
255 clk = mmp_clk_register_apmu("dfc", "pll1_4",
256 apmu_base + APMU_DFC, 0x19b, &clk_lock);
257 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
258
259 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
260 ARRAY_SIZE(sdh_parent),
261 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
262 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
263 clk_register_clkdev(clk, "sdh0_mux", NULL);
264
265 clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
266 apmu_base + APMU_SDH0, 0x1b, &clk_lock);
267 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
268
269 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
270 ARRAY_SIZE(sdh_parent),
271 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
272 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
273 clk_register_clkdev(clk, "sdh1_mux", NULL);
274
275 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
276 apmu_base + APMU_SDH1, 0x1b, &clk_lock);
277 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
278
279 clk = mmp_clk_register_apmu("usb", "usb_pll",
280 apmu_base + APMU_USB, 0x9, &clk_lock);
281 clk_register_clkdev(clk, "usb_clk", NULL);
282
283 clk = mmp_clk_register_apmu("sph", "usb_pll",
284 apmu_base + APMU_USB, 0x12, &clk_lock);
285 clk_register_clkdev(clk, "sph_clk", NULL);
286
287 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
288 ARRAY_SIZE(disp_parent),
289 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
290 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
291 clk_register_clkdev(clk, "disp_mux.0", NULL);
292
293 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
294 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
295 clk_register_clkdev(clk, NULL, "mmp-disp.0");
296
297 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
298 ARRAY_SIZE(ccic_parent),
299 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
300 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
301 clk_register_clkdev(clk, "ccic_mux.0", NULL);
302
303 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
304 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
305 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
306
307 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
308 ARRAY_SIZE(ccic_phy_parent),
309 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
310 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
311 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
312
313 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
314 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
315 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
316
317 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
318 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
319 10, 5, 0, &clk_lock);
320 clk_register_clkdev(clk, "sphyclk_div", NULL);
321
322 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
323 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
324 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
325 }
326